C28x / F29x Crystal Oscillator Selection Tool — SDAA503

MCU Crystal Oscillator Selection Tool — C28x/F29x Real-Time MCUs or Other MCUs

SDAA503 • Pierce Oscillator Design Process (Steps 1–5) • Generic First-Principles Derivation

Crystal & Circuit Parameters (Use per Section 4 of SDAA503 - for devices with ESR and CL requirements)
(edit to recalculate all steps)

Ω — from crystal datasheet
pF — crystal manufacturer's load cap
pF — max 7 pF per C28x/F29x datasheet
µW — from crystal datasheet
pF — typically 3–5 pF compact layout
V — Vpp ≈ VDD
1

Verify ESR Meets Oscillator Requirements

—
ESR_max = Rneg_min / 3     (Table 3-1 — C28x/F29x specific)
Interpolation for CL1 between 12 and 24 pF columns (Eq 2):
ESR_max(CL1) = ESR_max_12 + (ESR_max_24 − ESR_max_12) × (CL1 − 12) / 12
Check: Crystal ESR ≤ ESR_max(CL1)
Freq (MHz)Max ESR — CL1=CL2=12 pF (Ω)Max ESR — CL1=CL2=24 pF (Ω)
1055110
125095
145090
164575
184565
204550
Crystal ESR (input)
—
ESR_max (12 pF column)
—
ESR_max (24 pF column)
—
ESR_max (applied limit)
—
Verdict (—)
—
Note: ESR increases at cold temperatures. For automotive (AEC-Q100 Grade 1), target 20–30% below the applied limit. When the applied limit is interpolated (CL1 between the two table columns), the result is an estimate between characterized data points — apply a 15–20% additional guard band. ESR failure cannot be corrected by any external component — select a different crystal. If Table 3-1 data is not available for your oscillator, use the Generic Derivation section below to compute ESR_max from first principles.
2

Size Load Capacitors CL1 and CL2

—
CL_effective = CL1/2 + C_stray   (Eq 4, CL1 = CL2)
CL1 = CL2 = 2 × (CL_effective − C_stray)   (Eq 5)
Target CL (crystal spec)
—
C_stray (estimated)
—
Calculated CL1 = CL2
—
CL effective (verify)
—
Within 12–24 pF range?
—
Note: Use C0G (NP0) dielectric for CL1/CL2. Nearest standard values: 12, 15, 18, 22, 24 pF. Higher CL pulls frequency down; lower CL pulls it up (~<10 ppm effect). C0 must be ≤ 7 pF per C28x/F29x device datasheet.
3

Estimate Crystal Drive Level — Is Rd Required?

—
C_total = CL1/2 + C_stray   (pF)
DL_estimated = ( ESR × (π × f × C_total × Vpp)² ) / 2   (Eq 6, µW)

Rd NOT required if: DL_estimated ≤ DL_max
Rd REQUIRED if: DL_estimated > DL_max
C_total = CL1/2 + C_stray
—
DL_estimated
—
Crystal DL_max
—
Rd Required?
—
Note: This is an estimate using peak-voltage approximation (Vpp ≈ VDD). Direct measurement with an active differential probe (<1 pF) on hardware is required for final validation.
4

Calculate Dampening Resistor Rd

—
P_XTAL = I_rms² × ESR   (Eq 7)
P_Rd = I_rms² × Rd   (Eq 8)
I_rms = (V_pk_Rd / √2) / Rd   (Eq 9)

Rd_estimate = ESR × ( DL_estimated / (0.7 × DL_max) − 1 )   (Eq 10)
DL_estimated / (0.7 × DL_max)
—
Rd_estimate (analytical)
—
Nearest E24 value
—

Empirical Rd verification (Method 2): Measure V_pk across Rd with active probe, then:

I_rms = (V_pk_Rd / √2) / Rd
P_XTAL = I_rms² × ESR
If P_XTAL > DL_max → increase Rd; repeat.

Quick-check: crystal power with chosen Rd

V — active probe; blank = estimate from Vpp
I_rms
—
P_XTAL (with Rd)
—
P_XTAL vs DL_max
—
Caution: Rd reduces Rneg. After setting Rd, always perform Step 5 Rneg verification. Use active probe (<1 pF) — passive probes (10–15 pF) will corrupt measurements.
5

Verify Negative Resistance (Rneg) Margin

—
Rneg ≥ 3 × ESR     (minimum)        (Eq 11)
Rneg ≥ 5 × ESR     (automotive recommended)

ESR_max_allowed = Rneg_typical / 3   (Eq 12)
Rneg_measured = Rx_stop + ESR_actual   (empirical test, Section 6.4)
Ω — read from Rneg vs CL curve at target freq & C0
Ω — potentiometer value when oscillation stopped
Crystal ESR
—
ESR_max_allowed = Rneg/3
—
Rneg / ESR margin
—
Margin verdict
—
Empirical test: Insert pot Rx in series at X2, monitor XCLKOUT, increase Rx from 0 until oscillation stops → Rneg = Rx_stop + ESR.
Perform at room temp AND lowest operating temperature. Rneg decreases at low VDD and high temp.

Bill of Materials Summary

ReferenceComponentValueNotes
XTAL1 Quartz Crystal — Fundamental mode; verify ESR at min operating temp
CL1 Load Capacitor (X1 side) — C0G/NP0 dielectric; 0402, 50V
CL2 Load Capacitor (X2 side) — C0G/NP0 dielectric; 0402, 50V
Rd Dampening Resistor — Series with X2 pin; 0402; adjust empirically

Generic Pierce Oscillator — First-Principles Derivation
(Use per Appendix A of SDAA503 - for device datasheets with limited oscillator parameters)

Use this section when the oscillator does not provide a pre-tabulated ESR / CL requirement table (e.g. non-C28x/F29x devices, custom oscillator circuits, or early-stage design). Derive ESR_max, CL_max, and a custom frequency table from the inverter transconductance.

A Pierce oscillator sustains oscillation when the inverter negative resistance (Rneg) exceeds the effective crystal resistance (ESR_eff). Rneg is set by the inverter transconductance (gm) and the feedback capacitors. When the oscillator datasheet does not tabulate this, gm can be measured empirically on hardware or estimated from operating conditions.

Eq 13   ω = 2π × f
Eq 14   Rneg = gm_min / (ω² × CL1 × CL2)                       [Ω, CL in Farads]
Eq 16   ESR_max = Rneg / margin                               [margin = 3 standard, 5 automotive]
Eq 17   CL_max = √(gm_min / (margin × Rm × ω²)) − C0   [pF, uses Rm not ESR — see Eq 1]
Eq 27   gm_equiv = Rneg_meas × ω² × CL1 × CL2              [back-calc from empirical test]
Eq 32   Δf [ppm] = Cm / (2 × (C0 + CL)) × 10⁶              [pulling from series resonance]
Eq 33   Δf_dev [ppm] = (Cm/2) × (1/(C0+CL_nom) − 1/(C0+CL_actual)) × 10⁶
Eq 17 uses Rm (motional resistance), not ESR. Rm and ESR differ when C0 is not negligible relative to CL: ESR = Rm × (1 + C0/CL)² per Eq 1. If the crystal datasheet only gives ESR at a specific CL, enter that CL as CL_nom to back-calculate Rm = ESR / (1 + C0/CL_nom)². The CL_max result is the maximum external load capacitor value that still satisfies the Rneg margin.
Oscillator & Crystal Inputs
µA/V — worst-case (min VDD, max temp, slow process)
Ω — blank: derived from ESR at CL_spec via Eq 1
fF — from crystal datasheet (enables frequency pulling)
MHz — use for fixed-freq oscillators (e.g. 40 MHz)
pF — lower CL column in generated table
pF — upper CL column in generated table
Derivation Method
A — Known gm (datasheet)
B — Empirical back-calculate
C — Frequency pulling
Method A — Required Components & Documentation
Crystal (mandatory)
  • Fundamental-mode quartz crystal at target frequency
  • Datasheet must state: ESR (or Rm), C0, rated CL
  • C0 ≤ 7 pF recommended for adequate Rneg margin
  • Cm and Rm preferred — enables exact Eq 17; if only ESR given, tool back-calculates Rm
  • Overtone-mode crystals are not compatible with a Pierce inverter
Passive components (if board validation planned)
  • CL1, CL2: C0G/NP0, ±1% or better, 0402, 50 V — values per oscillator CL spec
  • Do not use X7R or Y5V — capacitance shifts with temperature
Oscillator documentation (mandatory)
  • Device datasheet or TRM with one of:
    • gm_min — minimum transconductance (µA/V or mA/V)
    • Rneg vs. CL graph — read Rneg at worst-case CL, solve for gm via Eq 14
    • Critical gain (gm_crit) or oscillator gain parameter
  • If none available: use Method B (empirical) instead
Test equipment (calculation-only — none required)
  • No oscilloscope, probe, or signal generator needed for pure calculation
  • Optional: PCB for empirical Rneg confirmation (Step 5)
ω (at target freq)
—
Rneg at design point
—
ESR_max derived (Eq 16)
—
Crystal ESR vs limit
—
CL_max (Eq 17)
—
Rneg/ESR margin
—
Single-frequency oscillators (e.g., 40 MHz): Enter the fixed frequency in "Target frequency override" above and check "Fixed-frequency oscillator." The generated table will show only that frequency. Note that Rneg scales as 1/ω² — at 40 MHz, Rneg is ~4× lower than at 20 MHz for the same gm and CL, so ESR requirements are substantially tighter.
Method B — Required Components & Equipment
Crystal and PCB (mandatory)
  • Candidate crystal soldered to X1/X2 on engineering or production board
  • Production CL1, CL2 (C0G/NP0) installed at intended design values
  • Rd = 0 Ω (short) or DNP for this measurement
  • XCLKOUT pin exposed at a test point or jumper header
  • Do not use X7R/Y5V for CL1/CL2 — capacitance error shifts gm_equiv result
Series potentiometer Rx (mandatory)
  • Value: 200–500 Ω total, linear taper
  • Type: cermet or wirewound trimmer (e.g. Bourns 3296W-201 or 3296W-501)
  • Lead length ≤ 5 mm from X2 pad; stray capacitance < 1 pF
  • Position: between X2 device pin and crystal/CL2 node (outside CL2)
  • Do NOT use carbon-composition pots above 10 MHz — 2–5 pF parasitic capacitance
Test equipment (mandatory)
  • Oscilloscope: bandwidth ≥ 5× f_osc (e.g. ≥ 200 MHz for 40 MHz crystal)
  • Active differential probe: input cap < 1 pF, BW ≥ 5× f_osc
    • Tektronix P6247/P6248 (1 GHz, 0.9 pF)
    • Keysight N2795A (1 GHz, <0.5 pF)
  • NEVER use passive 10× probes on X1/X2 — 10–15 pF stops oscillation
  • Precision multimeter, 4-wire Kelvin: measure Rx_stop accurately
  • DC supply: low noise (<10 mV ripple), set to minimum VDD
  • Automotive: add temperature chamber −40 to +125 °C, ±2 °C; repeat at min VDD
Signal generator (crystal substitute — limited use)
  • Sinusoidal, 50 Ω output, level 100–500 mV — connect to X1 via 50 Ω series resistor
  • Use only when crystal is unavailable for initial gm screening
  • Results may differ from crystal-driven value by up to 30% — validate with actual crystal before design freeze
Signal Generator in Lieu of Crystal (Appendix A.4.2): A sinusoidal generator at the target frequency (50 Ω source, 100–500 mV) connected to X1 can substitute for the crystal when hardware is unavailable. Insert Rx at X2; increase until XCLKOUT stops. However, the generator provides a purely resistive drive — it does not replicate the crystal's LC-tank phase shift. The resulting gm_equiv may be off by up to 30%. Use for pre-silicon screening only; always re-validate with the actual crystal before design freeze.
Ω — also available from Step 5 result above
pF — external cap value at time of Rneg measurement
gm_equiv (Eq 27)
—
Rneg predicted (gm_equiv)
—
ESR_max from gm_equiv
—
CL_max from gm_equiv
—
Corner coverage: gm_equiv from a single measurement reflects one voltage/temperature/process corner. For a conservative gm_min, repeat at minimum VDD and maximum operating temperature. Use the lowest gm_equiv across all corners — this value populates the generated table.

Alternative gm Derivation — CL Sweep (Eq 28/29, no Rx needed)

Swap in progressively larger C0G/NP0 load caps (same value both sides) until oscillation stops. CL_crit is the last value where oscillation was sustained. No series resistor or active probe required — only the precision capacitor kit from Method C.

gm = ESR × ω² × CL_crit²   (Eq 28)
Margin = (CL_crit / CL_design)²   (Eq 29)
3× pass: CL_crit ≥ 1.73 × CL_design    5× (auto): CL_crit ≥ 2.24 × CL_design
pF — install equal CL1=CL2, increase until XCLKOUT stops

Alternative gm Derivation — VDD Sweep (Eq 30/31)

At maximum operating temperature, reduce VDD until oscillation stops. gm at VDD_crit equals the critical transconductance. Margin at VDD_min is estimated from the VDD ratio. Accurate PSU, no PCB modification required.

gm(VDD_crit) = ESR × ω² × CL_design²   (Eq 30)
Margin_est ≈ VDD_min / VDD_crit   (Eq 31, first-order linear approx.)
V — ramp down at max temp until XCLKOUT stops
Best practice: For gm_min, perform the Rx series sweep (top of this panel) simultaneously at VDD_min and T_max. That single measurement captures all three worst-case corners (process, voltage, temperature) without approximation.
Method C — Required Components & Equipment
Crystal with BVD model (mandatory)
  • Same candidate crystal as the design
  • BVD parameter Cm (motional capacitance) required — typically in fF
  • Source 1: crystal manufacturer characterization sheet — request by part number
  • Source 2: measure with impedance analyzer (see below)
  • Cm varies part-to-part; use manufacturer's typical or maximum value for worst-case pulling
Impedance analyzer (if Cm not in datasheet)
  • Keysight E4990A, E4991B, or Zurich Instruments MFIA
  • Crystal fixture: low-parasitic SMD holder, stray inductance < 5 nH (Keysight 16092A or custom)
  • Calibrate with SOLT at crystal fixture reference plane
  • Do NOT use a basic LCR meter — crystal Q is too high for bridge-type instruments
Precision capacitor kit (for empirical verification)
  • C0G/NP0 dielectric only
  • Values: 8, 10, 12, 15, 18, 22, 24, 27, 33 pF — cover full oscillator CL range
  • Tolerance: ±0.5% or better (±1% acceptable if accuracy requirement > 20 ppm)
  • Package: 0402; solder into CL1/CL2 pads for each data point
Frequency measurement
  • Frequency counter: resolution ≤ 1 Hz (e.g. Keysight 53220A)
  • Connect to XCLKOUT GPIO — non-invasive; do not probe X1/X2 directly
  • Gate time ≥ 100 ms for 10 Hz resolution; ≥ 1 s for 1 Hz resolution
  • Allow ≥ 5 min thermal stabilization after each cap swap before recording frequency

When the motional capacitance Cm is known (from the crystal manufacturer's BVD model or impedance characterization), predict the frequency offset from series resonance (Eq 32) and the deviation from rated frequency when using a different load cap (Eq 33).

Enter Cm in the inputs above to enable this calculation.
Generated ESR Limit & CL Boundary Table (Equivalent of Table 3-1)

Computed from gm_min (Method A) or gm_equiv (Method B if Rneg_measured is entered). Each row shows the maximum allowable crystal ESR and the maximum external CL1=CL2 value that preserves the required Rneg margin at that frequency.

Freq (MHz) Rneg @ CL=12 pF (Ω) ESR_max (Ω) Rneg @ CL=24 pF (Ω) ESR_max (Ω) CL_max for design ESR (pF)
How to read this table: ESR_max columns give the maximum crystal ESR that the oscillator can sustain at the specified frequency and CL, with the required safety margin. CL_max is the largest load cap that still satisfies Rneg ≥ margin × ESR for the crystal entered above. Values below 1 Ω or negative CL_max indicate the margin cannot be met — choose a crystal with lower ESR or reduce CL.