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Summary of Differences

Below displays a summary of all driverlib changes described in this report.
Device 1 (D1) - C2000Ware 4.03.00.00\f2837xd
Device 2 (D2) - C2000Ware 4.03.00.00\f280013x

*DNE = Does Not Exist

adc

    Enumeration Differences

Type	f2837xd	f280013x	Description
ADC_Channel	ADC_CH_ADCIN0_ADCIN1	-	differential, ADCIN0 and ADCIN1
ADC_Channel	ADC_CH_ADCIN2_ADCIN3	-	differential, ADCIN2 and ADCIN3
ADC_Channel	ADC_CH_ADCIN4_ADCIN5	-	differential, ADCIN4 and ADCIN5
ADC_Channel	ADC_CH_ADCIN6_ADCIN7	-	differential, ADCIN6 and ADCIN7
ADC_Channel	ADC_CH_ADCIN8_ADCIN9	-	differential, ADCIN8 and ADCIN9
ADC_Channel	ADC_CH_ADCIN10_ADCIN11	-	differential, ADCIN10 and ADCIN11
ADC_Channel	ADC_CH_ADCIN12_ADCIN13	-	differential, ADCIN12 and ADCIN13
ADC_Channel	ADC_CH_ADCIN14_ADCIN15	-	differential, ADCIN14 and ADCIN15
ADC_Channel	-	ADC_CH_ADCIN16	ADCIN16 is converted
ADC_Channel	-	ADC_CH_ADCIN17	ADCIN17 is converted
ADC_Channel	-	ADC_CH_ADCIN18	ADCIN18 is converted
ADC_Channel	-	ADC_CH_ADCIN19	ADCIN19 is converted
ADC_Channel	-	ADC_CH_ADCIN20	ADCIN20 is converted
ADC_ClkPrescale	ADC_CLK_DIV_2_5	-	ADCCLK = (input clock) / 2.5
ADC_ClkPrescale	ADC_CLK_DIV_3_5	-	ADCCLK = (input clock) / 3.5
ADC_ClkPrescale	ADC_CLK_DIV_4_5	-	ADCCLK = (input clock) / 4.5
ADC_ClkPrescale	ADC_CLK_DIV_5_5	-	ADCCLK = (input clock) / 5.5
ADC_ClkPrescale	ADC_CLK_DIV_6_5	-	ADCCLK = (input clock) / 6.5
ADC_ClkPrescale	ADC_CLK_DIV_7_5	-	ADCCLK = (input clock) / 7.5
ADC_ClkPrescale	ADC_CLK_DIV_8_5	-	ADCCLK = (input clock) / 8.5
ADC_Resolution	ADC_RESOLUTION_12BIT	-	12-bit conversion resolution
ADC_Resolution	ADC_RESOLUTION_16BIT	-	16-bit conversion resolution
ADC_SignalMode	ADC_MODE_SINGLE_ENDED	-	Sample on single pin with VREFLO
ADC_SignalMode	ADC_MODE_DIFFERENTIAL	-	Sample on pair of pins
ADC_Trigger	ADC_TRIGGER_EPWM8_SOCA	-	ePWM8, ADCSOCA
ADC_Trigger	ADC_TRIGGER_EPWM8_SOCB	-	ePWM8, ADCSOCB
ADC_Trigger	ADC_TRIGGER_EPWM9_SOCA	-	ePWM9, ADCSOCA
ADC_Trigger	ADC_TRIGGER_EPWM9_SOCB	-	ePWM9, ADCSOCB
ADC_Trigger	ADC_TRIGGER_EPWM10_SOCA	-	ePWM10, ADCSOCA
ADC_Trigger	ADC_TRIGGER_EPWM10_SOCB	-	ePWM10, ADCSOCB
ADC_Trigger	ADC_TRIGGER_EPWM11_SOCA	-	ePWM11, ADCSOCA
ADC_Trigger	ADC_TRIGGER_EPWM11_SOCB	-	ePWM11, ADCSOCB
ADC_Trigger	ADC_TRIGGER_EPWM12_SOCA	-	ePWM12, ADCSOCA
ADC_Trigger	ADC_TRIGGER_EPWM12_SOCB	-	ePWM12, ADCSOCB
ADC_Trigger	ADC_TRIGGER_CPU2_TINT0	-	CPU2 Timer 0, TINT0
ADC_Trigger	ADC_TRIGGER_CPU2_TINT1	-	CPU2 Timer 1, TINT1
ADC_Trigger	ADC_TRIGGER_CPU2_TINT2	-	CPU2 Timer 2, TINT2

    Register Differences

f2837xd	f280013x	Description
CTL2.RESOLUTION	-	SOC Conversion Resolution
CTL2.SIGNALMODE	-	SOC Signaling Mode
INLTRIM1	-	ADC Linearity Trim 1 Register
INLTRIM4	-	ADC Linearity Trim 4 Register
INLTRIM5	-	ADC Linearity Trim 5 Register
INLTRIM6	-	ADC Linearity Trim 6 Register
-	PPB1CONFIG.CBCEN	Cycle By Cycle Enable
-	PPB2CONFIG.CBCEN	Cycle By Cycle Enable
-	PPB3CONFIG.CBCEN	Cycle By Cycle Enable
-	PPB4CONFIG.CBCEN	Cycle By Cycle Enable
-	INTCYCLE	ADC Early Interrupt Generation Cycle

    ADC_setMode

    ADC_setINLTrim

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	ADC_Resolution resolution;
		2	+	uint16_t i;
		3	+	uint32_t * inlTrimAddress;
	3	4
	4	5		//
	5	6		// Check the arguments.
	6	7		//
	7	8		ASSERT(ADC_isBaseValid(base));
	8	9
n	9		-	resolution = (ADC_Resolution)
		10	+	if(TI_OTP_DEV_PRG_KEY == TI_OTP_DEV_KEY)
	10		-	(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION);
		11	+	{
		12	+	switch(base)
		13	+	{
		14	+	case ADCA_BASE:
		15	+	inlTrimAddress = ADC_getINLTrimOTPLoc(0U);
		16	+	break;
		17	+	case ADCC_BASE:
		18	+	inlTrimAddress = ADC_getINLTrimOTPLoc(1U);
		19	+	break;
		20	+	default:
		21	+	//
		22	+	// Invalid base address!
		23	+	//
		24	+	inlTrimAddress = ADC_getINLTrimOTPLoc(0U);
		25	+	break;
		26	+	}
	11	27
		28	+	//
		29	+	// Update INL trim values to ADC trim registers
		30	+	//
	12		-	EALLOW;
		31	+	EALLOW;
	13		-	switch(base)
		32	+	for(i = 0U; i < 4U; i += 2U)
	14		-	{
	15		-	case ADCA_BASE:
	16		-	if(HWREGH(ADC_calADCAINL) != 0xFFFFU)
	17		-	{
		33	+	{
	18		-	//
	19		-	// Trim function is programmed into OTP, so call it
	20		-	//
	21		-	(*((void (*)(void))ADC_calADCAINL))();
	22		-	}
	23		-	else
	24		-	{
	25		-	//
	26		-	// Do nothing, no INL trim function populated
	27		-	//
	28		-	}
	29		-	break;
	30		-	case ADCB_BASE:
	31		-	if(HWREGH(ADC_calADCBINL) != 0xFFFFU)
	32		-	{
	33		-	//
	34		-	// Trim function is programmed into OTP, so call it
	35		-	//
	36		-	(*((void (*)(void))ADC_calADCBINL))();
	37		-	}
	38		-	else
	39		-	{
	40		-	//
	41		-	// Do nothing, no INL trim function populated
	42		-	//
	43		-	}
	44		-	break;
	45		-	case ADCC_BASE:
	46		-	if(HWREGH(ADC_calADCCINL) != 0xFFFFU)
	47		-	{
	48		-	//
	49		-	// Trim function is programmed into OTP, so call it
	50		-	//
	51		-	(*((void (*)(void))ADC_calADCCINL))();
	52		-	}
	53		-	else
	54		-	{
	55		-	//
	56		-	// Do nothing, no INL trim function populated
	57		-	//
	58		-	}
	59		-	break;
	60		-	case ADCD_BASE:
	61		-	if(HWREGH(ADC_calADCDINL) != 0xFFFFU)
	62		-	{
	63		-	//
	64		-	// Trim function is programmed into OTP, so call it
	65		-	//
	66		-	(*((void (*)(void))ADC_calADCDINL))();
	67		-	}
	68		-	else
	69		-	{
	70		-	//
	71		-	// Do nothing, no INL trim function populated
	72		-	//
	73		-	}
	74		-	break;
	75		-	default:
	76	34		//
n	77		-	// Invalid base address! Do nothing!
		35	+	// 32-bit writes are performed since the OTP source is word aligned.
	78	36		//
n	79		-	break;
		37	+	HWREG(base + ADC_O_INLTRIM2 + i) = (*inlTrimAddress++);
		38	+	}
		39	+	EDIS;
	80	40		}
n	81		-
	82		-	//
	83		-	// Apply linearity trim workaround for 12-bit resolution
	84		-	//
	85		-	if(resolution == ADC_RESOLUTION_12BIT)
	86		-	{
	87		-	//
	88		-	// 12-bit linearity trim workaround
	89		-	//
	90		-	HWREG(base + ADC_O_INLTRIM1) &= 0xFFFF0000U;
	91		-	HWREG(base + ADC_O_INLTRIM2) &= 0xFFFF0000U;
	92		-	HWREG(base + ADC_O_INLTRIM4) &= 0xFFFF0000U;
	93		-	HWREG(base + ADC_O_INLTRIM5) &= 0xFFFF0000U;
	94		-	}
	95		-	EDIS;
	96	41		}
	97	42

    ADC_setOffsetTrim

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	uint16_t offsetIndex = 0U;
		2	+	uint16_t *offset;
	3		-	uint16_t offsetTrim  = 0U;
		3	+	uint32_t moduleShiftVal;
	4		-	ADC_Resolution resolution;
		4	+	uint16_t offsetShiftVal;
	5		-	ADC_SignalMode signalMode;
		5	+	uint16_t analogRefRegVal;
		6	+	ADC_ReferenceMode refMode;
		7	+	ADC_ReferenceVoltage refVoltage;
	6	8
	7	9		//
	8	10		// Check the arguments.
	9	11		//
	10	12		ASSERT(ADC_isBaseValid(base));
	11	13
n	12		-	resolution = (ADC_Resolution)
		14	+	//
	13		-	(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION);
		15	+	// Assign a shift amount corresponding to which ADC module is being
	14		-	signalMode = (ADC_SignalMode)
		16	+	// configured.
	15		-	(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_SIGNALMODE);
		17	+	//
	16		-
	17	18		switch(base)
	18	19		{
	19	20		case ADCA_BASE:
n	20		-	offsetIndex = (uint16_t)(0U * 4U);
		21	+	moduleShiftVal = 0U;
	21		-	break;
	22		-	case ADCB_BASE:
	23		-	offsetIndex = (uint16_t)(1U * 4U);
	24	22		break;
	25	23		case ADCC_BASE:
n	26		-	offsetIndex = (uint16_t)(2U * 4U);
		24	+	moduleShiftVal = 1U;
	27		-	break;
	28		-	case ADCD_BASE:
	29		-	offsetIndex = (uint16_t)(3U * 4U);
	30	25		break;
	31	26		default:
	32	27		//
n	33		-	// Invalid base address!
		28	+	// Invalid base address!!
	34	29		//
n	35		-	offsetIndex = 0U;
		30	+	moduleShiftVal = 0U;
	36	31		break;
	37	32		}
	38	33
	39	34		//
n	40		-	// Offset trim function is programmed into OTP, so call it
		35	+	// Read the Analog Reference Control Register value to determine the
		36	+	// ADC reference mode and reference voltage value.
	41	37		//
n	42		-	if(HWREGH(ADC_getOffsetTrim) != 0xFFFFU)
		38	+	analogRefRegVal = HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFCTL);
		39	+
		40	+	//
		41	+	// Calculate refMode and refVoltage based on input ADC base
		42	+	//
		43	+	refMode = (ADC_ReferenceMode)((analogRefRegVal >> moduleShiftVal) & 1U);
		44	+	refVoltage = (ADC_ReferenceVoltage)((analogRefRegVal >>
		45	+	(ADC_VOLTAGE_REF_REG_OFFSET + moduleShiftVal)) & 1U);
		46	+
		47	+	//
		48	+	// Offset trim for internal VREF 3.3V is unique and stored in upper byte.
		49	+	//
		50	+	if((refMode == ADC_REFERENCE_INTERNAL) &&
		51	+	(refVoltage == ADC_REFERENCE_3_3V))
	43	52		{
n	44		-	//
		53	+	offsetShiftVal = 8U;
	45		-	// Calculate the index into OTP table of offset trims and call
	46		-	// function to return the correct offset trim
	47		-	//
	48		-	offsetIndex += ((signalMode == ADC_MODE_DIFFERENTIAL) ? 1U : 0U) +
	49		-	(2U * ((resolution == ADC_RESOLUTION_16BIT) ? 1U : 0U));
	50		-
	51		-	offsetTrim =
	52		-	(*((uint16_t (*)(uint16_t index))ADC_getOffsetTrim))(offsetIndex);
	53	54		}
	54	55		else
	55	56		{
n	56		-	//
	57		-	// Offset trim function is not populated, so set offset trim to 0
	58		-	//
	59		-	offsetTrim = 0U;
		57	+	offsetShiftVal = 0U;
	60	58		}
	61	59
	62	60		//
n	63		-	// Apply the offset trim. Offset Trim is not updated here in case of TMX or
		61	+	// Set up pointer to offset trim in OTP.
	64		-	// untrimmed devices. The default trims for TMX devices should be handled in
	65		-	// Device_init(). Refer to Device_init() and Device_configureTMXAnalogTrim()
	66		-	// APIs for more details.
	67	62		//
n	68		-	if(offsetTrim > 0x0U)
		63	+	offset = (uint16_t *)((uint32_t)ADC_OFFSET_TRIM_OTP + moduleShiftVal);
	69		-	{
		64	+
		65	+	//
		66	+	// Get offset trim from OTP and write it to the register.
		67	+	//
	70		-	EALLOW;
		68	+	EALLOW;
	71		-	HWREGH(base + ADC_O_OFFTRIM) = offsetTrim;
		69	+	HWREGH(base + ADC_O_OFFTRIM) = (*offset >> offsetShiftVal) & 0xFFU;
	72		-	EDIS;
		70	+	EDIS;
	73		-	}
	74	71		}
	75	72

    ADC_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		return(
	3	3		(base == ADCA_BASE) ||
n	4		-	(base == ADCB_BASE) ||
	5		-	(base == ADCC_BASE) ||
	6		-	(base == ADCD_BASE)
		4	+	(base == ADCC_BASE)
	7	5		);
	8	6		}
	9	7

    ADC_readResult

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(
	6	6		(resultBase == ADCARESULT_BASE) ||
n	7		-	(resultBase == ADCBRESULT_BASE) ||
	8		-	(resultBase == ADCCRESULT_BASE) ||
	9		-	(resultBase == ADCDRESULT_BASE)
		7	+	(resultBase == ADCCRESULT_BASE)
	10	8		);
	11	9		//
	12	10		// Return the ADC result for the selected SOC.
	13	11		//
	14	12		return(HWREGH(resultBase + (uint32_t)ADC_RESULTx_OFFSET_BASE +
	15	13		(uint32_t)socNumber));
	16	14		}
	17	15

    ADC_readPPBResult

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(
	6	6		(resultBase == ADCARESULT_BASE) ||
n	7		-	(resultBase == ADCBRESULT_BASE) ||
	8		-	(resultBase == ADCCRESULT_BASE) ||
	9		-	(resultBase == ADCDRESULT_BASE)
		7	+	(resultBase == ADCCRESULT_BASE)
	10	8		);
	11	9		//
	12	10		// Return the result of selected PPB.
	13	11		//
	14	12		return((uint32_t)HWREG(resultBase + (uint32_t)ADC_PPBxRESULT_OFFSET_BASE +
	15	13		((uint32_t)ppbNumber * 2UL)));
	16	14		}
	17	15

    ADC_getTemperatureC

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	int16_t tsOffset, tsSlope;
	3	2		float32_t temp;
	4	3
	5	4		//
n	6		-	// Check the device revision
		5	+	// Read temp sensor slope and offset locations from OTP and convert
	7	6		//
n	8		-	if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3)
		7	+	temp = (float32_t)tempResult * (vref / 2.5F);
		8	+	if(refMode == ADC_REFERENCE_INTERNAL)
	9	9		{
n	10		-	//
		10	+	return((int16_t)((((int32_t)temp - ADC_INT_REF_TSOFFSET) * 4096) /
	11		-	// For production devices (Rev. C), pull the slope and offset from OTP
		11	+	ADC_INT_REF_TSSLOPE));
	12		-	//
	13		-	tsSlope = (int16_t)ADC_getTempSlope();
	14		-	tsOffset = (int16_t)ADC_getTempOffset();
	15	12		}
	16	13		else
	17	14		{
n	18		-	//
		15	+	return((int16_t)((((int32_t)temp - ADC_EXT_REF_TSOFFSET) * 4096) /
	19		-	// For pre-production devices, use these static values for slope
		16	+	ADC_EXT_REF_TSSLOPE));
	20		-	// and offset
	21		-	//
	22		-	tsSlope = 5196;
	23		-	tsOffset = 1788;
	24	17		}
n	25		-
	26		-	//
	27		-	// The slope is stored as a Q15 fixed point number hence the need to
	28		-	// to an integer.
	29		-	//
	30		-	temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) *
	31		-	(float32_t)tsSlope;
	32		-	return((int16_t)((((int32_t)temp + (int32_t)0x4000 +
	33		-	((int32_t)273 * (int32_t)0x8000)) /
	34		-	(int32_t)0x8000) - (int32_t)273));
	35	18		}
	36	19

    ADC_getTemperatureK

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	int16_t tsOffset, tsSlope;
	3	2		float32_t temp;
	4	3
	5	4		//
n	6		-	// Check the device revision
		5	+	// Read temp sensor slope and offset locations from OTP and convert
	7	6		//
n	8		-	if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3)
		7	+	temp = (float32_t)tempResult * (vref / 2.5F);
		8	+	if(refMode == ADC_REFERENCE_INTERNAL)
	9	9		{
n	10		-	//
		10	+	return((int16_t)(((((int32_t)temp - ADC_INT_REF_TSOFFSET) * 4096) /
	11		-	// For production devices (Rev. C), pull the slope and offset from OTP
		11	+	ADC_INT_REF_TSSLOPE) + 273));
	12		-	//
	13		-	tsSlope = (int16_t)ADC_getTempSlope();
	14		-	tsOffset = (int16_t)ADC_getTempOffset();
	15	12		}
	16	13		else
	17	14		{
n	18		-	//
		15	+	return((int16_t)(((((int32_t)temp - ADC_EXT_REF_TSOFFSET) * 4096) /
	19		-	// For pre-production devices, use these static values for slope
		16	+	ADC_EXT_REF_TSSLOPE) + 273));
	20		-	// and offset
	21		-	//
	22		-	tsSlope = 5196;
	23		-	tsOffset = 1788;
	24	17		}
n	25		-
	26		-	//
	27		-	// The slope is stored as a Q15 fixed point number hence the need to
	28		-	// to an integer.
	29		-	//
	30		-	temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) *
	31		-	(float32_t)tsSlope;
	32		-	return((int16_t)(((int32_t)temp + (int32_t)0x4000 + ((int32_t)273 *
	33		-	(int32_t)0x8000)) / (int32_t)0x8000));
	34	18		}
	35	19

    ADC_setVREF

    ADC_setOffsetTrimAll

    ADC_setInterruptCycleOffset

    ADC_enablePPBEventCBCClear

    ADC_disablePPBEventCBCClear

asysctl

    Register Differences

f2837xd	f280013x	Description
INTOSC1TRIM	-	Internal Oscillator 1 Trim Register
INTOSC1TRIM.VALFINETRIM	-	Oscillator Value Fine Trim Bits
INTOSC2TRIM	-	Internal Oscillator 2 Trim Register
INTOSC2TRIM.VALFINETRIM	-	Oscillator Value Fine Trim Bits
LOCK.ANAREFTRIMA	-	Analog Reference A Trim Register Lock
LOCK.ANAREFTRIMB	-	Analog Reference B Trim Register Lock
LOCK.ANAREFTRIMC	-	Analog Reference C Trim Register Lock
LOCK.ANAREFTRIMD	-	Analog Reference D Trim Register Lock
ANAREFTRIMA	-	Analog Reference Trim A Register
ANAREFTRIMA.BGVALTRIM	-	Bandgap Value Trim
ANAREFTRIMA.BGSLOPETRIM	-	Bandgap Slope Trim
ANAREFTRIMA.IREFTRIM	-	Reference Current Trim
ANAREFTRIMB	-	Analog Reference Trim B Register
ANAREFTRIMB.BGVALTRIM	-	Bandgap Value Trim
ANAREFTRIMB.BGSLOPETRIM	-	Bandgap Slope Trim
ANAREFTRIMB.IREFTRIM	-	Reference Current Trim
ANAREFTRIMC	-	Analog Reference Trim C Register
ANAREFTRIMC.BGVALTRIM	-	Bandgap Value Trim
ANAREFTRIMC.BGSLOPETRIM	-	Bandgap Slope Trim
ANAREFTRIMC.IREFTRIM	-	Reference Current Trim
ANAREFTRIMD	-	Analog Reference Trim D Register
ANAREFTRIMD.BGVALTRIM	-	Bandgap Value Trim
ANAREFTRIMD.BGSLOPETRIM	-	Bandgap Slope Trim
ANAREFTRIMD.IREFTRIM	-	Reference Current Trim
-	EXTROSCCSR1	ExtR Oscillator Status Register
-	EXTROSCCSR1.OSCSTATUS	Running status of ExtR.
-	CONFIGLOCK	Lock Register for all the config registers.
-	CONFIGLOCK.AGPIOCTRL	Locks all AGPIOCTRL Register
-	ANAREFCTL	Analog Reference Control Register. This register is
-	ANAREFCTL.ANAREFSEL	Analog Reference Select
-	ANAREFCTL.ANAREF2P5SEL	Analog Reference Select
-	ANAREFCTL.ANAREFSEL_SUP_OVERRIDE	Control for overriding the analog
-	VMONCTL	Voltage Monitor Control Register
-	VMONCTL.BORLVMONDIS	Disable BORL(ow) feature on VDDIO
-	CMPHPMXSEL	Bits to select one of the many sources on CompHP
-	CMPHPMXSEL.CMP1HPMXSEL	CMP1HPMXSEL bits
-	CMPHPMXSEL.CMP2HPMXSEL	CMP2HPMXSEL bits
-	CMPHPMXSEL.CMP3HPMXSEL	CMP3HPMXSEL bits
-	CMPHPMXSEL.CMP4HPMXSEL	CMP4HPMXSEL bits
-	CMPLPMXSEL	Bits to select one of the many sources on CompLP
-	CMPLPMXSEL.CMP1LPMXSEL	CMP1LPMXSEL bits
-	CMPLPMXSEL.CMP2LPMXSEL	CMP2LPMXSEL bits
-	CMPLPMXSEL.CMP3LPMXSEL	CMP3LPMXSEL bits
-	CMPLPMXSEL.CMP4LPMXSEL	CMP4LPMXSEL bits
-	CMPHNMXSEL	Bits to select one of the many sources on CompHN
-	CMPHNMXSEL.CMP1HNMXSEL	CMP1HNMXSEL bits
-	CMPHNMXSEL.CMP2HNMXSEL	CMP2HNMXSEL bits
-	CMPHNMXSEL.CMP3HNMXSEL	CMP3HNMXSEL bits
-	CMPHNMXSEL.CMP4HNMXSEL	CMP4HNMXSEL bits
-	CMPLNMXSEL	Bits to select one of the many sources on CompLN
-	CMPLNMXSEL.CMP1LNMXSEL	CMP1LNMXSEL bits
-	CMPLNMXSEL.CMP2LNMXSEL	CMP2LNMXSEL bits
-	CMPLNMXSEL.CMP3LNMXSEL	CMP3LNMXSEL bits
-	CMPLNMXSEL.CMP4LNMXSEL	CMP4LNMXSEL bits
-	ADCDACLOOPBACK	Enabble loopback from DAC to ADCs
-	ADCDACLOOPBACK.ENLB2ADCA	Enable DACA loopback to ADCA
-	ADCDACLOOPBACK.ENLB2ADCC	Enable DACA loopback to ADCC
-	ADCDACLOOPBACK.KEY	Key to enable writes
-	CMPSSCTL	CMPSS Control Register
-	CMPSSCTL.CMP1LDACOUTEN	Enable general purpose DAC functionality for
-	CMPSSCTL.CMPSSCTLEN	Enable the CMPSSCTL Register
-	LOCK.ANAREFCTL	ANAREFCTL Register lock bit
-	LOCK.VMONCTL	VMONCTL Register lock bit
-	LOCK.CMPHPMXSEL	CMPHPMXSEL Register lock bit
-	LOCK.CMPLPMXSEL	CMPLPMXSEL Register lock bit
-	LOCK.CMPHNMXSEL	CMPHNMXSEL Register lock bit
-	LOCK.CMPLNMXSEL	CMPLNMXSEL Register lock bit
-	LOCK.VREGCTL	VREGCTL Register lock bit
-	LOCK.CMPSSCTL	CMPSSCTL Register lock bit
-	AGPIOCTRLA	AGPIO Control Register
-	AGPIOCTRLA.GPIO12	AGPIOCTRL for GPIO12
-	AGPIOCTRLA.GPIO13	AGPIOCTRL for GPIO13
-	AGPIOCTRLA.GPIO20	AGPIOCTRL for GPIO20
-	AGPIOCTRLA.GPIO21	AGPIOCTRL for GPIO21
-	AGPIOCTRLA.GPIO28	AGPIOCTRL for GPIO28
-	AGPIOCTRLH	AGPIO Control Register
-	AGPIOCTRLH.GPIO224	AGPIOCTRL for GPIO224
-	AGPIOCTRLH.GPIO226	AGPIOCTRL for GPIO226
-	AGPIOCTRLH.GPIO227	AGPIOCTRL for GPIO227
-	AGPIOCTRLH.GPIO228	AGPIOCTRL for GPIO228
-	AGPIOCTRLH.GPIO230	AGPIOCTRL for GPIO230
-	AGPIOCTRLH.GPIO242	AGPIOCTRL for GPIO242

    ASysCtl_setAnalogReferenceInternal

    ASysCtl_setAnalogReferenceExternal

    ASysCtl_setAnalogReference2P5

    ASysCtl_setAnalogReference1P65

    ASysCtl_selectCMPHNMux

    ASysCtl_selectCMPHNMuxValue

    ASysCtl_selectCMPLNMux

    ASysCtl_selectCMPLNMuxValue

    ASysCtl_selectCMPHPMux

    ASysCtl_selectCMPLPMux

    ASysCtl_enableCMPSSExternalDAC

    ASysCtl_disableCMPSSExternalDAC

    ASysCtl_lockANAREF

    ASysCtl_lockVMON

    ASysCtl_lockCMPHPMux

    ASysCtl_lockCMPLPMux

    ASysCtl_lockCMPHNMux

    ASysCtl_lockCMPLNMux

    ASysCtl_lockVREG

    ASysCtl_lockCMPSSCTL

    ASysCtl_getExtROscStatus

    ASysCtl_enableADCDACLoopback

    ASysCtl_disableADCDACLoopback

can

    Register Differences

f2837xd	f280013x	Description
IF3OBS	-	IF3 Observation Register
IF3OBS.MASK	-	Mask data read observation
IF3OBS.ARB	-	Arbitration data read observation
IF3OBS.CTRL	-	Ctrl read observation
IF3OBS.DATA_A	-	Data A read observation
IF3OBS.DATA_B	-	Data B read observation
IF3OBS.IF3SM	-	IF3 Status of Mask data read access
IF3OBS.IF3SA	-	IF3 Status of Arbitration data read access
IF3OBS.IF3SC	-	IF3 Status of Control bits read access
IF3OBS.IF3SDA	-	IF3 Status of Data A read access
IF3OBS.IF3SDB	-	IF3 Status of Data B read access
IF3OBS.IF3UPD	-	IF3 Update Data

    CAN_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		return(
n	3		-	(base == CANA_BASE) ||
	4		-	(base == CANB_BASE)
		3	+	(base == CANA_BASE)
	5	4		);
	6	5		}
	7	6

    CAN_selectClockSource

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CAN_isBaseValid(base));
	6	6
	7	7		//
	8	8		// Determine the CAN controller and set specified clock source
	9	9		//
	10	10		EALLOW;
	11	11
	12	12		switch(base)
	13	13		{
	14	14		case CANA_BASE:
	15	15		HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &=
	16	16		~SYSCTL_CLKSRCCTL2_CANABCLKSEL_M;
	17	17
	18	18		HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) |= ((uint16_t)source <<
	19	19		SYSCTL_CLKSRCCTL2_CANABCLKSEL_S);
	20	20		break;
	21	21
n	22		-	case CANB_BASE:
	23		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &=
	24		-	~SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M;
	25		-
	26		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) |= ((uint16_t)source <<
	27		-	SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S);
	28		-	break;
	29		-
	30	22		default:
	31	23
	32	24		//
	33	25		// Do nothing. Not a valid mode value.
	34	26		//
	35	27		break;
	36	28		}
	37	29
	38	30		EDIS;
	39	31		}
	40	32

cla

clb

clbxbar

cmpss

    Register Differences

f2837xd	f280013x	Description
COMPDACCTL	-	CMPSS DAC Control Register
COMPDACCTL.DACSOURCE	-	DAC Source Control
COMPDACCTL.RAMPSOURCE	-	Ramp Generator Source Control
COMPDACCTL.SELREF	-	DAC Reference Select
COMPDACCTL.RAMPLOADSEL	-	Ramp Load Select
COMPDACCTL.SWLOADSEL	-	Software Load Select
COMPDACCTL.FREESOFT	-	Free/Soft Emulation Bits
RAMPMAXREFA	-	CMPSS Ramp Max Reference Active Register
RAMPMAXREFS	-	CMPSS Ramp Max Reference Shadow Register
RAMPDECVALA	-	CMPSS Ramp Decrement Value Active Register
RAMPDECVALS	-	CMPSS Ramp Decrement Value Shadow Register
RAMPSTS	-	CMPSS Ramp Status Register
RAMPDLYA	-	CMPSS Ramp Delay Active Register
RAMPDLYA.DELAY	-	Ramp Delay Value
RAMPDLYS	-	CMPSS Ramp Delay Shadow Register
RAMPDLYS.DELAY	-	Ramp Delay Value
CTRIPLFILCLKCTL.CLKPRESCALE	-	Sample Clock Prescale
CTRIPHFILCLKCTL.CLKPRESCALE	-	Sample Clock Prescale
-	COMPDACHCTL	CMPSS High DAC Control Register
-	COMPDACHCTL.DACSOURCE	DAC Source Control
-	COMPDACHCTL.RAMPSOURCE	Ramp Generator Source Control
-	COMPDACHCTL.RAMPLOADSEL	Ramp Load Select
-	COMPDACHCTL.SWLOADSEL	Software Load Select
-	COMPDACHCTL.BLANKSOURCE	EPWMBLANK Source Select
-	COMPDACHCTL.BLANKEN	EPWMBLANK Enable
-	COMPDACHCTL.FREESOFT	Free/Soft Emulation Bits
-	RAMPHREFA	CMPSS High Ramp Reference Active Register
-	RAMPHREFS	CMPSS High Ramp Reference Shadow Register
-	RAMPHSTEPVALA	CMPSS High Ramp Step Value Active Register
-	RAMPHSTEPVALS	CMPSS High Ramp Step Value Shadow Register
-	RAMPHSTS	CMPSS High Ramp Status Register
-	RAMPHDLYA	CMPSS High Ramp Delay Active Register
-	RAMPHDLYA.DELAY	High Ramp Delay Value Active
-	RAMPHDLYS	CMPSS High Ramp Delay Shadow Register
-	RAMPHDLYS.DELAY	High Ramp Delay Value Shadow

    CMPSS_configFilterHigh

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint16_t regValue;
	3	3
	4	4		//
	5	5		// Check the arguments.
	6	6		//
	7	7		ASSERT(CMPSS_isBaseValid(base));
		8	+	ASSERT(samplePrescale <= 65535U);
		9	+	ASSERT((sampleWindow >= 1U) && (sampleWindow <= 32U));
	8	10		ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U));
	9	11
	10	12		//
	11	13		// Shift the sample window and threshold values into the correct positions
	12	14		// and write them to the appropriate register.
	13	15		//
	14	16		regValue = ((sampleWindow - 1U) << CMPSS_CTRIPHFILCTL_SAMPWIN_S) |
	15	17		((threshold - 1U) << CMPSS_CTRIPHFILCTL_THRESH_S);
	16	18
	17	19		EALLOW;
	18	20
	19	21		HWREGH(base + CMPSS_O_CTRIPHFILCTL) =
	20	22		(HWREGH(base + CMPSS_O_CTRIPHFILCTL) &
	21	23		~(CMPSS_CTRIPHFILCTL_SAMPWIN_M | CMPSS_CTRIPHFILCTL_THRESH_M)) |
	22	24		regValue;
	23	25
	24	26		//
	25	27		// Set the filter sample clock prescale for the high comparator.
	26	28		//
	27	29		HWREGH(base + CMPSS_O_CTRIPHFILCLKCTL) = samplePrescale;
	28	30
	29	31		EDIS;
	30	32		}
	31	33

    CMPSS_configFilterLow

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint16_t regValue;
	3	3
	4	4		//
	5	5		// Check the arguments.
	6	6		//
	7	7		ASSERT(CMPSS_isBaseValid(base));
		8	+	ASSERT(samplePrescale <= 65535U);
		9	+	ASSERT((sampleWindow >= 1U) && (sampleWindow <= 32U));
	8	10		ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U));
	9	11
	10	12		//
	11	13		// Shift the sample window and threshold values into the correct positions
	12	14		// and write them to the appropriate register.
	13	15		//
	14	16		regValue = ((sampleWindow - 1U) << CMPSS_CTRIPLFILCTL_SAMPWIN_S) |
	15	17		((threshold - 1U) << CMPSS_CTRIPLFILCTL_THRESH_S);
	16	18
	17	19		EALLOW;
	18	20
	19	21		HWREGH(base + CMPSS_O_CTRIPLFILCTL) =
	20	22		(HWREGH(base + CMPSS_O_CTRIPLFILCTL) &
	21	23		~(CMPSS_CTRIPLFILCTL_SAMPWIN_M | CMPSS_CTRIPLFILCTL_THRESH_M)) |
	22	24		regValue;
	23	25
	24	26		//
	25	27		// Set the filter sample clock prescale for the low comparator.
	26	28		//
	27	29		HWREGH(base + CMPSS_O_CTRIPLFILCLKCTL) = samplePrescale;
	28	30
	29	31		EDIS;
	30	32		}
	31	33

    CMPSS_configRamp

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
		6	+	ASSERT(!CMPSS_isLiteBaseValid(base));
	6		-	ASSERT(delayVal <= CMPSS_RAMPDLYS_DELAY_M);
		7	+	ASSERT(delayVal <= CMPSS_RAMPHDLYS_DELAY_M);
	7	8		ASSERT((pwmSyncSrc >= 1U) && (pwmSyncSrc <= 16U));
	8	9
	9	10		EALLOW;
	10	11
	11	12		//
	12	13		// Write the ramp generator source to the register
	13	14		//
n	14		-	HWREGH(base + CMPSS_O_COMPDACCTL) =
		15	+	HWREGH(base + CMPSS_O_COMPDACHCTL) =
	15		-	(HWREGH(base + CMPSS_O_COMPDACCTL) &
		16	+	(HWREGH(base + CMPSS_O_COMPDACHCTL) &
	16		-	~CMPSS_COMPDACCTL_RAMPSOURCE_M) |
		17	+	~CMPSS_COMPDACHCTL_RAMPSOURCE_M) |
	17		-	((uint16_t)(pwmSyncSrc - 1U) << CMPSS_COMPDACCTL_RAMPSOURCE_S);
		18	+	((uint16_t)(pwmSyncSrc - 1U) << CMPSS_COMPDACHCTL_RAMPSOURCE_S);
	18	19
	19	20		//
	20	21		// Set or clear the bit that determines from where the max ramp value
	21	22		// should be loaded.
	22	23		//
	23	24		if(useRampValShdw)
	24	25		{
n	25		-	HWREGH(base + CMPSS_O_COMPDACCTL) |= CMPSS_COMPDACCTL_RAMPLOADSEL;
		26	+	HWREGH(base + CMPSS_O_COMPDACHCTL) |= CMPSS_COMPDACHCTL_RAMPLOADSEL;
	26	27		}
	27	28		else
	28	29		{
n	29		-	HWREGH(base + CMPSS_O_COMPDACCTL) &= ~CMPSS_COMPDACCTL_RAMPLOADSEL;
		30	+	HWREGH(base + CMPSS_O_COMPDACHCTL) &= ~CMPSS_COMPDACHCTL_RAMPLOADSEL;
	30	31		}
	31	32
	32	33		EDIS;
	33	34
	34	35		//
	35	36		// Write the maximum ramp value to the shadow register.
	36	37		//
n	37		-	HWREGH(base + CMPSS_O_RAMPMAXREFS) = maxRampVal;
		38	+	HWREGH(base + CMPSS_O_RAMPHREFS) = maxRampVal;
	38	39
	39	40		//
	40	41		// Write the ramp decrement value to the shadow register.
	41	42		//
n	42		-	HWREGH(base + CMPSS_O_RAMPDECVALS) = decrementVal;
		43	+	HWREGH(base + CMPSS_O_RAMPHSTEPVALS) = decrementVal;
	43	44
	44	45		//
	45	46		// Write the ramp delay value to the shadow register.
	46	47		//
n	47		-	HWREGH(base + CMPSS_O_RAMPDLYS) = delayVal;
		48	+	HWREGH(base + CMPSS_O_RAMPHDLYS) = delayVal;
	48	49		}
	49	50

    CMPSS_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		return(
	3	3		(base == CMPSS1_BASE) ||
n	4		-	(base == CMPSS2_BASE) ||
		4	+	(base == CMPSSLITE2_BASE) ||
	5		-	(base == CMPSS3_BASE) ||
		5	+	(base == CMPSSLITE3_BASE) ||
	6		-	(base == CMPSS4_BASE) ||
	7		-	(base == CMPSS5_BASE) ||
	8		-	(base == CMPSS6_BASE) ||
	9		-	(base == CMPSS7_BASE) ||
	10		-	(base == CMPSS8_BASE)
		6	+	(base == CMPSSLITE4_BASE)
	11	7		);
	12	8		}
	13	9

    CMPSS_configDAC

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
	6	6
	7	7		//
	8	8		// Write the DAC configuration to the appropriate register.
	9	9		//
	10	10		EALLOW;
	11	11
n	12		-	HWREGH(base + CMPSS_O_COMPDACCTL) =
		12	+	HWREGH(base + CMPSS_O_COMPDACHCTL) = (HWREGH(base + CMPSS_O_COMPDACHCTL) &
	13		-	(HWREGH(base + CMPSS_O_COMPDACCTL) &
		13	+	~(CMPSS_COMPDACHCTL_SWLOADSEL      |
	14		-	~(CMPSS_COMPDACCTL_SWLOADSEL | CMPSS_COMPDACCTL_SELREF |
	15		-	CMPSS_COMPDACCTL_DACSOURCE)) | config;
		14	+	CMPSS_COMPDACHCTL_DACSOURCE)) | config;
	16	15
	17	16		EDIS;
	18	17		}
	19	18

    CMPSS_setMaxRampValue

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
		6	+	ASSERT(!CMPSS_isLiteBaseValid(base));
	6	7
	7	8		//
	8	9		// Write the maximum ramp value to the shadow register.
	9	10		//
n	10		-	HWREGH(base + CMPSS_O_RAMPMAXREFS) = value;
		11	+	HWREGH(base + CMPSS_O_RAMPHREFS) = value;
	11	12		}
	12	13

    CMPSS_getMaxRampValue

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
		6	+	ASSERT(!CMPSS_isLiteBaseValid(base));
	6	7
	7	8		//
	8	9		// Read the maximum ramp value from the register.
	9	10		//
n	10		-	return(HWREGH(base + CMPSS_O_RAMPMAXREFA));
		11	+	return(HWREGH(base + CMPSS_O_RAMPHREFA));
	11	12		}
	12	13

    CMPSS_setRampDecValue

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
		6	+	ASSERT(!CMPSS_isLiteBaseValid(base));
	6	7
	7	8		//
	8	9		// Write the ramp decrement value to the shadow register.
	9	10		//
n	10		-	HWREGH(base + CMPSS_O_RAMPDECVALS) = value;
		11	+	HWREGH(base + CMPSS_O_RAMPHSTEPVALS) = value;
	11	12		}
	12	13

    CMPSS_getRampDecValue

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
		6	+	ASSERT(!CMPSS_isLiteBaseValid(base));
	6	7
	7	8		//
	8	9		// Read the ramp decrement value from the register.
	9	10		//
n	10		-	return(HWREGH(base + CMPSS_O_RAMPDECVALA));
		11	+	return(HWREGH(base + CMPSS_O_RAMPHSTEPVALA));
	11	12		}
	12	13

    CMPSS_setRampDelayValue

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
		6	+	ASSERT(!CMPSS_isLiteBaseValid(base));
	6	7		ASSERT(value < 8192U);
	7	8
	8	9		//
	9	10		// Write the ramp delay value to the shadow register.
	10	11		//
n	11		-	HWREGH(base + CMPSS_O_RAMPDLYS) = value;
		12	+	HWREGH(base + CMPSS_O_RAMPHDLYS) = value;
	12	13		}
	13	14

    CMPSS_getRampDelayValue

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
		6	+	ASSERT(!CMPSS_isLiteBaseValid(base));
	6	7
	7	8		//
	8	9		// Read the ramp delay value from the register.
	9	10		//
n	10		-	return(HWREGH(base + CMPSS_O_RAMPDLYA));
		11	+	return(HWREGH(base + CMPSS_O_RAMPHDLYA));
	11	12		}
	12	13

    CMPSS_setHysteresis

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(CMPSS_isBaseValid(base));
		6	+	if(base == CMPSS1_BASE)
		7	+	{
	6		-	ASSERT(value <= 4U);
		8	+	ASSERT(value <= 4U);
		9	+	}
		10	+	else
		11	+	{
		12	+	ASSERT(value <= 7U);
		13	+	}
	7	14
	8	15		//
	9	16		// Read the ramp delay value from the register.
	10	17		//
	11	18		EALLOW;
	12	19
	13	20		HWREGH(base + CMPSS_O_COMPHYSCTL) = value;
	14	21
	15	22		EDIS;
	16	23		}
	17	24

    CMPSS_isLiteBaseValid

    CMPSS_configBlanking

    CMPSS_enableBlanking

    CMPSS_disableBlanking

cmpss_lite

cputimer

    Enumeration Differences

Type	f2837xd	f280013x	Description
CPUTimer_ClockSource	CPUTIMER_CLOCK_SOURCE_AUX	-	Auxiliary PLL Clock Source

dac

dcc

dcsm

    Enumeration Differences

Type	f2837xd	f280013x	Description
DCSM_RAMModule	-	DCSM_RAMLS6	RAMLS6
DCSM_RAMModule	-	DCSM_RAMLS7	RAMLS7
DCSM_Sector	DCSM_SECTOR_A	-	Sector A
DCSM_Sector	DCSM_SECTOR_B	-	Sector B
DCSM_Sector	DCSM_SECTOR_C	-	Sector C
DCSM_Sector	DCSM_SECTOR_D	-	Sector D
DCSM_Sector	DCSM_SECTOR_E	-	Sector E
DCSM_Sector	DCSM_SECTOR_F	-	Sector F
DCSM_Sector	DCSM_SECTOR_G	-	Sector G
DCSM_Sector	DCSM_SECTOR_H	-	Sector H
DCSM_Sector	DCSM_SECTOR_I	-	Sector I
DCSM_Sector	DCSM_SECTOR_J	-	Sector J
DCSM_Sector	DCSM_SECTOR_K	-	Sector K
DCSM_Sector	DCSM_SECTOR_L	-	Sector L
DCSM_Sector	DCSM_SECTOR_M	-	Sector M
DCSM_Sector	DCSM_SECTOR_N	-	Sector N
DCSM_Sector	-	DCSM_SECTOR_0	Sector 0
DCSM_Sector	-	DCSM_SECTOR_1	Sector 1
DCSM_Sector	-	DCSM_SECTOR_2	Sector 2
DCSM_Sector	-	DCSM_SECTOR_3	Sector 3
DCSM_Sector	-	DCSM_SECTOR_4	Sector 4
DCSM_Sector	-	DCSM_SECTOR_5	Sector 5
DCSM_Sector	-	DCSM_SECTOR_6	Sector 6
DCSM_Sector	-	DCSM_SECTOR_7	Sector 7
DCSM_Sector	-	DCSM_SECTOR_8	Sector 8
DCSM_Sector	-	DCSM_SECTOR_9	Sector 9
DCSM_Sector	-	DCSM_SECTOR_10	Sector 10
DCSM_Sector	-	DCSM_SECTOR_11	Sector 11
DCSM_Sector	-	DCSM_SECTOR_12	Sector 12
DCSM_Sector	-	DCSM_SECTOR_13	Sector 13
DCSM_Sector	-	DCSM_SECTOR_14	Sector 14
DCSM_Sector	-	DCSM_SECTOR_15	Sector 15
DCSM_Sector	-	DCSM_SECTOR_16	Sector 16
DCSM_Sector	-	DCSM_SECTOR_17	Sector 17
DCSM_Sector	-	DCSM_SECTOR_18	Sector 18
DCSM_Sector	-	DCSM_SECTOR_19	Sector 19
DCSM_Sector	-	DCSM_SECTOR_20	Sector 20
DCSM_Sector	-	DCSM_SECTOR_21	Sector 21
DCSM_Sector	-	DCSM_SECTOR_22	Sector 22
DCSM_Sector	-	DCSM_SECTOR_23	Sector 23
DCSM_Sector	-	DCSM_SECTOR_24	Sector 24
DCSM_Sector	-	DCSM_SECTOR_25	Sector 25
DCSM_Sector	-	DCSM_SECTOR_26	Sector 26
DCSM_Sector	-	DCSM_SECTOR_27	Sector 27
DCSM_Sector	-	DCSM_SECTOR_28	Sector 28
DCSM_Sector	-	DCSM_SECTOR_29	Sector 29
DCSM_Sector	-	DCSM_SECTOR_30	Sector 30
DCSM_Sector	-	DCSM_SECTOR_31	Sector 31
DCSM_Sector	-	DCSM_SECTOR_39_32	Sector 39-32
DCSM_Sector	-	DCSM_SECTOR_47_40	Sector 47-40
DCSM_Sector	-	DCSM_SECTOR_55_48	Sector 55-48
DCSM_Sector	-	DCSM_SECTOR_63_56	Sector 63-56
DCSM_Sector	-	DCSM_SECTOR_71_64	Sector 71-64
DCSM_Sector	-	DCSM_SECTOR_79_72	Sector 79-72
DCSM_Sector	-	DCSM_SECTOR_87_80	Sector 87-80
DCSM_Sector	-	DCSM_SECTOR_95_88	Sector 95-88
DCSM_Sector	-	DCSM_SECTOR_103_96	Sector 103-96
DCSM_Sector	-	DCSM_SECTOR_111_104	Sector 111-104
DCSM_Sector	-	DCSM_SECTOR_119_112	Sector 119-112
DCSM_Sector	-	DCSM_SECTOR_127_120	Sector 127-120
DCSM_SecurityStatus	-	DCSM_STATUS_BLOCKED	Blocked

    Register Differences

f2837xd	f280013x	Description
Z1OTP_CRCLOCK	-	Secure CRC Lock in Z1 OTP
Z1OTP_BOOTCTRL	-	Boot Mode in Z1 OTP
Z2OTP_CRCLOCK	-	Secure CRC Lock in Z2 OTP
Z2OTP_BOOTCTRL	-	Boot Mode in Z2 OTP
Z1_OTPSECLOCK.CRCLOCK	-	Zone1 CRC Lock.
Z1_BOOTCTRL	-	Boot Mode
Z1_BOOTCTRL.KEY	-	OTP Boot Key
Z1_BOOTCTRL.BMODE	-	OTP Boot Mode
Z1_BOOTCTRL.BOOTPIN0	-	OTP Boot Pin 0 Mapping
Z1_BOOTCTRL.BOOTPIN1	-	OTP Boot Pin 1 Mapping
Z1_GRABSECTR	-	Zone 1 Grab Flash Sectors Register
Z1_GRABSECTR.GRAB_SECTA	-	Grab Flash Sector A
Z1_GRABSECTR.GRAB_SECTB	-	Grab Flash Sector B
Z1_GRABSECTR.GRAB_SECTC	-	Grab Flash Sector C
Z1_GRABSECTR.GRAB_SECTD	-	Grab Flash Sector D
Z1_GRABSECTR.GRAB_SECTE	-	Grab Flash Sector E
Z1_GRABSECTR.GRAB_SECTF	-	Grab Flash Sector F
Z1_GRABSECTR.GRAB_SECTG	-	Grab Flash Sector G
Z1_GRABSECTR.GRAB_SECTH	-	Grab Flash Sector H
Z1_GRABSECTR.GRAB_SECTI	-	Grab Flash Sector I
Z1_GRABSECTR.GRAB_SECTJ	-	Grab Flash Sector J
Z1_GRABSECTR.GRAB_SECTK	-	Grab Flash Sector K
Z1_GRABSECTR.GRAB_SECTL	-	Grab Flash Sector L
Z1_GRABSECTR.GRAB_SECTM	-	Grab Flash Sector M
Z1_GRABSECTR.GRAB_SECTN	-	Grab Flash Sector N
Z1_GRABRAMR	-	Zone 1 Grab RAM Blocks Register
Z1_GRABRAMR.GRAB_RAM0	-	Grab RAM LS0
Z1_GRABRAMR.GRAB_RAM1	-	Grab RAM LS1
Z1_GRABRAMR.GRAB_RAM2	-	Grab RAM LS2
Z1_GRABRAMR.GRAB_RAM3	-	Grab RAM LS3
Z1_GRABRAMR.GRAB_RAM4	-	Grab RAM LS4
Z1_GRABRAMR.GRAB_RAM5	-	Grab RAM LS5
Z1_GRABRAMR.GRAB_RAM6	-	Grab RAM D0
Z1_GRABRAMR.GRAB_RAM7	-	Grab RAM D1
Z1_GRABRAMR.GRAB_CLA1	-	Grab CLA1
Z1_EXEONLYSECTR	-	Zone 1 Flash Execute_Only Sector Register
Z1_EXEONLYSECTR.EXEONLY_SECTA	-	Execute-Only Flash Sector A
Z1_EXEONLYSECTR.EXEONLY_SECTB	-	Execute-Only Flash Sector B
Z1_EXEONLYSECTR.EXEONLY_SECTC	-	Execute-Only Flash Sector C
Z1_EXEONLYSECTR.EXEONLY_SECTD	-	Execute-Only Flash Sector D
Z1_EXEONLYSECTR.EXEONLY_SECTE	-	Execute-Only Flash Sector E
Z1_EXEONLYSECTR.EXEONLY_SECTF	-	Execute-Only Flash Sector F
Z1_EXEONLYSECTR.EXEONLY_SECTG	-	Execute-Only Flash Sector G
Z1_EXEONLYSECTR.EXEONLY_SECTH	-	Execute-Only Flash Sector H
Z1_EXEONLYSECTR.EXEONLY_SECTI	-	Execute-Only Flash Sector I
Z1_EXEONLYSECTR.EXEONLY_SECTJ	-	Execute-Only Flash Sector J
Z1_EXEONLYSECTR.EXEONLY_SECTK	-	Execute-Only Flash Sector K
Z1_EXEONLYSECTR.EXEONLY_SECTL	-	Execute-Only Flash Sector L
Z1_EXEONLYSECTR.EXEONLY_SECTM	-	Execute-Only Flash Sector M
Z1_EXEONLYSECTR.EXEONLY_SECTN	-	Execute-Only Flash Sector N
Z1_EXEONLYRAMR	-	Zone 1 RAM Execute_Only Block Register
Z1_EXEONLYRAMR.EXEONLY_RAM0	-	Execute-Only RAM LS0
Z1_EXEONLYRAMR.EXEONLY_RAM1	-	Execute-Only RAM LS1
Z1_EXEONLYRAMR.EXEONLY_RAM2	-	Execute-Only RAM LS2
Z1_EXEONLYRAMR.EXEONLY_RAM3	-	Execute-Only RAM LS3
Z1_EXEONLYRAMR.EXEONLY_RAM4	-	Execute-Only RAM LS4
Z1_EXEONLYRAMR.EXEONLY_RAM5	-	Execute-Only RAM LS5
Z1_EXEONLYRAMR.EXEONLY_RAM6	-	Execute-Only RAM D0
Z1_EXEONLYRAMR.EXEONLY_RAM7	-	Execute-Only RAM D1
Z2_OTPSECLOCK.CRCLOCK	-	Zone2 CRC Lock.
Z2_BOOTCTRL	-	Boot Mode
Z2_BOOTCTRL.KEY	-	OTP Boot Key
Z2_BOOTCTRL.BMODE	-	OTP Boot Mode
Z2_BOOTCTRL.BOOTPIN0	-	OTP Boot Pin 0 Mapping
Z2_BOOTCTRL.BOOTPIN1	-	OTP Boot Pin 1 Mapping
Z2_GRABSECTR	-	Zone 2 Grab Flash Sectors Register
Z2_GRABSECTR.GRAB_SECTA	-	Grab Flash Sector A
Z2_GRABSECTR.GRAB_SECTB	-	Grab Flash Sector B
Z2_GRABSECTR.GRAB_SECTC	-	Grab Flash Sector C
Z2_GRABSECTR.GRAB_SECTD	-	Grab Flash Sector D
Z2_GRABSECTR.GRAB_SECTE	-	Grab Flash Sector E
Z2_GRABSECTR.GRAB_SECTF	-	Grab Flash Sector F
Z2_GRABSECTR.GRAB_SECTG	-	Grab Flash Sector G
Z2_GRABSECTR.GRAB_SECTH	-	Grab Flash Sector H
Z2_GRABSECTR.GRAB_SECTI	-	Grab Flash Sector I
Z2_GRABSECTR.GRAB_SECTJ	-	Grab Flash Sector J
Z2_GRABSECTR.GRAB_SECTK	-	Grab Flash Sector K
Z2_GRABSECTR.GRAB_SECTL	-	Grab Flash Sector L
Z2_GRABSECTR.GRAB_SECTM	-	Grab Flash Sector M
Z2_GRABSECTR.GRAB_SECTN	-	Grab Flash Sector N
Z2_GRABRAMR	-	Zone 2 Grab RAM Blocks Register
Z2_GRABRAMR.GRAB_RAM0	-	Grab RAM LS0
Z2_GRABRAMR.GRAB_RAM1	-	Grab RAM LS1
Z2_GRABRAMR.GRAB_RAM2	-	Grab RAM LS2
Z2_GRABRAMR.GRAB_RAM3	-	Grab RAM LS3
Z2_GRABRAMR.GRAB_RAM4	-	Grab RAM LS4
Z2_GRABRAMR.GRAB_RAM5	-	Grab RAM LS5
Z2_GRABRAMR.GRAB_RAM6	-	Grab RAM D0
Z2_GRABRAMR.GRAB_RAM7	-	Grab RAM D1
Z2_GRABRAMR.GRAB_CLA1	-	Grab CLA1
Z2_EXEONLYSECTR	-	Zone 2 Flash Execute_Only Sector Register
Z2_EXEONLYSECTR.EXEONLY_SECTA	-	Execute-Only Flash Sector A
Z2_EXEONLYSECTR.EXEONLY_SECTB	-	Execute-Only Flash Sector B
Z2_EXEONLYSECTR.EXEONLY_SECTC	-	Execute-Only Flash Sector C
Z2_EXEONLYSECTR.EXEONLY_SECTD	-	Execute-Only Flash Sector D
Z2_EXEONLYSECTR.EXEONLY_SECTE	-	Execute-Only Flash Sector E
Z2_EXEONLYSECTR.EXEONLY_SECTF	-	Execute-Only Flash Sector F
Z2_EXEONLYSECTR.EXEONLY_SECTG	-	Execute-Only Flash Sector G
Z2_EXEONLYSECTR.EXEONLY_SECTH	-	Execute-Only Flash Sector H
Z2_EXEONLYSECTR.EXEONLY_SECTI	-	Execute-Only Flash Sector I
Z2_EXEONLYSECTR.EXEONLY_SECTJ	-	Execute-Only Flash Sector J
Z2_EXEONLYSECTR.EXEONLY_SECTK	-	Execute-Only Flash Sector K
Z2_EXEONLYSECTR.EXEONLY_SECTL	-	Execute-Only Flash Sector L
Z2_EXEONLYSECTR.EXEONLY_SECTM	-	Execute-Only Flash Sector M
Z2_EXEONLYSECTR.EXEONLY_SECTN	-	Execute-Only Flash Sector N
Z2_EXEONLYRAMR	-	Zone 2 RAM Execute_Only Block Register
Z2_EXEONLYRAMR.EXEONLY_RAM0	-	Execute-Only RAM LS0
Z2_EXEONLYRAMR.EXEONLY_RAM1	-	Execute-Only RAM LS1
Z2_EXEONLYRAMR.EXEONLY_RAM2	-	Execute-Only RAM LS2
Z2_EXEONLYRAMR.EXEONLY_RAM3	-	Execute-Only RAM LS3
Z2_EXEONLYRAMR.EXEONLY_RAM4	-	Execute-Only RAM LS4
Z2_EXEONLYRAMR.EXEONLY_RAM5	-	Execute-Only RAM LS5
Z2_EXEONLYRAMR.EXEONLY_RAM6	-	Execute-Only RAM D0
Z2_EXEONLYRAMR.EXEONLY_RAM7	-	Execute-Only RAM D1
SECTSTAT	-	Sectors Status Register
SECTSTAT.STATUS_SECTA	-	Zone Status Flash Sector A
SECTSTAT.STATUS_SECTB	-	Zone Status Flash Sector B
SECTSTAT.STATUS_SECTC	-	Zone Status Flash Sector C
SECTSTAT.STATUS_SECTD	-	Zone Status Flash Sector D
SECTSTAT.STATUS_SECTE	-	Zone Status Flash Sector E
SECTSTAT.STATUS_SECTF	-	Zone Status Flash Sector F
SECTSTAT.STATUS_SECTG	-	Zone Status Flash Sector G
SECTSTAT.STATUS_SECTH	-	Zone Status Flash Sector H
SECTSTAT.STATUS_SECTI	-	Zone Status Flash Sector I
SECTSTAT.STATUS_SECTJ	-	Zone Status Flash Sector J
SECTSTAT.STATUS_SECTK	-	Zone Status Flash Sector K
SECTSTAT.STATUS_SECTL	-	Zone Status Flash Sector L
SECTSTAT.STATUS_SECTM	-	Zone Status Flash Sector M
SECTSTAT.STATUS_SECTN	-	Zone Status Flash Sector N
RAMSTAT	-	RAM Status Register
RAMSTAT.STATUS_RAM0	-	Zone Status RAM LS0
RAMSTAT.STATUS_RAM1	-	Zone Status RAM LS1
RAMSTAT.STATUS_RAM2	-	Zone Status RAM LS2
RAMSTAT.STATUS_RAM3	-	Zone Status RAM LS3
RAMSTAT.STATUS_RAM4	-	Zone Status RAM LS4
RAMSTAT.STATUS_RAM5	-	Zone Status RAM LS5
RAMSTAT.STATUS_RAM6	-	Zone Status RAM D0
RAMSTAT.STATUS_RAM7	-	Zone Status RAM D1
RAMSTAT.STATUS_CLA1	-	Zone Status CLA1
-	Z1OTP_JLM_ENABLE	Zone 1 JTAGLOCK Enable Register
-	Z1OTP_GPREG1	Zone 1 General Purpose Register 1
-	Z1OTP_GPREG2	Zone 1 General Purpose Register 2
-	Z1OTP_GPREG3	Zone 1 General Purpose Register 3
-	Z1OTP_GPREG4	Zone 1 General Purpose Register 4
-	Z1OTP_JTAGPSWDH0	JTAG Lock Permanent Password 0
-	Z1OTP_JTAGPSWDH1	JTAG Lock Permanent Password 1
-	Z1OTP_CMACKEY0	Secure Boot CMAC Key 0
-	Z1OTP_CMACKEY1	Secure Boot CMAC Key 1
-	Z1OTP_CMACKEY2	Secure Boot CMAC Key 2
-	Z1OTP_CMACKEY3	Secure Boot CMAC Key 3
-	Z2OTP_GPREG1	Zone 2 General Purpose Register 1
-	Z2OTP_GPREG2	Zone 2 General Purpose Register 2
-	Z2OTP_GPREG3	Zone 2 General Purpose Register 3
-	Z2OTP_GPREG4	Zone 2 General Purpose Register 4
-	Z1_OTPSECLOCK.JTAGLOCK	JTAG Lock Status
-	Z1_JLM_ENABLE	Zone 1 JTAGLOCK Enable Register
-	Z1_JLM_ENABLE.Z1_JLM_ENABLE	Zone1 JLM_ENABLE register.
-	Z1_LINKPOINTERERR.Z1_LINKPOINTERERR	Error to Resolve Z1 Link pointer
-	Z1_GPREG1	Zone 1 General Purpose Register-1
-	Z1_GPREG2	Zone 1 General Purpose Register-2
-	Z1_GPREG3	Zone 1 General Purpose Register-3
-	Z1_GPREG4	Zone 1 General Purpose Register-4
-	Z1_GRABSECT1R	Zone 1 Grab Flash Status Register 1
-	Z1_GRABSECT1R.GRAB_SECT0	Grab Flash Sector 0
-	Z1_GRABSECT1R.GRAB_SECT1	Grab Flash Sector 1
-	Z1_GRABSECT1R.GRAB_SECT2	Grab Flash Sector 2
-	Z1_GRABSECT1R.GRAB_SECT3	Grab Flash Sector 3
-	Z1_GRABSECT1R.GRAB_SECT4	Grab Flash Sector 4
-	Z1_GRABSECT1R.GRAB_SECT5	Grab Flash Sector 5
-	Z1_GRABSECT1R.GRAB_SECT6	Grab Flash Sector 6
-	Z1_GRABSECT1R.GRAB_SECT7	Grab Flash Sector 7
-	Z1_GRABSECT1R.GRAB_SECT8	Grab Flash Sector 8
-	Z1_GRABSECT1R.GRAB_SECT9	Grab Flash Sector 9
-	Z1_GRABSECT1R.GRAB_SECT10	Grab Flash Sector 10
-	Z1_GRABSECT1R.GRAB_SECT11	Grab Flash Sector 11
-	Z1_GRABSECT1R.GRAB_SECT12	Grab Flash Sector 12
-	Z1_GRABSECT1R.GRAB_SECT13	Grab Flash Sector 13
-	Z1_GRABSECT1R.GRAB_SECT14	Grab Flash Sector 14
-	Z1_GRABSECT1R.GRAB_SECT15	Grab Flash Sector 15
-	Z1_GRABSECT2R	Zone 1 Grab Flash Status Register 2
-	Z1_GRABSECT2R.GRAB_SECT16	Grab Flash Sector 16
-	Z1_GRABSECT2R.GRAB_SECT17	Grab Flash Sector 17
-	Z1_GRABSECT2R.GRAB_SECT18	Grab Flash Sector 18
-	Z1_GRABSECT2R.GRAB_SECT19	Grab Flash Sector 19
-	Z1_GRABSECT2R.GRAB_SECT20	Grab Flash Sector 20
-	Z1_GRABSECT2R.GRAB_SECT21	Grab Flash Sector 21
-	Z1_GRABSECT2R.GRAB_SECT22	Grab Flash Sector 22
-	Z1_GRABSECT2R.GRAB_SECT23	Grab Flash Sector 23
-	Z1_GRABSECT2R.GRAB_SECT24	Grab Flash Sector 24
-	Z1_GRABSECT2R.GRAB_SECT25	Grab Flash Sector 25
-	Z1_GRABSECT2R.GRAB_SECT26	Grab Flash Sector 26
-	Z1_GRABSECT2R.GRAB_SECT27	Grab Flash Sector 27
-	Z1_GRABSECT2R.GRAB_SECT28	Grab Flash Sector 28
-	Z1_GRABSECT2R.GRAB_SECT29	Grab Flash Sector 29
-	Z1_GRABSECT2R.GRAB_SECT30	Grab Flash Sector 30
-	Z1_GRABSECT2R.GRAB_SECT31	Grab Flash Sector 31
-	Z1_GRABSECT3R	Zone 1 Grab Flash Status Register 3
-	Z1_GRABSECT3R.GRAB_SECT39_32	Grab Flash Sectors 39-32
-	Z1_GRABSECT3R.GRAB_SECT47_40	Grab Flash Sectors 47-40
-	Z1_GRABSECT3R.GRAB_SECT55_48	Grab Flash Sectors 55-48
-	Z1_GRABSECT3R.GRAB_SECT63_56	Grab Flash Sectors 63-56
-	Z1_GRABSECT3R.GRAB_SECT71_64	Grab Flash Sectors 71_64
-	Z1_GRABSECT3R.GRAB_SECT79_72	Grab Flash Sectors 79-72
-	Z1_GRABSECT3R.GRAB_SECT87_80	Grab Flash Sectors 87-80
-	Z1_GRABSECT3R.GRAB_SECT95_88	Grab Flash Sectors 95-88
-	Z1_GRABSECT3R.GRAB_SECT103_96	Grab Flash Sectors 103-96
-	Z1_GRABSECT3R.GRAB_SECT111_104	Grab Flash Sectors 111_104
-	Z1_GRABSECT3R.GRAB_SECT119_112	Grab Flash Sectors 119-112
-	Z1_GRABSECT3R.GRAB_SECT127_120	Grab Flash Sectors 127-120
-	Z1_GRABRAM1R	Zone 1 Grab RAM Status Register 1
-	Z1_GRABRAM1R.GRAB_RAM0	Grab RAM LS0 Section A
-	Z1_GRABRAM1R.GRAB_RAM1	Grab RAM LS0 Section B
-	Z1_GRABRAM1R.GRAB_RAM2	Grab RAM LS0 Section C
-	Z1_GRABRAM1R.GRAB_RAM3	Grab RAM LS0 Section D
-	Z1_GRABRAM1R.GRAB_RAM4	Grab RAM LS1 Section A
-	Z1_GRABRAM1R.GRAB_RAM5	Grab RAM LS1 Section B
-	Z1_GRABRAM1R.GRAB_RAM6	Grab RAM LS1 Section C
-	Z1_GRABRAM1R.GRAB_RAM7	Grab RAM LS1 Section D
-	Z1_EXEONLYSECT1R	Zone 1 Execute Only Flash Status Register 1
-	Z1_EXEONLYSECT1R.EXEONLY_SECT0	Execute-Only Flash Sector 0
-	Z1_EXEONLYSECT1R.EXEONLY_SECT1	Execute-Only Flash Sector 1
-	Z1_EXEONLYSECT1R.EXEONLY_SECT2	Execute-Only Flash Sector 2
-	Z1_EXEONLYSECT1R.EXEONLY_SECT3	Execute-Only Flash Sector 3
-	Z1_EXEONLYSECT1R.EXEONLY_SECT4	Execute-Only Flash Sector 4
-	Z1_EXEONLYSECT1R.EXEONLY_SECT5	Execute-Only Flash Sector 5
-	Z1_EXEONLYSECT1R.EXEONLY_SECT6	Execute-Only Flash Sector 6
-	Z1_EXEONLYSECT1R.EXEONLY_SECT7	Execute-Only Flash Sector 7
-	Z1_EXEONLYSECT1R.EXEONLY_SECT8	Execute-Only Flash Sector 8
-	Z1_EXEONLYSECT1R.EXEONLY_SECT9	Execute-Only Flash Sector 9
-	Z1_EXEONLYSECT1R.EXEONLY_SECT10	Execute-Only Flash Sector 10
-	Z1_EXEONLYSECT1R.EXEONLY_SECT11	Execute-Only Flash Sector 11
-	Z1_EXEONLYSECT1R.EXEONLY_SECT12	Execute-Only Flash Sector 12
-	Z1_EXEONLYSECT1R.EXEONLY_SECT13	Execute-Only Flash Sector 13
-	Z1_EXEONLYSECT1R.EXEONLY_SECT14	Execute-Only Flash Sector 14
-	Z1_EXEONLYSECT1R.EXEONLY_SECT15	Execute-Only Flash Sector 15
-	Z1_EXEONLYSECT1R.EXEONLY_SECT16	Execute-Only Flash Sector 16
-	Z1_EXEONLYSECT1R.EXEONLY_SECT17	Execute-Only Flash Sector 17
-	Z1_EXEONLYSECT1R.EXEONLY_SECT18	Execute-Only Flash Sector 18
-	Z1_EXEONLYSECT1R.EXEONLY_SECT19	Execute-Only Flash Sector 19
-	Z1_EXEONLYSECT1R.EXEONLY_SECT20	Execute-Only Flash Sector 20
-	Z1_EXEONLYSECT1R.EXEONLY_SECT21	Execute-Only Flash Sector 21
-	Z1_EXEONLYSECT1R.EXEONLY_SECT22	Execute-Only Flash Sector 22
-	Z1_EXEONLYSECT1R.EXEONLY_SECT23	Execute-Only Flash Sector 23
-	Z1_EXEONLYSECT1R.EXEONLY_SECT24	Execute-Only Flash Sector 24
-	Z1_EXEONLYSECT1R.EXEONLY_SECT25	Execute-Only Flash Sector 25
-	Z1_EXEONLYSECT1R.EXEONLY_SECT26	Execute-Only Flash Sector 26
-	Z1_EXEONLYSECT1R.EXEONLY_SECT27	Execute-Only Flash Sector 27
-	Z1_EXEONLYSECT1R.EXEONLY_SECT28	Execute-Only Flash Sector 28
-	Z1_EXEONLYSECT1R.EXEONLY_SECT29	Execute-Only Flash Sector 29
-	Z1_EXEONLYSECT1R.EXEONLY_SECT30	Execute-Only Flash Sector 30
-	Z1_EXEONLYSECT1R.EXEONLY_SECT31	Execute-Only Flash Sector 31
-	Z1_EXEONLYSECT2R	Zone 1 Execute Only Flash Status Register 2
-	Z1_EXEONLYSECT2R.EXEONLY_SECT39_32	Execute-Only Flash Sectors 39_32
-	Z1_EXEONLYSECT2R.EXEONLY_SECT47_40	Execute-Only Flash Sectors 47-40
-	Z1_EXEONLYSECT2R.EXEONLY_SECT55_48	Execute-Only Flash Sectors 55-48
-	Z1_EXEONLYSECT2R.EXEONLY_SECT63_56	Execute-Only Flash Sectors 63-56
-	Z1_EXEONLYSECT2R.EXEONLY_SECT71_64	Execute-Only Flash Sectors 71-64
-	Z1_EXEONLYSECT2R.EXEONLY_SECT79_72	Execute-Only Flash Sectors 79-72
-	Z1_EXEONLYSECT2R.EXEONLY_SECT87_80	Execute-Only Flash Sectors 87-80
-	Z1_EXEONLYSECT2R.EXEONLY_SECT95_88	Execute-Only Flash Sectors 95-88
-	Z1_EXEONLYSECT2R.EXEONLY_SECT103_96	Execute-Only Flash Sectors 103-96
-	Z1_EXEONLYSECT2R.EXEONLY_SECT111_104	Execute-Only Flash Sectors 111-104
-	Z1_EXEONLYSECT2R.EXEONLY_SECT119_112	Execute-Only Flash Sectors 119-112
-	Z1_EXEONLYSECT2R.EXEONLY_SECT127_120	Execute-Only Flash Sectors 127-120
-	Z1_EXEONLYRAM1R	Zone 1 Execute Only RAM Status Register 1
-	Z1_EXEONLYRAM1R.EXEONLY_RAM0	Execute-Only RAM LS0 Section A
-	Z1_EXEONLYRAM1R.EXEONLY_RAM1	Execute-Only RAM LS0 Section B
-	Z1_EXEONLYRAM1R.EXEONLY_RAM2	Execute-Only RAM LS0 Section C
-	Z1_EXEONLYRAM1R.EXEONLY_RAM3	Execute-Only RAM LS0 Section D
-	Z1_EXEONLYRAM1R.EXEONLY_RAM4	Execute-Only RAM LS1 Section A
-	Z1_EXEONLYRAM1R.EXEONLY_RAM5	Execute-Only RAM LS1 Section B
-	Z1_EXEONLYRAM1R.EXEONLY_RAM6	Execute-Only RAM LS1 Section C
-	Z1_EXEONLYRAM1R.EXEONLY_RAM7	Execute-Only RAM LS1 Section D
-	Z1_JTAGKEY0	JTAG Unlock Key Register 0
-	Z1_JTAGKEY1	JTAG Unlock Key Register 1
-	Z1_JTAGKEY2	JTAG Unlock Key Register 2
-	Z1_JTAGKEY3	JTAG Unlock Key Register 3
-	Z1_CMACKEY0	Secure Boot CMAC Key Status Register 0
-	Z1_CMACKEY1	Secure Boot CMAC Key Status Register 1
-	Z1_CMACKEY2	Secure Boot CMAC Key Status Register 2
-	Z1_CMACKEY3	Secure Boot CMAC Key Status Register 3
-	Z2_OTPSECLOCK.JTAGLOCK	JTAG Lock Status
-	Z2_LINKPOINTERERR.Z2_LINKPOINTERERR	Error to Resolve Z2 Link pointer
-	Z2_GPREG1	Zone 2 General Purpose Register-1
-	Z2_GPREG2	Zone 2 General Purpose Register-2
-	Z2_GPREG3	Zone 2 General Purpose Register-3
-	Z2_GPREG4	Zone 2 General Purpose Register-4
-	Z2_GRABSECT1R	Zone 2 Grab Flash Status Register 1
-	Z2_GRABSECT1R.GRAB_SECT0	Grab Flash Sector 0
-	Z2_GRABSECT1R.GRAB_SECT1	Grab Flash Sector 1
-	Z2_GRABSECT1R.GRAB_SECT2	Grab Flash Sector 2
-	Z2_GRABSECT1R.GRAB_SECT3	Grab Flash Sector 3
-	Z2_GRABSECT1R.GRAB_SECT4	Grab Flash Sector 4
-	Z2_GRABSECT1R.GRAB_SECT5	Grab Flash Sector 5
-	Z2_GRABSECT1R.GRAB_SECT6	Grab Flash Sector 6
-	Z2_GRABSECT1R.GRAB_SECT7	Grab Flash Sector 7
-	Z2_GRABSECT1R.GRAB_SECT8	Grab Flash Sector 8
-	Z2_GRABSECT1R.GRAB_SECT9	Grab Flash Sector 9
-	Z2_GRABSECT1R.GRAB_SECT10	Grab Flash Sector 10
-	Z2_GRABSECT1R.GRAB_SECT11	Grab Flash Sector 11
-	Z2_GRABSECT1R.GRAB_SECT12	Grab Flash Sector 12
-	Z2_GRABSECT1R.GRAB_SECT13	Grab Flash Sector 13
-	Z2_GRABSECT1R.GRAB_SECT14	Grab Flash Sector 14
-	Z2_GRABSECT1R.GRAB_SECT15	Grab Flash Sector 15
-	Z2_GRABSECT2R	Zone 2 Grab Flash Status Register 2
-	Z2_GRABSECT2R.GRAB_SECT16	Grab Flash Sector 16
-	Z2_GRABSECT2R.GRAB_SECT17	Grab Flash Sector 17
-	Z2_GRABSECT2R.GRAB_SECT18	Grab Flash Sector 18
-	Z2_GRABSECT2R.GRAB_SECT19	Grab Flash Sector 19
-	Z2_GRABSECT2R.GRAB_SECT20	Grab Flash Sector 20
-	Z2_GRABSECT2R.GRAB_SECT21	Grab Flash Sector 21
-	Z2_GRABSECT2R.GRAB_SECT22	Grab Flash Sector 22
-	Z2_GRABSECT2R.GRAB_SECT23	Grab Flash Sector 23
-	Z2_GRABSECT2R.GRAB_SECT24	Grab Flash Sector 24
-	Z2_GRABSECT2R.GRAB_SECT25	Grab Flash Sector 25
-	Z2_GRABSECT2R.GRAB_SECT26	Grab Flash Sector 26
-	Z2_GRABSECT2R.GRAB_SECT27	Grab Flash Sector 27
-	Z2_GRABSECT2R.GRAB_SECT28	Grab Flash Sector 28
-	Z2_GRABSECT2R.GRAB_SECT29	Grab Flash Sector 29
-	Z2_GRABSECT2R.GRAB_SECT30	Grab Flash Sector 30
-	Z2_GRABSECT2R.GRAB_SECT31	Grab Flash Sector 31
-	Z2_GRABSECT3R	Zone 2 Grab Flash Status Register 3
-	Z2_GRABSECT3R.GRAB_SECT39_32	Grab Flash Sectors 39-32
-	Z2_GRABSECT3R.GRAB_SECT47_40	Grab Flash Sectors 47-40
-	Z2_GRABSECT3R.GRAB_SECT55_48	Grab Flash Sectors 55-48
-	Z2_GRABSECT3R.GRAB_SECT63_56	Grab Flash Sectors 63-56
-	Z2_GRABSECT3R.GRAB_SECT71_64	Grab Flash Sectors 71_64
-	Z2_GRABSECT3R.GRAB_SECT79_72	Grab Flash Sectors 79-72
-	Z2_GRABSECT3R.GRAB_SECT87_80	Grab Flash Sectors 87-80
-	Z2_GRABSECT3R.GRAB_SECT95_88	Grab Flash Sectors 95-88
-	Z2_GRABSECT3R.GRAB_SECT103_96	Grab Flash Sectors 103-96
-	Z2_GRABSECT3R.GRAB_SECT111_104	Grab Flash Sectors 111_104
-	Z2_GRABSECT3R.GRAB_SECT119_112	Grab Flash Sectors 119-112
-	Z2_GRABSECT3R.GRAB_SECT127_120	Grab Flash Sectors 127-120
-	Z2_GRABRAM1R	Zone 2 Grab RAM Status Register 1
-	Z2_GRABRAM1R.GRAB_RAM0	Grab RAM LS0 Section A
-	Z2_GRABRAM1R.GRAB_RAM1	Grab RAM LS0 Section B
-	Z2_GRABRAM1R.GRAB_RAM2	Grab RAM LS0 Section C
-	Z2_GRABRAM1R.GRAB_RAM3	Grab RAM LS0 Section D
-	Z2_GRABRAM1R.GRAB_RAM4	Grab RAM LS1 Section A
-	Z2_GRABRAM1R.GRAB_RAM5	Grab RAM LS1 Section B
-	Z2_GRABRAM1R.GRAB_RAM6	Grab RAM LS1 Section C
-	Z2_GRABRAM1R.GRAB_RAM7	Grab RAM LS1 Section D
-	Z2_EXEONLYSECT1R	Zone 2 Execute Only Flash Status Register 1
-	Z2_EXEONLYSECT1R.EXEONLY_SECT0	Execute-Only Flash Sector 0
-	Z2_EXEONLYSECT1R.EXEONLY_SECT1	Execute-Only Flash Sector 1
-	Z2_EXEONLYSECT1R.EXEONLY_SECT2	Execute-Only Flash Sector 2
-	Z2_EXEONLYSECT1R.EXEONLY_SECT3	Execute-Only Flash Sector 3
-	Z2_EXEONLYSECT1R.EXEONLY_SECT4	Execute-Only Flash Sector 4
-	Z2_EXEONLYSECT1R.EXEONLY_SECT5	Execute-Only Flash Sector 5
-	Z2_EXEONLYSECT1R.EXEONLY_SECT6	Execute-Only Flash Sector 6
-	Z2_EXEONLYSECT1R.EXEONLY_SECT7	Execute-Only Flash Sector 7
-	Z2_EXEONLYSECT1R.EXEONLY_SECT8	Execute-Only Flash Sector 8
-	Z2_EXEONLYSECT1R.EXEONLY_SECT9	Execute-Only Flash Sector 9
-	Z2_EXEONLYSECT1R.EXEONLY_SECT10	Execute-Only Flash Sector 10
-	Z2_EXEONLYSECT1R.EXEONLY_SECT11	Execute-Only Flash Sector 11
-	Z2_EXEONLYSECT1R.EXEONLY_SECT12	Execute-Only Flash Sector 12
-	Z2_EXEONLYSECT1R.EXEONLY_SECT13	Execute-Only Flash Sector 13
-	Z2_EXEONLYSECT1R.EXEONLY_SECT14	Execute-Only Flash Sector 14
-	Z2_EXEONLYSECT1R.EXEONLY_SECT15	Execute-Only Flash Sector 15
-	Z2_EXEONLYSECT1R.EXEONLY_SECT16	Execute-Only Flash Sector 16
-	Z2_EXEONLYSECT1R.EXEONLY_SECT17	Execute-Only Flash Sector 17
-	Z2_EXEONLYSECT1R.EXEONLY_SECT18	Execute-Only Flash Sector 18
-	Z2_EXEONLYSECT1R.EXEONLY_SECT19	Execute-Only Flash Sector 19
-	Z2_EXEONLYSECT1R.EXEONLY_SECT20	Execute-Only Flash Sector 20
-	Z2_EXEONLYSECT1R.EXEONLY_SECT21	Execute-Only Flash Sector 21
-	Z2_EXEONLYSECT1R.EXEONLY_SECT22	Execute-Only Flash Sector 22
-	Z2_EXEONLYSECT1R.EXEONLY_SECT23	Execute-Only Flash Sector 23
-	Z2_EXEONLYSECT1R.EXEONLY_SECT24	Execute-Only Flash Sector 24
-	Z2_EXEONLYSECT1R.EXEONLY_SECT25	Execute-Only Flash Sector 25
-	Z2_EXEONLYSECT1R.EXEONLY_SECT26	Execute-Only Flash Sector 26
-	Z2_EXEONLYSECT1R.EXEONLY_SECT27	Execute-Only Flash Sector 27
-	Z2_EXEONLYSECT1R.EXEONLY_SECT28	Execute-Only Flash Sector 28
-	Z2_EXEONLYSECT1R.EXEONLY_SECT29	Execute-Only Flash Sector 29
-	Z2_EXEONLYSECT1R.EXEONLY_SECT30	Execute-Only Flash Sector 30
-	Z2_EXEONLYSECT1R.EXEONLY_SECT31	Execute-Only Flash Sector 31
-	Z2_EXEONLYSECT2R	Zone 2 Execute Only Flash Status Register 2
-	Z2_EXEONLYSECT2R.EXEONLY_SECT39_32	Execute-Only Flash Sectors 39-32
-	Z2_EXEONLYSECT2R.EXEONLY_SECT47_40	Execute-Only Flash Sectors 47-40
-	Z2_EXEONLYSECT2R.EXEONLY_SECT55_48	Execute-Only Flash Sectors 55-48
-	Z2_EXEONLYSECT2R.EXEONLY_SECT63_56	Execute-Only Flash Sectors 63-56
-	Z2_EXEONLYSECT2R.EXEONLY_SECT71_64	Execute-Only Flash Sectors 71-64
-	Z2_EXEONLYSECT2R.EXEONLY_SECT79_72	Execute-Only Flash Sectors 79-72
-	Z2_EXEONLYSECT2R.EXEONLY_SECT87_80	Execute-Only Flash Sectors 87-80
-	Z2_EXEONLYSECT2R.EXEONLY_SECT95_88	Execute-Only Flash Sectors 95-88
-	Z2_EXEONLYSECT2R.EXEONLY_SECT103_96	Execute-Only Flash Sectors 103-96
-	Z2_EXEONLYSECT2R.EXEONLY_SECT111_104	Execute-Only Flash Sectors 111-104
-	Z2_EXEONLYSECT2R.EXEONLY_SECT119_112	Execute-Only Flash Sectors 119-112
-	Z2_EXEONLYSECT2R.EXEONLY_SECT127_120	Execute-Only Flash Sectors 127-120
-	Z2_EXEONLYRAM1R	Zone 2 Execute Only RAM Status Register 1
-	Z2_EXEONLYRAM1R.EXEONLY_RAM0	Execute-Only RAM LS0 Section A
-	Z2_EXEONLYRAM1R.EXEONLY_RAM1	Execute-Only RAM LS0 Section B
-	Z2_EXEONLYRAM1R.EXEONLY_RAM2	Execute-Only RAM LS0 Section C
-	Z2_EXEONLYRAM1R.EXEONLY_RAM3	Execute-Only RAM LS0 Section D
-	Z2_EXEONLYRAM1R.EXEONLY_RAM4	Execute-Only RAM LS1 Section A
-	Z2_EXEONLYRAM1R.EXEONLY_RAM5	Execute-Only RAM LS1 Section B
-	Z2_EXEONLYRAM1R.EXEONLY_RAM6	Execute-Only RAM LS1 Section C
-	Z2_EXEONLYRAM1R.EXEONLY_RAM7	Execute-Only RAM LS1 Section D
-	SECTSTAT1	Flash Sectors Status Register 1
-	SECTSTAT1.STATUS_SECT0	Zone Status Flash Bank 0 Sector 0
-	SECTSTAT1.STATUS_SECT1	Zone Status Flash Bank 0 Sector 1
-	SECTSTAT1.STATUS_SECT2	Zone Status Flash Bank 0 Sector 2
-	SECTSTAT1.STATUS_SECT3	Zone Status Flash Bank 0 Sector 3
-	SECTSTAT1.STATUS_SECT4	Zone Status Flash Bank 0 Sector 4
-	SECTSTAT1.STATUS_SECT5	Zone Status Flash Bank 0 Sector 5
-	SECTSTAT1.STATUS_SECT6	Zone Status Flash Bank 0 Sector 6
-	SECTSTAT1.STATUS_SECT7	Zone Status Flash Bank 0 Sector 7
-	SECTSTAT1.STATUS_SECT8	Zone Status Flash Bank 0 Sector 8
-	SECTSTAT1.STATUS_SECT9	Zone Status Flash Bank 0 Sector 9
-	SECTSTAT1.STATUS_SECT10	Zone Status Flash Bank 0 Sector 10
-	SECTSTAT1.STATUS_SECT11	Zone Status Flash Bank 0 Sector 11
-	SECTSTAT1.STATUS_SECT12	Zone Status Flash Bank 0 Sector 12
-	SECTSTAT1.STATUS_SECT13	Zone Status Flash Bank 0 Sector 13
-	SECTSTAT1.STATUS_SECT14	Zone Status Flash Bank 0 Sector 14
-	SECTSTAT1.STATUS_SECT15	Zone Status Flash Bank 0 Sector 15
-	SECTSTAT2	Flash Sectors Status Register 2
-	SECTSTAT2.STATUS_SECT16	Zone Status Flash Bank 0 Sector 16
-	SECTSTAT2.STATUS_SECT17	Zone Status Flash Bank 0 Sector 17
-	SECTSTAT2.STATUS_SECT18	Zone Status Flash Bank 0 Sector 18
-	SECTSTAT2.STATUS_SECT19	Zone Status Flash Bank 0 Sector 19
-	SECTSTAT2.STATUS_SECT20	Zone Status Flash Bank 0 Sector 20
-	SECTSTAT2.STATUS_SECT21	Zone Status Flash Bank 0 Sector 21
-	SECTSTAT2.STATUS_SECT22	Zone Status Flash Bank 0 Sector 22
-	SECTSTAT2.STATUS_SECT23	Zone Status Flash Bank 0 Sector 23
-	SECTSTAT2.STATUS_SECT24	Zone Status Flash Bank 0 Sector 24
-	SECTSTAT2.STATUS_SECT25	Zone Status Flash Bank 0 Sector 25
-	SECTSTAT2.STATUS_SECT26	Zone Status Flash Bank 0 Sector 26
-	SECTSTAT2.STATUS_SECT27	Zone Status Flash Bank 0 Sector 27
-	SECTSTAT2.STATUS_SECT28	Zone Status Flash Bank 0 Sector 28
-	SECTSTAT2.STATUS_SECT29	Zone Status Flash Bank 0 Sector 29
-	SECTSTAT2.STATUS_SECT30	Zone Status Flash Bank 0 Sector 30
-	SECTSTAT2.STATUS_SECT31	Zone Status Flash Bank 0 Sector 31
-	SECTSTAT3	Flash Sectors Status Register 3
-	SECTSTAT3.STATUS_SECT39_32	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT47_40	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT55_48	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT63_56	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT71_64	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT79_72	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT87_80	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT95_88	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT103_96	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT111_104	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT119_112	Zone Status flash Bank 0 Sectors
-	SECTSTAT3.STATUS_SECT127_120	Zone Status flash Bank 0 Sectors
-	RAMSTAT1	RAM Status Register 1
-	RAMSTAT1.STATUS_RAM0	Zone Status RAM LS0 Section A
-	RAMSTAT1.STATUS_RAM1	Zone Status RAM LS0 Section B
-	RAMSTAT1.STATUS_RAM2	Zone Status RAM LS0 Section C
-	RAMSTAT1.STATUS_RAM3	Zone Status RAM LS0 Section D
-	RAMSTAT1.STATUS_RAM4	Zone Status RAM LS1 Section A
-	RAMSTAT1.STATUS_RAM5	Zone Status RAM LS1 Section B
-	RAMSTAT1.STATUS_RAM6	Zone Status RAM LS1 Section C
-	RAMSTAT1.STATUS_RAM7	Zone Status RAM LS1 Section D
-	SECERRSTAT	Security Error Status Register
-	SECERRSTAT.ERR	Security Configuration load Error Status
-	SECERRCLR	Security Error Clear Register
-	SECERRCLR.ERR	Clear Security Configuration Load Error Status Bit
-	SECERRFRC	Security Error Force Register
-	SECERRFRC.ERR	Set Security Configuration Load Error Status Bit
-	SECERRFRC.KEY	Valid Register Write Key
-	DENYCODE	Flash Authorization Denial Code
-	DENYCODE.BLOCKED	Blocked Code
-	DENYCODE.ILLADDR	Illegal Address Code
-	DENYCODE.ILLPROG	Illegal Program Address
-	DENYCODE.ILLERASE	Illegal Erase Address
-	DENYCODE.ILLRDVER	Illegal Read Verify Address
-	DENYCODE.ILLMODECH	Illegal Mode Change
-	DENYCODE.ILLCMD	Illegal Command
-	DENYCODE.ILLSIZE	Illegal Command Size
-	RAMOPENSTAT	RAM Security Open Status Register
-	RAMOPENSTAT.RAMOPEN	RAM Security Open
-	RAMOPENFRC	RAM Security Open Force Register
-	RAMOPENFRC.SET	Set RAM Open request
-	RAMOPENFRC.KEY	Valid Write KEY
-	RAMOPENCLR	RAM Security Open Clear Register
-	RAMOPENCLR.CLEAR	Clear RAM Open request
-	RAMOPENCLR.KEY	Valid Write KEY
-	RAMOPENLOCK	RAMOPEN Lock Register
-	RAMOPENLOCK.LOCK	RAMOPEN Lock

    DCSM_unlockZone1CSM

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t linkPointer;
	3	3		uint32_t zsbBase  = (DCSM_Z1OTP_BASE + 0x20U); // base address of the ZSB
n	4		-	int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer)
		4	+	int32_t bitPos = 13; // Bits [13:0] point to a ZSB (14-bit link pointer)
	5	5		int32_t zeroFound = 0;
	6	6
	7	7		//
	8	8		// Check the arguments.
	9	9		//
	10	10		ASSERT(psCMDKey != NULL);
	11	11
	12	12		linkPointer = HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTER);
	13	13
	14	14		//
n	15		-	// Bits 31 and 30 as most-significant 0 are invalid LinkPointer options
		15	+	// Bits 31 - 14 as most-significant 0 are invalid LinkPointer options
	16	16		//
n	17		-	linkPointer = linkPointer << 3;
		17	+	linkPointer = linkPointer << 18;
	18	18
	19	19		//
	20	20		// Zone-Select Block (ZSB) selection using Link-Pointers
	21	21		// and 0's bit position within the Link pointer
	22	22		//
	23	23		while((zeroFound == 0) && (bitPos > -1))
	24	24		{
	25	25		//
	26	26		// The most significant bit position in the resolved link pointer
	27	27		// which is 0, defines the valid base address for the ZSB.
	28	28		//
	29	29		if((linkPointer & 0x80000000U) == 0U)
	30	30		{
	31	31		zeroFound = 1;
	32	32		//
	33	33		// Base address of the ZSB is calculated using
n	34		-	// 0x10 as the slope/step with which zsbBase expands with
		34	+	// 0x20 as the slope/step with which zsbBase expands with
	35		-	// change in the bitPos and 3*0x10 is the offset
		35	+	// change in the bitPos and 2*0x20 is the offset
	36	36		//
n	37		-	zsbBase = (DCSM_Z1OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U));
		37	+	zsbBase = (DCSM_Z1OTP_BASE + (((uint32_t)bitPos + 2U) * 0x20U));
	38	38		}
	39	39		else
	40	40		{
	41	41		//
	42	42		// Move through the linkPointer to find the most significant
	43	43		// bit position of 0
	44	44		//
	45	45		bitPos--;
	46	46		linkPointer = linkPointer << 1;
	47	47		}
	48	48		}
	49	49
	50	50		//
	51	51		// Perform dummy reads on the 128-bit password
	52	52		// Using linkPointer because it is no longer needed
	53	53		//
	54	54		linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD0);
	55	55		linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD1);
	56	56		linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD2);
	57	57		linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD3);
	58	58
	59	59		if(psCMDKey != NULL)
	60	60		{
	61	61		HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY0) = psCMDKey->csmKey0;
	62	62		HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY1) = psCMDKey->csmKey1;
	63	63		HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY2) = psCMDKey->csmKey2;
	64	64		HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY3) = psCMDKey->csmKey3;
	65	65		}
	66	66		}
	67	67

    DCSM_unlockZone2CSM

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t linkPointer;
	3	3		uint32_t zsbBase = (DCSM_Z2OTP_BASE + 0x20U); // base address of the ZSB
n	4		-	int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer)
		4	+	int32_t bitPos = 13; // Bits [13:0] point to a ZSB (14-bit link pointer)
	5	5		int32_t zeroFound = 0;
	6	6
	7	7		//
	8	8		// Check the arguments.
	9	9		//
	10	10		ASSERT(psCMDKey != NULL);
	11	11
	12	12		linkPointer = HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTER);
	13	13
	14	14		//
n	15		-	// Bits 31 and 30 as most-significant 0 are invalid LinkPointer options
		15	+	// Bits 31 - 14 as most-significant 0 are invalid LinkPointer options
	16	16		//
n	17		-	linkPointer = linkPointer << 3;
		17	+	linkPointer = linkPointer << 18;
	18	18
	19	19		//
	20	20		// Zone-Select Block (ZSB) selection using Link-Pointers
	21	21		// and 0's bit position within the Link pointer
	22	22		//
	23	23		while((zeroFound == 0) && (bitPos > -1))
	24	24		{
	25	25		//
	26	26		// The most significant bit position in the resolved link pointer
	27	27		// which is 0, defines the valid base address for the ZSB.
	28	28		//
	29	29		if((linkPointer & 0x80000000U) == 0U)
	30	30		{
	31	31		zeroFound = 1;
	32	32		//
	33	33		// Base address of the ZSB is calculated using
n	34		-	// 0x10 as the slope/step with which zsbBase expands with
		34	+	// 0x20 as the slope/step with which zsbBase expands with
	35		-	// change in the bitPos and 3*0x10 is the offset
		35	+	// change in the bitPos and 2*0x20 is the offset
	36	36		//
n	37		-	zsbBase = (DCSM_Z2OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U));
		37	+	zsbBase = (DCSM_Z2OTP_BASE + (((uint32_t)bitPos + 2U) * 0x20U));
	38	38		}
	39	39		else
	40	40		{
	41	41		//
	42	42		// Move through the linkPointer to find the most significant
	43	43		// bit position of 0
	44	44		//
	45	45		bitPos--;
	46	46		linkPointer = linkPointer << 1;
	47	47		}
	48	48		}
	49	49
	50	50		//
	51	51		// Perform dummy reads on the 128-bit password
	52	52		// Using linkPointer because it is no longer needed
	53	53		//
	54	54		linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD0);
	55	55		linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD1);
	56	56		linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD2);
	57	57		linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD3);
	58	58
	59	59		if(psCMDKey != NULL)
	60	60		{
	61	61		HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY0) = psCMDKey->csmKey0;
	62	62		HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY1) = psCMDKey->csmKey1;
	63	63		HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY2) = psCMDKey->csmKey2;
	64	64		HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY3) = psCMDKey->csmKey3;
	65	65		}
	66	66		}
	67	67

    DCSM_getZone1FlashEXEStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint16_t regValue;
		3	+	uint16_t statusBitShift;
		4	+	uint32_t regintValue;
	3	5		DCSM_EXEOnlyStatus status;
	4	6
	5	7		//
	6	8		// Check if sector belongs to this zone
	7	9		//
	8	10		if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE1)
	9	11		{
	10	12		status = DCSM_INCORRECT_ZONE;
	11	13		}
	12	14		else
	13	15		{
	14	16		//
	15	17		// Get the EXE status register
	16	18		//
		19	+	if(sector <= DCSM_SECTOR_15)
		20	+	{
		21	+	regintValue = ((HWREG(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECT1R)) &
		22	+	DCSM_EXEONLYSECTR_M);
		23	+	statusBitShift = (uint16_t)sector;
		24	+	regValue = (uint16_t)regintValue;
		25	+	}
		26	+	else if(sector <= DCSM_SECTOR_31)
		27	+	{
	17		-	regValue = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECTR);
		28	+	regintValue = ((HWREG(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECT1R))
		29	+	>> DCSM_EXEONLYSECTR_S);
		30	+
		31	+	regValue = (uint16_t)regintValue;
		32	+	statusBitShift = (uint16_t)sector & 0xFU;
		33	+	}
		34	+	else
		35	+	{
		36	+	regintValue = ((HWREG(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECT2R)) &
		37	+	DCSM_EXEONLYSECTR_M);
		38	+	regValue = (uint16_t)regintValue;
		39	+	statusBitShift = (uint16_t)sector & 0xFU;
		40	+	}
	18	41		//
	19	42		// Get the EXE status of the Flash Sector
	20	43		//
n	21		-	status = (DCSM_EXEOnlyStatus)((uint16_t)
		44	+	status = (DCSM_EXEOnlyStatus)(uint16_t)(((regValue >> statusBitShift) &
	22		-	((regValue >> (uint16_t)sector) &
	23		-	0x01U));
		45	+	0x01U));
	24	46		}
	25	47		return(status);
	26	48		}
	27	49

    DCSM_getZone1RAMEXEStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(module != DCSM_CLA);
	3	3		uint32_t status;
	4	4
	5	5		//
	6	6		// Check if module belongs to this zone
	7	7		//
	8	8		if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE1)
	9	9		{
	10	10		status = DCSM_INCORRECT_ZONE;
	11	11		}
	12	12		else
	13	13		{
	14	14		//
	15	15		// Get the EXE status of the RAM Module
	16	16		//
n	17		-	status = (uint16_t)((HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYRAMR) >>
		17	+	status = (uint16_t)((HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYRAM1R) >>
	18	18		(uint16_t)module) & 0x01U);
	19	19		}
	20	20		return((DCSM_EXEOnlyStatus)status);
	21	21		}
	22	22

    DCSM_getZone2FlashEXEStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint16_t regValue;
		3	+	uint16_t statusBitShift;
		4	+	uint32_t regintValue;
	3	5		DCSM_EXEOnlyStatus status;
	4	6
	5	7		//
	6	8		// Check if sector belongs to this zone
	7	9		//
	8	10		if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE2)
	9	11		{
	10	12		status = DCSM_INCORRECT_ZONE;
	11	13		}
	12	14		else
	13	15		{
	14	16		//
	15	17		// Get the EXE status register
	16	18		//
		19	+	if(sector <= DCSM_SECTOR_15)
		20	+	{
		21	+	regintValue = ((HWREG(DCSM_Z2_BASE +
		22	+	DCSM_O_Z2_EXEONLYSECT1R)) &
		23	+	DCSM_EXEONLYSECTR_M);
		24	+	statusBitShift = (uint16_t)sector;
		25	+	regValue = (uint16_t)regintValue;
		26	+	}
		27	+	else if(sector <= DCSM_SECTOR_31)
		28	+	{
	17		-	regValue = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYSECTR);
		29	+	regintValue = ((HWREG(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYSECT1R))
		30	+	>> DCSM_EXEONLYSECTR_S);
		31	+
		32	+	regValue = (uint16_t)regintValue;
		33	+	statusBitShift = (uint16_t)sector & 0xFU;
		34	+	}
		35	+	else
		36	+	{
		37	+	regintValue = ((HWREG(DCSM_Z2_BASE +
		38	+	DCSM_O_Z2_EXEONLYSECT2R)) &
		39	+	DCSM_EXEONLYSECTR_M);
		40	+	regValue = (uint16_t)regintValue;
		41	+	statusBitShift = (uint16_t)sector & 0xFU;
		42	+	}
	18	43		//
	19	44		// Get the EXE status of the Flash Sector
	20	45		//
t	21	46		status = (DCSM_EXEOnlyStatus)((uint16_t)((regValue >>
	22		-	(uint16_t)sector) & 0x01U));
		47	+	0x01U));
	23	48		}
	24	49
	25	50		return(status);
	26	51		}
	27	52

    DCSM_getZone2RAMEXEStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(module != DCSM_CLA);
	3	3		uint32_t status;
	4	4
	5	5		//
	6	6		// Check if module belongs to this zone
	7	7		//
	8	8		if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE2)
	9	9		{
	10	10		status = DCSM_INCORRECT_ZONE;
	11	11		}
	12	12		else
	13	13		{
	14	14		//
	15	15		// Get the EXE status of the RAM Module
	16	16		//
n	17		-	status = (uint16_t)((HWREGH(DCSM_Z2_BASE +
		17	+	status = (uint16_t)((HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYRAM1R) >>
	18		-	DCSM_O_Z2_EXEONLYRAMR) >> (uint16_t)module) & 0x01U);
		18	+	(uint16_t)module) & 0x01U);
	19	19		}
	20	20		return((DCSM_EXEOnlyStatus)status);
	21	21		}
	22	22

    DCSM_secureZone1

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Write to the FORCESEC bit.
	4	4		//
n	5		-	HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR)|= DCSM_Z1_CR_FORCESEC;
		5	+	HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CR)|= DCSM_Z1_CR_FORCESEC;
	6	6		}
	7	7

    DCSM_secureZone2

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Write to the FORCESEC bit.
	4	4		//
n	5		-	HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR)|= DCSM_Z2_CR_FORCESEC;
		5	+	HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CR)|= DCSM_Z2_CR_FORCESEC;
	6	6		}
	7	7

    DCSM_getZone1CSMSecurityStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	uint16_t status;
		2	+	uint32_t status;
	3	3		DCSM_SecurityStatus returnStatus;
n	4		-	status = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR);
		4	+	status = HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CR);
	5	5
	6	6		//
n	7		-	// if ARMED bit is set and UNSECURED bit or ALLONE bit or both UNSECURED
		7	+	// if ARMED bit is set and UNSECURED bit is set then CSM is unsecured.
	8		-	// and ALLONE bits are set then CSM is unsecured. Else it is secure.
		8	+	// Else it is secure.
	9	9		//
	10	10		if(((status & DCSM_Z1_CR_ARMED) != 0U) &&
n	11		-	(((status & DCSM_Z1_CR_UNSECURE) != 0U) ||
		11	+	((status & DCSM_Z1_CR_UNSECURE) != 0U))
	12		-	((status & DCSM_Z1_CR_ALLONE) != 0U )))
	13	12		{
	14	13		returnStatus = DCSM_STATUS_UNSECURE;
		14	+	}
		15	+	else if((status & DCSM_Z1_CR_ALLONE) == DCSM_Z1_CR_ALLONE)
		16	+	{
		17	+	returnStatus = DCSM_STATUS_BLOCKED;
	15	18		}
	16	19		else if((status & DCSM_Z1_CR_ALLZERO) == DCSM_Z1_CR_ALLZERO)
	17	20		{
	18	21		returnStatus = DCSM_STATUS_LOCKED;
	19	22		}
	20	23		else
	21	24		{
	22	25		returnStatus = DCSM_STATUS_SECURE;
	23	26		}
	24	27
	25	28		return(returnStatus);
	26	29		}
	27	30

    DCSM_getZone2CSMSecurityStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	uint16_t status;
		2	+	uint32_t status;
	3	3		DCSM_SecurityStatus returnStatus;
n	4		-	status = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR);
		4	+	status = HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CR);
	5	5
	6	6		//
n	7		-	// if ARMED bit is set and UNSECURED bit or ALLONE bit or both UNSECURED
		7	+	// if ARMED bit is set and UNSECURED bit is set then CSM is unsecured.
	8		-	// and ALLONE bits are set then CSM is unsecured. Else it is secure.
		8	+	// Else it is secure.
	9	9		//
	10	10		if(((status & DCSM_Z2_CR_ARMED) != 0U) &&
n	11		-	(((status & DCSM_Z2_CR_UNSECURE) != 0U) ||
		11	+	((status & DCSM_Z2_CR_UNSECURE) != 0U))
	12		-	((status & DCSM_Z2_CR_ALLONE) != 0U )))
	13	12		{
	14	13		returnStatus = DCSM_STATUS_UNSECURE;
		14	+	}
		15	+	else if((status & DCSM_Z2_CR_ALLONE) == DCSM_Z2_CR_ALLONE)
		16	+	{
		17	+	returnStatus = DCSM_STATUS_BLOCKED;
	15	18		}
	16	19		else if((status & DCSM_Z2_CR_ALLZERO) == DCSM_Z2_CR_ALLZERO)
	17	20		{
	18	21		returnStatus = DCSM_STATUS_LOCKED;
	19	22		}
	20	23		else
	21	24		{
	22	25		returnStatus = DCSM_STATUS_SECURE;
	23	26		}
	24	27
	25	28		return(returnStatus);
	26	29		}
	27	30

    DCSM_getZone1ControlStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	uint32_t stat;
	2	3		//
	3	4		// Return the contents of the CR register.
	4	5		//
n	5		-	return(HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR));
		6	+
		7	+	stat = ((HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CR)) >> DCSM_ZX_CR_S);
		8	+
		9	+	return((uint16_t)stat);
	6	10
	7	11		}
	8	12

    DCSM_getZone2ControlStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	uint32_t stat;
	2	3		//
	3	4		// Return the contents of the CR register.
	4	5		//
n	5		-	return(HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR));
		6	+	stat = ((HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CR)) >> DCSM_ZX_CR_S);
		7	+
		8	+	return((uint16_t)stat);
	6	9		}
	7	10

    DCSM_getRAMZone

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint16_t shift = (uint16_t)module * 2U;
	3	3		uint32_t RAMStatus;
	4	4		//
	5	5		//Read the RAMSTAT register for the specific RAM Module.
	6	6		//
n	7		-	RAMStatus = ((HWREG(DCSMCOMMON_BASE + DCSM_O_RAMSTAT) >>
		7	+	RAMStatus = ((HWREG(DCSMCOMMON_BASE + DCSM_O_RAMSTAT1) >>
	8	8		shift) & 0x03U);
	9	9		return((DCSM_MemoryStatus)RAMStatus);
	10	10		}
	11	11

    DCSM_getFlashSectorZone

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t sectStat;
	3	3		uint16_t shift;
	4	4
	5	5		//
	6	6		// Get the Sector status register for the specific bank
	7	7		//
		8	+	if(sector <= DCSM_SECTOR_15)
		9	+	{
	8		-	sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT);
		10	+	sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT1);
	9		-	shift = (uint16_t)sector * 2U;
		11	+	shift = (uint16_t)sector * 2U;
		12	+	}
		13	+	else if(sector <= DCSM_SECTOR_31)
		14	+	{
		15	+	sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT2);
		16	+	shift = ((uint16_t)sector & 0xFU) * (uint16_t)2U;
		17	+	}
		18	+	else
		19	+	{
		20	+	sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT3);
		21	+	shift = ((uint16_t)sector & 0xFU) * (uint16_t)2U;
		22	+	}
	10	23
	11	24		//
	12	25		//Read the SECTSTAT register for the specific Flash Sector.
	13	26		//
	14	27		return((DCSM_MemoryStatus)((uint16_t)((sectStat >> shift) & 0x3U)));
	15	28		}
	16	29

    DCSM_writeZone1CSM

    DCSM_writeZone2CSM

    DCSM_readZone1CSMPwd

    DCSM_readZone2CSMPwd

    DCSM_getFlashErrorStatus

    DCSM_clearFlashErrorStatus

    DCSM_forceFlashErrorStatus

    DCSM_getZone1OTPSecureLockStatus

    DCSM_getZone2OTPSecureLockStatus

    DCSM_getFlashDenyCodeStatus

    DCSM_getRAMOpenStatus

    DCSM_forceRAMOpenStatus

    DCSM_clearRAMOpenStatus

    DCSM_setRAMOpenLockStatus

dma

driver_inclusive_terminology_mapping

ecap

    Register Differences

f2837xd	f280013x	Description
-	ECCTL0	Capture Control Register 0
-	ECCTL0.INPUTSEL	INPUT source select
-	ECCTL2.CTRFILTRESET	Reset event filter, modulus counter, and interrupt
-	ECCTL2.MODCNTRSTS	modulo counter status
-	SYNCINSEL	SYNC source select register
-	SYNCINSEL.SEL	SYNCIN source select

    ECAP_setEmulationMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Write to FREE/SOFT bit
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL1) =
	9	10		((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_FREE_SOFT_M)) |
	10	11		((uint16_t)mode << ECAP_ECCTL1_FREE_SOFT_S));
		12	+	EDIS;
	11	13		}
	12	14

    ECAP_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		return(
	3	3		(base == ECAP1_BASE) ||
n	4		-	(base == ECAP2_BASE) ||
	5		-	(base == ECAP3_BASE) ||
	6		-	(base == ECAP4_BASE) ||
	7		-	(base == ECAP5_BASE) ||
	8		-	(base == ECAP6_BASE)
		4	+	(base == ECAP2_BASE)
	9	5		);
	10	6		}
	11	7

    ECAP_setEventPrescaler

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
	4	4		ASSERT(preScalerValue < ECAP_MAX_PRESCALER_VALUE);
	5	5
		6	+	EALLOW;
	6	7
	7	8		//
	8	9		// Write to PRESCALE bit
	9	10		//
	10	11		HWREGH(base + ECAP_O_ECCTL1) =
	11	12		((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_PRESCALE_M)) |
	12	13		(preScalerValue << ECAP_ECCTL1_PRESCALE_S));
		14	+	EDIS;
	13	15		}
	14	16

    ECAP_setEventPolarity

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2
	3	3		uint16_t shift;
	4	4
	5	5		ASSERT(ECAP_isBaseValid(base));
	6	6
	7	7		shift = ((uint16_t)event) << 1U;
	8	8
		9	+	EALLOW;
	9	10
	10	11		//
	11	12		// Write to CAP1POL, CAP2POL, CAP3POL or CAP4POL
	12	13		//
	13	14		HWREGH(base + ECAP_O_ECCTL1) =
	14	15		(HWREGH(base + ECAP_O_ECCTL1) & ~(1U << shift)) |
	15	16		((uint16_t)polarity << shift);
		17	+	EDIS;
	16	18		}
	17	19

    ECAP_setCaptureMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Write to CONT/ONESHT
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL2) =
	9	10		((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_CONT_ONESHT)) |
	10	11		(uint16_t)mode);
	11	12
	12	13		//
	13	14		// Write to STOP_WRAP
	14	15		//
	15	16		HWREGH(base + ECAP_O_ECCTL2) =
	16	17		((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_STOP_WRAP_M)) |
	17	18		(((uint16_t)event) << ECAP_ECCTL2_STOP_WRAP_S ));
		19	+	EDIS;
	18	20		}
	19	21

    ECAP_reArm

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Write to RE-ARM bit
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_REARM;
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_enableInterrupt

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3		ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 |
	4	4		ECAP_ISR_SOURCE_CAPTURE_EVENT_2 |
	5	5		ECAP_ISR_SOURCE_CAPTURE_EVENT_3 |
	6	6		ECAP_ISR_SOURCE_CAPTURE_EVENT_4 |
	7	7		ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
	8	8		ECAP_ISR_SOURCE_COUNTER_PERIOD |
	9	9		ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U);
	10	10
	11	11
		12	+	EALLOW;
	12	13
	13	14		//
	14	15		// Set bits in ECEINT register
	15	16		//
	16	17		HWREGH(base + ECAP_O_ECEINT) |= intFlags;
		18	+	EDIS;
	17	19		}
	18	20

    ECAP_disableInterrupt

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2
	3	3		ASSERT(ECAP_isBaseValid(base));
	4	4		ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 |
	5	5		ECAP_ISR_SOURCE_CAPTURE_EVENT_2 |
	6	6		ECAP_ISR_SOURCE_CAPTURE_EVENT_3 |
	7	7		ECAP_ISR_SOURCE_CAPTURE_EVENT_4 |
	8	8		ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
	9	9		ECAP_ISR_SOURCE_COUNTER_PERIOD |
	10	10		ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U);
	11	11
		12	+	EALLOW;
	12	13
	13	14		//
	14	15		// Clear bits in ECEINT register
	15	16		//
	16	17		HWREGH(base + ECAP_O_ECEINT) &= ~intFlags;
		18	+	EDIS;
	17	19		}
	18	20

    ECAP_forceInterrupt

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3		ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 |
	4	4		ECAP_ISR_SOURCE_CAPTURE_EVENT_2 |
	5	5		ECAP_ISR_SOURCE_CAPTURE_EVENT_3 |
	6	6		ECAP_ISR_SOURCE_CAPTURE_EVENT_4 |
	7	7		ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
	8	8		ECAP_ISR_SOURCE_COUNTER_PERIOD |
	9	9		ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U);
	10	10
		11	+	EALLOW;
	11	12
	12	13		//
	13	14		// Write to ECFRC register
	14	15		//
	15	16		HWREGH(base + ECAP_O_ECFRC) = intFlags;
		17	+	EDIS;
	16	18		}
	17	19

    ECAP_enableCaptureMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Clear CAP/APWM bit
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_CAP_APWM;
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_enableAPWMMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Set CAP/APWM bit
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_CAP_APWM;
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_enableCounterResetOnEvent

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL1) |= 1U << ((2U * (uint16_t)event) + 1U);
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_disableCounterResetOnEvent

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL1) &= ~(1U << ((2U * (uint16_t)event) + 1U));
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_enableTimeStampCapture

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Set CAPLDEN bit
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL1) |= ECAP_ECCTL1_CAPLDEN;
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_disableTimeStampCapture

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Clear CAPLDEN bit
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL1) &= ~ECAP_ECCTL1_CAPLDEN;
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_enableLoadCounter

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2
	3	3		ASSERT(ECAP_isBaseValid(base));
	4	4
		5	+	EALLOW;
	5	6
	6	7		//
	7	8		// Write to SYNCI_EN
	8	9		//
	9	10		HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SYNCI_EN;
		11	+	EDIS;
	10	12		}
	11	13

    ECAP_disableLoadCounter

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2
	3	3		ASSERT(ECAP_isBaseValid(base));
	4	4
		5	+	EALLOW;
	5	6
	6	7		//
	7	8		// Write to SYNCI_EN
	8	9		//
	9	10		HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_SYNCI_EN;
		11	+	EDIS;
	10	12		}
	11	13

    ECAP_loadCounter

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Write to SWSYNC
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SWSYNC;
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_setSyncOutMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Write to SYNCO_SEL
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL2) =
	9	10		((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_SYNCO_SEL_M)) |
	10	11		(uint16_t)mode);
		12	+	EDIS;
	11	13		}
	12	14

    ECAP_stopCounter

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Clear TSCTR
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_TSCTRSTOP;
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_startCounter

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5
	5	6		//
	6	7		// Set TSCTR
	7	8		//
	8	9		HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_TSCTRSTOP;
		10	+	EDIS;
	9	11		}
	10	12

    ECAP_setAPWMPolarity

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(ECAP_isBaseValid(base));
	3	3
		4	+	EALLOW;
	4	5		HWREGH(base + ECAP_O_ECCTL2) =
	5	6		((HWREGH(base + ECAP_O_ECCTL2) & ~ECAP_ECCTL2_APWMPOL) |
	6	7		(uint16_t)polarity);
		8	+	EDIS;
	7	9		}
	8	10

    ECAP_setSyncInPulseSource

    ECAP_selectECAPInput

    ECAP_resetCounters

    ECAP_getModuloCounterStatus

emif

epg

epwm

    Enumeration Differences

Type	f2837xd	f280013x	Description
EPWM_ActionQualifierTriggerSource	-	EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT	Digital compare filter event
EPWM_CurrentLink	EPWM_LINK_WITH_EPWM_8	-	link current ePWM with ePWM8
EPWM_CurrentLink	EPWM_LINK_WITH_EPWM_9	-	link current ePWM with ePWM9
EPWM_CurrentLink	EPWM_LINK_WITH_EPWM_10	-	link current ePWM with ePWM10
EPWM_CurrentLink	EPWM_LINK_WITH_EPWM_11	-	link current ePWM with ePWM11
EPWM_CurrentLink	EPWM_LINK_WITH_EPWM_12	-	link current ePWM with ePWM12
EPWM_DigitalCompareBlankingPulse	-	EPWM_DC_WINDOW_START_BLANK_PULSE_MIX	Blank pulse mix
EPWM_SyncOutPulseMode	EPWM_SYNC_OUT_PULSE_ON_SOFTWARE	-	Sync pulse is generated by software
EPWM_SyncOutPulseMode	EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN	-	Sync pulse is passed from EPWMxSYNCIN
EPWM_SyncOutPulseMode	EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO	-	Sync pulse is generated when time base counter equals zero
EPWM_SyncOutPulseMode	EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B	-	Sync pulse is generated when time base counter equals compare B value
EPWM_SyncOutPulseMode	EPWM_SYNC_OUT_PULSE_DISABLED	-	Sync pulse is disabled
EPWM_SyncOutPulseMode	EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C	-	Sync pulse is generated when time base counter equals compare C value
EPWM_SyncOutPulseMode	EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D	-	Sync pulse is generated when time base counter equals compare D value

    Register Differences

f2837xd	f280013x	Description
TBCTL.SYNCOSEL	-	Sync Output Select
TBCTL2.SYNCOSELX	-	Syncout selection
-	SYNCINSEL	EPWMxSYNCIN Source Select Register
-	SYNCINSEL.SEL	EPWMxSYNCI source select
-	SYNCOUTEN	EPWMxSYNCOUT Source Enable Register
-	SYNCOUTEN.SWEN	EPWMxSYNCO Software Force Enable
-	SYNCOUTEN.ZEROEN	EPWMxSYNCO Zero Count Event Enable
-	SYNCOUTEN.CMPBEN	EPWMxSYNCO Compare B Event Enable
-	SYNCOUTEN.CMPCEN	EPWMxSYNCO Compare C Event Enable
-	SYNCOUTEN.CMPDEN	EPWMxSYNCO Compare D Event Enable
-	SYNCOUTEN.DCAEVT1EN	EPWMxSYNCO Digital Compare A Event 1 Sync Enable
-	SYNCOUTEN.DCBEVT1EN	EPWMxSYNCO Digital Compare B Event 1 Sync Enable
-	TBCTL3	Time Base Control Register 3
-	TBCTL3.OSSFRCEN	One Shot Sync Force Enable
-	DCACTL.EVT1LATSEL	DCAEVT1 Latched signal select
-	DCACTL.EVT1LATCLRSEL	DCAEVT1 Latched clear source select
-	DCACTL.EVT1LAT	Indicates the status of DCAEVT1LAT signal.
-	DCACTL.EVT2LATSEL	DCAEVT2 Latched signal select
-	DCACTL.EVT2LATCLRSEL	DCAEVT2 Latched clear source select
-	DCACTL.EVT2LAT	Indicates the status of DCAEVT2LAT signal.
-	DCBCTL.EVT1LATSEL	DCBEVT1 Latched signal select
-	DCBCTL.EVT1LATCLRSEL	DCBEVT1 Latched clear source select
-	DCBCTL.EVT1LAT	Indicates the status of DCBEVT1LAT signal.
-	DCBCTL.EVT2LATSEL	DCBEVT2 Latched signal select
-	DCBCTL.EVT2LATCLRSEL	DCBEVT2 Latched clear source select
-	DCBCTL.EVT2LAT	Indicates the status of DCBEVT2LAT signal.
-	BLANKPULSEMIXSEL	Blanking window trigger pulse select register
-	BLANKPULSEMIXSEL.ZRO	Zero match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.PRD	Period match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.CAU	CMPA up-count match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.CAD	CMPA down-count match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.CBU	CMPB up-count match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.CBD	CMPB down-count match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.CCU	CMPC up-count match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.CCD	CMPC down-count match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.CDU	CMPD up-count match enable to BLANKPULSEMIX
-	BLANKPULSEMIXSEL.CDD	CMPD down-count match enable to BLANKPULSEMIX
-	LOCK	EPWM Lock Register
-	LOCK.HRLOCK	HRPWM Register Set Lock
-	LOCK.GLLOCK	Global Load Register Set Lock
-	LOCK.TZCFGLOCK	TripZone Register Set Lock
-	LOCK.TZCLRLOCK	TripZone Clear Register Set Lock
-	LOCK.DCLOCK	Digital Compare Register Set Lock
-	LOCK.KEY	Key to write to this register

    EPWM_configureSignal

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		float32_t tbClkInHz = 0.0F;
	3	3		uint16_t tbPrdVal = 0U, cmpAVal = 0U, cmpBVal = 0U;
	4	4
	5	5		//
	6	6		// Check the arguments.
	7	7		//
	8	8		ASSERT(EPWM_isBaseValid(base));
	9	9
	10	10		//
	11	11		// Valid values in the function for TBCTR Mode are UP, DOWN
	12	12		// and UP-DOWN count.
	13	13		//
	14	14		ASSERT((uint16_t)signalParams->tbCtrMode <= 2U);
	15	15
	16	16		//
n	17		-	// Configure EPWM clock Divider
	18		-	//
	19		-	SysCtl_setEPWMClockDivider(signalParams->epwmClkDiv);
	20		-
	21		-	//
	22	17		// Configure Time Base counter Clock
	23	18		//
	24	19		EPWM_setClockPrescaler(base, signalParams->tbClkDiv,
	25	20		signalParams->tbHSClkDiv);
	26	21
	27	22		//
	28	23		// Configure Time Base Counter Mode
	29	24		//
	30	25		EPWM_setTimeBaseCounterMode(base, signalParams->tbCtrMode);
	31	26
	32	27		//
	33	28		// Calculate TBCLK, TBPRD and CMPx values to be configured for
	34	29		// achieving desired signal
	35	30		//
	36	31		tbClkInHz = ((float32_t)signalParams->sysClkInHz /
n	37		-	(float32_t)(1U << ((uint16_t)signalParams->epwmClkDiv +
		32	+	(float32_t)(1U << (uint16_t)signalParams->tbClkDiv));
	38		-	(uint16_t)signalParams->tbClkDiv)));
	39	33
	40	34		if(signalParams->tbHSClkDiv <= EPWM_HSCLOCK_DIVIDER_4)
	41	35		{
	42	36		tbClkInHz /= (float32_t)(1U << (uint16_t)signalParams->tbHSClkDiv);
	43	37		}
	44	38		else
	45	39		{
	46	40		tbClkInHz /= (float32_t)(2U * (uint16_t)signalParams->tbHSClkDiv);
	47	41		}
	48	42
	49	43		if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP)
	50	44		{
	51	45		tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f);
	52	46		cmpAVal = (uint16_t)(signalParams->dutyValA *
	53	47		(float32_t)(tbPrdVal + 1U));
	54	48		cmpBVal = (uint16_t)(signalParams->dutyValB *
	55	49		(float32_t)(tbPrdVal + 1U));
	56	50		}
	57	51		else if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN)
	58	52		{
	59	53		tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f);
	60	54		cmpAVal = (uint16_t)((float32_t)(tbPrdVal + 1U) -
	61	55		(signalParams->dutyValA * (float32_t)(tbPrdVal + 1U)));
	62	56		cmpBVal = (uint16_t)((float32_t)(tbPrdVal + 1U) -
	63	57		(signalParams->dutyValB * (float32_t)(tbPrdVal + 1U)));
	64	58		}
	65	59		else
	66	60		{
	67	61		tbPrdVal = (uint16_t)(tbClkInHz / (2.0f * signalParams->freqInHz));
	68	62		cmpAVal = (uint16_t)(((float32_t)tbPrdVal -
	69	63		((signalParams->dutyValA *
	70	64		(float32_t)tbPrdVal))) + 0.5f);
	71	65		cmpBVal = (uint16_t)(((float32_t)tbPrdVal -
	72	66		((signalParams->dutyValB *
	73	67		(float32_t)tbPrdVal))) + 0.5f);
	74	68		}
	75	69
	76	70		//
	77	71		// Configure TBPRD value
	78	72		//
	79	73		EPWM_setTimeBasePeriod(base, tbPrdVal);
	80	74
	81	75		//
	82	76		// Default Configurations.
	83	77		//
	84	78		EPWM_disablePhaseShiftLoad(base);
	85	79		EPWM_setPhaseShift(base, 0U);
	86	80		EPWM_setTimeBaseCounter(base, 0U);
	87	81
	88	82		//
	89	83		// Setup shadow register load on ZERO
	90	84		//
	91	85		EPWM_setCounterCompareShadowLoadMode(base,
	92	86		EPWM_COUNTER_COMPARE_A,
	93	87		EPWM_COMP_LOAD_ON_CNTR_ZERO);
	94	88		EPWM_setCounterCompareShadowLoadMode(base,
	95	89		EPWM_COUNTER_COMPARE_B,
	96	90		EPWM_COMP_LOAD_ON_CNTR_ZERO);
	97	91		//
	98	92		// Set Compare values
	99	93		//
	100	94		EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A,
	101	95		cmpAVal);
	102	96		EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B,
	103	97		cmpBVal);
	104	98
	105	99		//
	106	100		// Set actions for ePWMxA & ePWMxB
	107	101		//
	108	102		if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP)
	109	103		{
	110	104		//
	111	105		// Set PWMxA on Zero
	112	106		//
	113	107		EPWM_setActionQualifierAction(base,
	114	108		EPWM_AQ_OUTPUT_A,
	115	109		EPWM_AQ_OUTPUT_HIGH,
	116	110		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	117	111
	118	112		//
	119	113		// Clear PWMxA on event A, up count
	120	114		//
	121	115		EPWM_setActionQualifierAction(base,
	122	116		EPWM_AQ_OUTPUT_A,
	123	117		EPWM_AQ_OUTPUT_LOW,
	124	118		EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
	125	119
	126	120		if(signalParams->invertSignalB == true)
	127	121		{
	128	122		//
	129	123		// Clear PWMxB on Zero
	130	124		//
	131	125		EPWM_setActionQualifierAction(base,
	132	126		EPWM_AQ_OUTPUT_B,
	133	127		EPWM_AQ_OUTPUT_LOW,
	134	128		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	135	129		//
	136	130		// Set PWMxB on event B, up count
	137	131		//
	138	132		EPWM_setActionQualifierAction(base,
	139	133		EPWM_AQ_OUTPUT_B,
	140	134		EPWM_AQ_OUTPUT_HIGH,
	141	135		EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	142	136		}
	143	137		else
	144	138		{
	145	139		//
	146	140		// Set PWMxB on Zero
	147	141		//
	148	142		EPWM_setActionQualifierAction(base,
	149	143		EPWM_AQ_OUTPUT_B,
	150	144		EPWM_AQ_OUTPUT_HIGH,
	151	145		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	152	146		//
	153	147		// Clear PWMxB on event B, up count
	154	148		//
	155	149		EPWM_setActionQualifierAction(base,
	156	150		EPWM_AQ_OUTPUT_B,
	157	151		EPWM_AQ_OUTPUT_LOW,
	158	152		EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	159	153
	160	154		}
	161	155		}
	162	156		else if((signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN))
	163	157		{
	164	158		//
	165	159		// Set PWMxA on Zero
	166	160		//
	167	161		EPWM_setActionQualifierAction(base,
	168	162		EPWM_AQ_OUTPUT_A,
	169	163		EPWM_AQ_OUTPUT_HIGH,
	170	164		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	171	165
	172	166		//
	173	167		// Clear PWMxA on event A, down count
	174	168		//
	175	169		EPWM_setActionQualifierAction(base,
	176	170		EPWM_AQ_OUTPUT_A,
	177	171		EPWM_AQ_OUTPUT_LOW,
	178	172		EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
	179	173
	180	174		if(signalParams->invertSignalB == true)
	181	175		{
	182	176		//
	183	177		// Clear PWMxB on Zero
	184	178		//
	185	179		EPWM_setActionQualifierAction(base,
	186	180		EPWM_AQ_OUTPUT_B,
	187	181		EPWM_AQ_OUTPUT_LOW,
	188	182		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	189	183		//
	190	184		// Set PWMxB on event B, down count
	191	185		//
	192	186		EPWM_setActionQualifierAction(base,
	193	187		EPWM_AQ_OUTPUT_B,
	194	188		EPWM_AQ_OUTPUT_HIGH,
	195	189		EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
	196	190		}
	197	191		else
	198	192		{
	199	193		//
	200	194		// Set PWMxB on Zero
	201	195		//
	202	196		EPWM_setActionQualifierAction(base,
	203	197		EPWM_AQ_OUTPUT_B,
	204	198		EPWM_AQ_OUTPUT_HIGH,
	205	199		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	206	200		//
	207	201		// Clear PWMxB on event B, down count
	208	202		//
	209	203		EPWM_setActionQualifierAction(base,
	210	204		EPWM_AQ_OUTPUT_B,
	211	205		EPWM_AQ_OUTPUT_LOW,
	212	206		EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
	213	207		}
	214	208		}
	215	209		else
	216	210		{
	217	211		//
	218	212		// Clear PWMxA on Zero
	219	213		//
	220	214		EPWM_setActionQualifierAction(base,
	221	215		EPWM_AQ_OUTPUT_A,
	222	216		EPWM_AQ_OUTPUT_LOW,
	223	217		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	224	218
	225	219		//
	226	220		// Set PWMxA on event A, up count
	227	221		//
	228	222		EPWM_setActionQualifierAction(base,
	229	223		EPWM_AQ_OUTPUT_A,
	230	224		EPWM_AQ_OUTPUT_HIGH,
	231	225		EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
	232	226
	233	227		//
	234	228		// Clear PWMxA on event A, down count
	235	229		//
	236	230		EPWM_setActionQualifierAction(base,
	237	231		EPWM_AQ_OUTPUT_A,
	238	232		EPWM_AQ_OUTPUT_LOW,
	239	233		EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
	240	234
	241	235		if(signalParams->invertSignalB == true)
	242	236		{
	243	237		//
	244	238		// Set PWMxB on Zero
	245	239		//
	246	240		EPWM_setActionQualifierAction(base,
	247	241		EPWM_AQ_OUTPUT_B,
	248	242		EPWM_AQ_OUTPUT_HIGH,
	249	243		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	250	244
	251	245		//
	252	246		// Clear PWMxB on event B, up count
	253	247		//
	254	248		EPWM_setActionQualifierAction(base,
	255	249		EPWM_AQ_OUTPUT_B,
	256	250		EPWM_AQ_OUTPUT_LOW,
	257	251		EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	258	252		//
	259	253		// Set PWMxB on event B, down count
	260	254		//
	261	255		EPWM_setActionQualifierAction(base,
	262	256		EPWM_AQ_OUTPUT_B,
	263	257		EPWM_AQ_OUTPUT_HIGH,
	264	258		EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
	265	259		}
	266	260		else
	267	261		{
	268	262		//
	269	263		// Clear PWMxB on Zero
	270	264		//
	271	265		EPWM_setActionQualifierAction(base,
	272	266		EPWM_AQ_OUTPUT_B,
	273	267		EPWM_AQ_OUTPUT_LOW,
	274	268		EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
	275	269
	276	270		//
	277	271		// Set PWMxB on event B, up count
	278	272		//
	279	273		EPWM_setActionQualifierAction(base,
	280	274		EPWM_AQ_OUTPUT_B,
	281	275		EPWM_AQ_OUTPUT_HIGH,
	282	276		EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	283	277		//
	284	278		// Clear PWMxB on event B, down count
	285	279		//
	286	280		EPWM_setActionQualifierAction(base,
	287	281		EPWM_AQ_OUTPUT_B,
	288	282		EPWM_AQ_OUTPUT_LOW,
	289	283		EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
	290	284		}
	291	285		}
	292	286		}
	293	287

    EPWM_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		return(
	3	3		(base == EPWM1_BASE) ||
	4	4		(base == EPWM2_BASE) ||
	5	5		(base == EPWM3_BASE) ||
	6	6		(base == EPWM4_BASE) ||
	7	7		(base == EPWM5_BASE) ||
	8	8		(base == EPWM6_BASE) ||
n	9		-	(base == EPWM7_BASE) ||
		9	+	(base == EPWM7_BASE)
	10		-	(base == EPWM8_BASE) ||
	11		-	(base == EPWM9_BASE) ||
	12		-	(base == EPWM10_BASE) ||
	13		-	(base == EPWM11_BASE) ||
	14		-	(base == EPWM12_BASE)
	15	10		);
	16	11		}
	17	12

    EPWM_setSyncOutPulseMode

    EPWM_setSyncInPulseSource

    EPWM_enableSyncOutPulseSource

    EPWM_disableSyncOutPulseSource

    EPWM_setOneShotSyncOutTrigger

    EPWM_setDigitalCompareCBCLatchMode

    EPWM_selectDigitalCompareCBCLatchClearEvent

    EPWM_getDigitalCompareCBCLatchStatus

    EPWM_lockRegisters

epwmxbar

eqep

    Enumeration Differences

Type	f2837xd	f280013x	Description
EQEP_INT	-	EQEP_INT_QMA_ERROR	QMA error

    Register Differences

f2837xd	f280013x	Description
-	QDECCTL.QIDIRE	Qep Index Direction Enhancement enable
-	QEINT.QMAE	QMA error interrupt enable
-	QFLG.QMAE	QMA error interrupt flag
-	QCLR.QMAE	Clear QMA error interrupt flag
-	QFRC.QMAE	Force QMA error interrupt
-	REV	QEP Revision Number
-	REV.MAJOR	Major Revision Number
-	REV.MINOR	Minor Revision Number
-	QEPSTROBESEL	QEP Strobe select register
-	QEPSTROBESEL.STROBESEL	QMA Mode Select
-	QMACTRL	QMA Control register
-	QMACTRL.MODE	QMA Mode Select
-	QEPSRCSEL	QEP Source Select Register
-	QEPSRCSEL.QEPASEL	QEPA Source select
-	QEPSRCSEL.QEPBSEL	QEPB Source select
-	QEPSRCSEL.QEPISEL	QEPI Source select
-	QEPSRCSEL.QEPSSEL	QEPS Source select

    EQEP_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		return(
n	3		-	(base == EQEP1_BASE) ||
	4		-	(base == EQEP2_BASE) ||
	5		-	(base == EQEP3_BASE)
		3	+	(base == EQEP1_BASE)
	6	4		);
	7	5		}
	8	6

    EQEP_setQMAModuleMode

    EQEP_setStrobeSource

    EQEP_enableDirectionChangeDuringIndex

    EQEP_disableDirectionChangeDuringIndex

    EQEP_selectSource

flash

    Enumeration Differences

Type	f2837xd	f280013x	Description
FLASH_PUMP_KEY	FLASH_PUMP_KEY	-	Pump semaphore key
Flash_BankNumber	FLASH_BANK	-	Bank
Flash_BankPowerMode	FLASH_BANK_PWR_SLEEP	-	Sleep fallback mode
Flash_BankPowerMode	FLASH_BANK_PWR_STANDBY	-	Standby fallback mode
Flash_BankPowerMode	FLASH_BANK_PWR_ACTIVE	-	Active fallback mode
Flash_ErrorStatus	FLASH_NO_ERR	-	No error
Flash_ErrorStatus	FLASH_FAIL_0	-	Fail on 0
Flash_ErrorStatus	FLASH_FAIL_1	-	Fail on 1
Flash_ErrorStatus	FLASH_UNC_ERR	-	Uncorrectable error
Flash_ErrorType	FLASH_DATA_ERR	-	Data error
Flash_ErrorType	FLASH_ECC_ERR	-	ECC error
Flash_PumpOwnership	FLASH_CPU1_WRAPPER	-	CPU1 Wrapper
Flash_PumpOwnership	FLASH_CPU2_WRAPPER	-	CPU2 Wrapper
Flash_PumpPowerMode	FLASH_PUMP_PWR_SLEEP	-	Sleep fallback mode
Flash_PumpPowerMode	FLASH_PUMP_PWR_ACTIVE	-	Active fallback mode
Flash_SingleBitErrorIndicator	FLASH_DATA_BITS	-	Data bits
Flash_SingleBitErrorIndicator	FLASH_CHECK_BITS	-	ECC bits

    Register Differences

f2837xd	f280013x	Description
FBAC	-	Flash Bank Access Control Register
FBAC.VREADST	-	VREAD Setup Time Count
FBFALLBACK	-	Flash Bank Fallback Power Register
FBFALLBACK.BNKPWR0	-	Bank Power Mode
FBPRDY	-	Flash Bank Pump Ready Register
FBPRDY.BANKRDY	-	Flash Bank Active Power State
FBPRDY.PUMPRDY	-	Flash Pump Active Power Mode
FPAC1	-	Flash Pump Access Control Register 1
FPAC1.PMPPWR	-	Charge Pump Fallback Power Mode
FPAC1.PSLEEP	-	Pump Sleep Down Count
FMSTAT	-	Flash Module Status Register
FMSTAT.PSUSP	-	Program Suspend.
FMSTAT.ESUSP	-	Erase Suspend.
FMSTAT.VOLTSTAT	-	Flash Pump Power Status
FMSTAT.CSTAT	-	Command Fail Status
FMSTAT.INVDAT	-	Invalid Data
FMSTAT.PGM	-	Program Operation Status
FMSTAT.ERS	-	Erase Operation Status
FMSTAT.BUSY	-	Busy Bit
FMSTAT.EV	-	Erase Verify Status
FMSTAT.PGV	-	Programming Verify Status
SINGLE_ERR_ADDR_LOW	-	Single Error Address Low
SINGLE_ERR_ADDR_HIGH	-	Single Error Address High
UNC_ERR_ADDR_LOW	-	Uncorrectable Error Address Low
UNC_ERR_ADDR_HIGH	-	Uncorrectable Error Address High
ERR_STATUS	-	Error Status
ERR_STATUS.FAIL_0_L	-	Lower 64bits Single Bit Error Corrected Value 0
ERR_STATUS.FAIL_1_L	-	Lower 64bits Single Bit Error Corrected Value 1
ERR_STATUS.UNC_ERR_L	-	Lower 64 bits Uncorrectable error occurred
ERR_STATUS.FAIL_0_H	-	Upper 64bits Single Bit Error Corrected Value 0
ERR_STATUS.FAIL_1_H	-	Upper 64bits Single Bit Error Corrected Value 1
ERR_STATUS.UNC_ERR_H	-	Upper 64 bits Uncorrectable error occurred
ERR_STATUS.CLR_FAIL_0_L_CLR	-	Lower 64bits Single Bit Error Corrected
ERR_STATUS.CLR_FAIL_1_L_CLR	-	Lower 64bits Single Bit Error Corrected
ERR_STATUS.CLR_UNC_ERR_L_CLR	-	Lower 64 bits Uncorrectable error
ERR_STATUS.CLR_FAIL_0_H_CLR	-	Upper 64bits Single Bit Error Corrected
ERR_STATUS.CLR_FAIL_1_H_CLR	-	Upper 64bits Single Bit Error Corrected
ERR_STATUS.CLR_UNC_ERR_H_CLR	-	Upper 64 bits Uncorrectable error
ERR_POS	-	Error Position
ERR_POS.ERR_POS_L	-	Bit Position of Single bit Error in lower 64
ERR_POS.ERR_TYPE_L	-	Error Type in lower 64 bits
ERR_POS.ERR_POS_H	-	Bit Position of Single bit Error in upper 64
ERR_POS.ERR_TYPE_H	-	Error Type in upper 64 bits
ERR_STATUS_CLR	-	Error Status Clear
ERR_STATUS_CLR.FAIL_0_L_CLR	-	Lower 64bits Single Bit Error Corrected
ERR_STATUS_CLR.FAIL_1_L_CLR	-	Lower 64bits Single Bit Error Corrected
ERR_STATUS_CLR.UNC_ERR_L_CLR	-	Lower 64 bits Uncorrectable error
ERR_STATUS_CLR.FAIL_0_H_CLR	-	Upper 64bits Single Bit Error Corrected
ERR_STATUS_CLR.FAIL_1_H_CLR	-	Upper 64bits Single Bit Error Corrected
ERR_STATUS_CLR.UNC_ERR_H_CLR	-	Upper 64 bits Uncorrectable error
ERR_CNT	-	Error Control
ERR_CNT.ERR_CNT	-	Error counter
ERR_THRESHOLD	-	Error Threshold
ERR_THRESHOLD.ERR_THRESHOLD	-	Error Threshold
ERR_INTFLG	-	Error Interrupt Flag
ERR_INTFLG.SINGLE_ERR_INTFLG	-	Single Error Interrupt Flag
ERR_INTFLG.UNC_ERR_INTFLG	-	Uncorrectable Interrupt Flag
ERR_INTCLR	-	Error Interrupt Flag Clear
ERR_INTCLR.SINGLE_ERR_INTCLR	-	Single Error Interrupt Flag Clear
ERR_INTCLR.UNC_ERR_INTCLR	-	Uncorrectable Interrupt Flag Clear
FDATAH_TEST	-	Data High Test
FDATAL_TEST	-	Data Low Test
FADDR_TEST	-	ECC Test Address
FADDR_TEST.ADDRL	-	ECC Address Low
FADDR_TEST.ADDRH	-	ECC Address High
FECC_TEST	-	ECC Test Address
FECC_TEST.ECC	-	ECC Control Bits
FECC_CTRL.ECC_SELECT	-	ECC Bit Select
FECC_CTRL.DO_ECC_CALC	-	Enable ECC Calculation
FOUTH_TEST	-	Test Data Out High
FOUTL_TEST	-	Test Data Out Low
FECC_STATUS	-	ECC Status
FECC_STATUS.SINGLE_ERR	-	Test Result is Single Bit Error
FECC_STATUS.UNC_ERR	-	Test Result is Uncorrectable Error
FECC_STATUS.DATA_ERR_POS	-	Holds Bit Position of Error
FECC_STATUS.ERR_TYPE	-	Holds Bit Position of 8 Check Bits of Error
PUMPREQUEST	-	Flash programming semaphore PUMP request register
PUMPREQUEST.PUMP_OWNERSHIP	-	Flash Pump Request Semaphore between
PUMPREQUEST.KEY	-	Key Qualifier for writes to this
-	FLPROT	Flash program/erase protect register
-	FLPROT.FLWEPROT	Flash write/erase protect bit.

    Flash_initModule

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(Flash_isCtrlBaseValid(ctrlBase));
	6	6		ASSERT(Flash_isECCBaseValid(eccBase));
	7	7		ASSERT(waitstates <= 0xFU);
	8	8
n	9		-	//
	10		-	// Set the bank power up delay so that the bank will power up properly.
	11		-	//
	12		-	Flash_setBankPowerUpDelay(ctrlBase, 0x14);
	13		-
	14		-	//
	15		-	// Set the bank fallback power mode to active.
	16		-	//
	17		-	Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE);
	18		-
	19		-	//
	20		-	// Power up flash bank and pump and this also sets the fall back mode of
	21		-	// flash and pump as active
	22		-	//
	23		-	Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE);
	24	9
	25	10		//
	26	11		// Disable cache and prefetch mechanism before changing wait states
	27	12		//
	28	13		Flash_disableCache(ctrlBase);
	29	14		Flash_disablePrefetch(ctrlBase);
	30	15
	31	16		//
	32	17		// Set waitstates according to frequency.
	33	18		//
	34	19		Flash_setWaitstates(ctrlBase, waitstates);
	35	20		//
	36	21		// Enable cache and prefetch mechanism to improve performance of code
	37	22		// executed from flash.
	38	23		//
	39	24		Flash_enableCache(ctrlBase);
	40	25		Flash_enablePrefetch(ctrlBase);
	41	26
	42	27		//
	43	28		// At reset, ECC is enabled.  If it is disabled by application software and
	44	29		// if application again wants to enable ECC.
	45	30		//
	46	31		Flash_enableECC(eccBase);
	47	32
	48	33		//
	49	34		// Force a pipeline flush to ensure that the write to the last register
	50	35		// configured occurs before returning.
	51	36		//
	52	37		FLASH_DELAY_CONFIG;
	53	38		}
	54	39

    Flash_powerDown

    Flash_wakeFromLPM

    Flash_isPumpSemBaseValid

    Flash_setBankPowerMode

    Flash_setPumpPowerMode

    Flash_setBankPowerUpDelay

    Flash_setPumpWakeupTime

    Flash_isBankReady

    Flash_isPumpReady

    Flash_getSingleBitErrorAddressLow

    Flash_getSingleBitErrorAddressHigh

    Flash_getUncorrectableErrorAddressLow

    Flash_getUncorrectableErrorAddressHigh

    Flash_getLowErrorStatus

    Flash_getHighErrorStatus

    Flash_getLowErrorPosition

    Flash_getHighErrorPosition

    Flash_getLowErrorType

    Flash_getHighErrorType

    Flash_clearLowErrorStatus

    Flash_clearHighErrorStatus

    Flash_getErrorCount

    Flash_setErrorThreshold

    Flash_getInterruptFlag

    Flash_clearSingleErrorInterruptFlag

    Flash_clearUncorrectableInterruptFlag

    Flash_setDataLowECCTest

    Flash_setDataHighECCTest

    Flash_setECCTestAddress

    Flash_setECCTestECCBits

    Flash_enableECCTestMode

    Flash_disableECCTestMode

    Flash_selectLowECCBlock

    Flash_selectHighECCBlock

    Flash_performECCCalculation

    Flash_getTestDataOutHigh

    Flash_getTestDataOutLow

    Flash_getECCTestStatus

    Flash_getECCTestErrorPosition

    Flash_getECCTestSingleBitErrorType

    Flash_claimPumpSemaphore

    Flash_releasePumpSemaphore

    Flash_setFLWEPROT

    Flash_enableSingleBitECCTestMode

    Flash_enableDoubleBitECCTestMode

    Flash_disableSingleBitECCTestMode

    Flash_disableDoubleBitECCTestMode

gpio

    Enumeration Differences

Type	f2837xd	f280013x	Description
GPIO_CoreSelect	GPIO_CORE_CPU1	-	CPU1 selected as controller core
GPIO_CoreSelect	GPIO_CORE_CPU1_CLA1	-	CPU1's CLA1 selected as controller core
GPIO_CoreSelect	GPIO_CORE_CPU2	-	CPU2 selected as controller core
GPIO_CoreSelect	GPIO_CORE_CPU2_CLA1	-	CPU2's CLA1 selected as controller core
GPIO_Port	GPIO_PORT_C	-	GPIO port C
GPIO_Port	GPIO_PORT_D	-	GPIO port D
GPIO_Port	GPIO_PORT_E	-	GPIO port E
GPIO_Port	GPIO_PORT_F	-	GPIO port F
GPIO_Port	-	GPIO_PORT_H	GPIO port H

    Register Differences

f2837xd	f280013x	Description
SEL3	-	GPIO A Core Select Register (GPIO16 to 23)
SEL4	-	GPIO A Core Select Register (GPIO24 to 31)
SEL3	-	GPIO B Core Select Register (GPIO48 to 55)
SEL4	-	GPIO B Core Select Register (GPIO56 to 63)
SEL3	-	GPIO C Core Select Register (GPIO80 to 87)
SEL4	-	GPIO C Core Select Register (GPIO88 to 95)
SEL3	-	GPIO D Core Select Register (GPIO112 to 119)
SEL4	-	GPIO D Core Select Register (GPIO120 to 127)
SEL3	-	GPIO E Core Select Register (GPIO144 to 151)
SEL4	-	GPIO E Core Select Register (GPIO152 to 159)
-	AT_R	GPIO A Data Read Register
-	AT_R	GPIO B Data Read Register
-	AT_R	GPIO H Data Read Register

    GPIO_setInterruptPin

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		XBAR_InputNum input;
	3	3
	4	4		//
	5	5		// Check the arguments.
	6	6		//
	7	7		ASSERT(GPIO_isPinValid(pin));
	8	8
	9	9		//
	10	10		// Pick the X-BAR input that corresponds to the requested XINT.
	11	11		//
	12	12		switch(extIntNum)
	13	13		{
	14	14		case GPIO_INT_XINT1:
	15	15		input = XBAR_INPUT4;
	16	16		break;
	17	17
	18	18		case GPIO_INT_XINT2:
	19	19		input = XBAR_INPUT5;
	20	20		break;
	21	21
	22	22		case GPIO_INT_XINT3:
	23	23		input = XBAR_INPUT6;
	24	24		break;
	25	25
	26	26		case GPIO_INT_XINT4:
	27	27		input = XBAR_INPUT13;
	28	28		break;
	29	29
	30	30		case GPIO_INT_XINT5:
	31	31		input = XBAR_INPUT14;
	32	32		break;
	33	33
	34	34		default:
	35	35		//
	36	36		// Invalid interrupt. Shouldn't happen if enum value is used.
	37	37		// XBAR_INPUT1 isn't tied to an XINT, so we'll use it to check for
	38	38		// a bad value.
	39	39		//
	40	40		input = XBAR_INPUT1;
	41	41		break;
	42	42		}
	43	43
	44	44		if(input != XBAR_INPUT1)
	45	45		{
n	46		-	XBAR_setInputPin(input, (uint16_t)pin);
		46	+	XBAR_setInputPin(INPUTXBAR_BASE, input, (uint16_t)pin);
	47	47		}
	48	48		}
	49	49

    GPIO_setControllerCore

    GPIO_setAnalogMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		volatile uint32_t *gpioBaseAddr;
	3	3		uint32_t pinMask;
	4	4
	5	5		//
	6	6		// Check the arguments.
	7	7		//
n	8		-	ASSERT((pin == 42U) || (pin == 43U));
		8	+	ASSERT(((pin >= 224U) && (pin <= 245U) && (pin != 229U) && (pin != 234U) &&
		9	+	(pin != 235U) && (pin != 236U) && (pin != 240U) && (pin != 243U)) ||
		10	+	(pin == 12U)   || (pin == 13U)  || (pin == 20U)  || (pin == 21U)  ||
		11	+	(pin == 28U));
	9	12
	10	13		pinMask = (uint32_t)1U << (pin % 32U);
	11	14		gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
	12	15		((pin / 32U) * GPIO_CTRL_REGS_STEP);
	13	16
	14	17		EALLOW;
	15	18
	16	19		//
	17	20		// Set the analog mode selection.
	18	21		//
	19	22		if(mode == GPIO_ANALOG_ENABLED)
	20	23		{
	21	24		//
	22	25		// Enable analog mode
	23	26		//
	24	27		gpioBaseAddr[GPIO_GPxAMSEL_INDEX] |= pinMask;
		28	+	if((pin == 12U)   || (pin == 13U)  || (pin == 20U)  || (pin == 21U)  ||
		29	+	(pin == 28U)   || (pin == 224U) || (pin == 226U) || (pin == 227U) ||
		30	+	(pin == 228U)  || (pin == 230U) || (pin == 242U))
		31	+	{
		32	+	//
		33	+	// Set AGPIOCTL
		34	+	//
		35	+	HWREG(ANALOGSUBSYS_BASE + ASYSCTL_O_AGPIOCTRLA +
		36	+	((pin / 32U) * 2U)) |= (pinMask);
		37	+	}
	25	38		}
	26	39		else
	27	40		{
	28	41		//
	29	42		// Disable analog mode
	30	43		//
	31	44		gpioBaseAddr[GPIO_GPxAMSEL_INDEX] &= ~pinMask;
		45	+	if((pin == 12U)   || (pin == 13U)  || (pin == 20U)  || (pin == 21U)  ||
		46	+	(pin == 28U)   || (pin == 224U) || (pin == 226U) || (pin == 227U) ||
		47	+	(pin == 228U)  || (pin == 230U) || (pin == 242U))
		48	+	{
		49	+	//
		50	+	// Clear AGPIOCTL
		51	+	//
		52	+	HWREG(ANALOGSUBSYS_BASE + ASYSCTL_O_AGPIOCTRLA +
		53	+	((pin / 32U) * 2U)) &= ~(pinMask);
		54	+	}
	32	55		}
	33	56
	34	57		EDIS;
	35	58		}
	36	59

    GPIO_isPinValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	return(pin <= 168U);
		2	+	return((pin <= 41U) || ((pin >= 224U) && (pin <= 245U)));
	3	3		}
	4	4

    GPIO_readPinDataRegister

    GPIO_readPortDataRegister

hic

hrpwm

    HRPWM_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	return((base == EPWM1_BASE) || (base == EPWM2_BASE) ||
		2	+	return((base == EPWM1_BASE));
	3		-	(base == EPWM3_BASE) || (base == EPWM4_BASE) ||
	4		-	(base == EPWM5_BASE) || (base == EPWM6_BASE) ||
	5		-	(base == EPWM7_BASE) || (base == EPWM8_BASE));
	6	3		}
	7	4

    HRPWM_lockRegisters

i2c

    Enumeration Differences

Type	f2837xd	f280013x	Description
I2C_STS	-	I2C_STS_BYTE_SENT	Byte transmit complete

    Register Differences

f2837xd	f280013x	Description
-	STR.BYTESENT	Byte transmit over indication
-	EMDR.FCM	Forward Compatibility for Tx behav in Type1

    I2C_setExtendedMode

inputxbar

interrupt

    Enumeration Differences

Pie Channel Legend

Color	Description
	Pie channel common for both devices
	Pie channel applicable only for C2000Ware 4.03.00.00\f2837xd
	C2000Ware 4.03.00.00\f2837xd INT has been replaced with new INT on C2000Ware 4.03.00.00\f280013x
	Pie channel applicable only for C2000Ware 4.03.00.00\f280013x

Pie Channel Mapping

	INTx.1	INTx.2	INTx.3	INTx.4	INTx.5	INTx.6	INTx.7	INTx.8	INTx.9	INTx.10	INTx.11	INTx.12	INTx.13	INTx.14	INTx.15	INTx.16
INT1.y	ADCA1	ADCC1	ADCC1	XINT1	XINT2	SYS_ERR[1]	TIMER0	WAKE	-	-	-	-	IPC_0	IPC_1	IPC_2	IPC_3
INT2.y	EPWM1_TZ	EPWM2_TZ	EPWM3_TZ	EPWM4_TZ	EPWM5_TZ	EPWM6_TZ	EPWM7_TZ	EPWM8_TZ	EPWM9_TZ	EPWM10_TZ	EPWM11_TZ	EPWM12_TZ	-	-	-	-
INT3.y	EPWM1	EPWM2	EPWM3	EPWM4	EPWM5	EPWM6	EPWM7	EPWM8	EPWM9	EPWM10	EPWM11	EPWM12	-	-	-	-
INT4.y	ECAP1	ECAP2	ECAP3	ECAP4	ECAP5	ECAP6	-	-	-	-	-	-	-	-	-	-
INT5.y	EQEP1	EQEP2	EQEP3	-	CLB1	CLB2	CLB3	CLB4	SD1	SD2	-	-	-	-	-	-
INT6.y	SPIA_RX	SPIA_TX	SPIB_RX	SPIB_TX	MCBSPA_RX	MCBSPA_TX	DCC0[2]	MCBSPB_TX	SPIC_RX	SPIC_TX	-	-	-	-	-	-
INT7.y	DMA_CH1	DMA_CH2	DMA_CH3	DMA_CH4	DMA_CH5	DMA_CH6	-	-	-	-	-	-	-	-	-	-
INT8.y	I2CA	I2CA_FIFO	I2CB	I2CB_FIFO	SCIC_RX	SCIC_TX	SCID_RX	SCID_TX	-	-	-	-	-	-	UPPA	-
INT9.y	SCIA_RX	SCIA_TX	SCIB_RX	SCIB_TX	CANA0	CANA1	CANB0	CANB1	-	-	-	-	-	-	USBA	-
INT10.y	ADCA_EVT	ADCA2	ADCA3	ADCA4	ADCC_EVT	ADCC2	ADCC3	ADCC4	ADCC_EVT	ADCC2	ADCC3	ADCC4	ADCD_EVT	ADCD2	ADCD3	ADCD4
INT11.y	CLA1_1	CLA1_2	CLA1_3	CLA1_4	CLA1_5	CLA1_6	CLA1_7	CLA1_8	-	-	-	-	-	-	-	-
INT12.y	XINT3	XINT4	XINT5	PBIST	FLSS[3]	VCU	FPU_OVERFLOW	FPU_UNDERFLOW	EMIF_ERROR	RAM_CORR_ERR	FLASH_CORR_ERR	RAM_ACC_VIOL	SYS_PLL_SLIP	AUX_PLL_SLIP	CLA_OVERFLOW	CLA_UNDERFLOW

[1] ADCD1 on f2837xd

[2] MCBSPB_RX on f2837xd

[3] FMC on f2837xd

ipc

mcbsp

memcfg

    Enumeration Differences

Type	f2837xd	f280013x	Description
MEMCFG_CERR	MEMCFG_CERR_CPUREAD	-	Correctable CPU read error
MEMCFG_CERR	MEMCFG_CERR_DMAREAD	-	Correctable DMA read error
MEMCFG_CERR	MEMCFG_CERR_CLA1READ	-	Correctable CLA1 read error
MEMCFG_MVIOL	MEMCFG_MVIOL_DMAWRITE	-	Controller DMA write access
MEMCFG_NMVIOL	MEMCFG_NMVIOL_CPUREAD	-	Non-controller CPU read access
MEMCFG_NMVIOL	MEMCFG_NMVIOL_CPUWRITE	-	Non-controller CPU write access
MEMCFG_NMVIOL	MEMCFG_NMVIOL_CPUFETCH	-	Non-controller CPU fetch access
MEMCFG_NMVIOL	MEMCFG_NMVIOL_DMAWRITE	-	Non-controller DMA write access
MEMCFG_NMVIOL	MEMCFG_NMVIOL_CLA1READ	-	Non-controller CLA1 read access
MEMCFG_NMVIOL	MEMCFG_NMVIOL_CLA1WRITE	-	Non-controller CLA1 write access
MEMCFG_NMVIOL	MEMCFG_NMVIOL_CLA1FETCH	-	Non-controller CLA1 fetch access
MEMCFG_PROT	MEMCFG_PROT_ALLOWDMAWRITE	-	DMA write allowed (GSxRAM)
MEMCFG_PROT	MEMCFG_PROT_BLOCKDMAWRITE	-	DMA write blocked (GSxRAM)
MEMCFG_SECT	MEMCFG_SECT_D0	-	D0 RAM
MEMCFG_SECT	MEMCFG_SECT_D1	-	D1 RAM
MEMCFG_SECT	MEMCFG_SECT_LS2	-	LS2 RAM
MEMCFG_SECT	MEMCFG_SECT_LS3	-	LS3 RAM
MEMCFG_SECT	MEMCFG_SECT_LS4	-	LS4 RAM
MEMCFG_SECT	MEMCFG_SECT_LS5	-	LS5 RAM
MEMCFG_SECT	MEMCFG_SECT_GS0	-	GS0 RAM
MEMCFG_SECT	MEMCFG_SECT_GS1	-	GS1 RAM
MEMCFG_SECT	MEMCFG_SECT_GS2	-	GS2 RAM
MEMCFG_SECT	MEMCFG_SECT_GS3	-	GS3 RAM
MEMCFG_SECT	MEMCFG_SECT_GS4	-	GS4 RAM
MEMCFG_SECT	MEMCFG_SECT_GS5	-	GS5 RAM
MEMCFG_SECT	MEMCFG_SECT_GS6	-	GS6 RAM
MEMCFG_SECT	MEMCFG_SECT_GS7	-	GS7 RAM
MEMCFG_SECT	MEMCFG_SECT_GS8	-	GS8 RAM
MEMCFG_SECT	MEMCFG_SECT_GS9	-	GS9 RAM
MEMCFG_SECT	MEMCFG_SECT_GS10	-	GS10 RAM
MEMCFG_SECT	MEMCFG_SECT_GS11	-	GS11 RAM
MEMCFG_SECT	MEMCFG_SECT_GS12	-	GS12 RAM
MEMCFG_SECT	MEMCFG_SECT_GS13	-	GS13 RAM
MEMCFG_SECT	MEMCFG_SECT_GS14	-	GS14 RAM
MEMCFG_SECT	MEMCFG_SECT_GS15	-	GS15 RAM
MEMCFG_SECT	MEMCFG_SECT_GSX_ALL	-	All GS RAM
MEMCFG_SECT	MEMCFG_SECT_MSGCPUTOCPU	-	CPU-to-CPU message RAM
MEMCFG_SECT	MEMCFG_SECT_MSGCPUTOCLA1	-	CPU-to-CLA1 message RAM
MEMCFG_SECT	MEMCFG_SECT_MSGCLA1TOCPU	-	CLA1-to-CPU message RAM
MEMCFG_SECT	MEMCFG_SECT_MSGX_ALL	-	All message RAM
MEMCFG_SECT	-	MEMCFG_SECT_PIEVECT	PIEVECT RAM
MEMCFG_SECT	-	MEMCFG_SECT_ROMBOOT	BOOT ROM
MEMCFG_SECT	-	MEMCFG_SECT_ROM_ALL	All ROMs
MEMCFG_UCERR	MEMCFG_UCERR_CPUREAD	-	Uncorrectable CPU read error
MEMCFG_UCERR	MEMCFG_UCERR_DMAREAD	-	Uncorrectable DMA read error
MEMCFG_UCERR	MEMCFG_UCERR_CLA1READ	-	Uncorrectable CLA1 read error
MemCfg_CLAMemoryType	MEMCFG_CLA_MEM_DATA	-	Section is CLA data memory
MemCfg_CLAMemoryType	MEMCFG_CLA_MEM_PROGRAM	-	Section is CLA program memory
MemCfg_GSRAMControllerSel	MEMCFG_GSRAMCONTROLLER_CPU1	-	CPU1 is controller of the section
MemCfg_GSRAMControllerSel	MEMCFG_GSRAMCONTROLLER_CPU2	-	CPU2 is controller of the section
MemCfg_LSRAMControllerSel	MEMCFG_LSRAMCONTROLLER_CPU_ONLY	-	CPU is the owner of the section
MemCfg_LSRAMControllerSel	MEMCFG_LSRAMCONTROLLER_CPU_CLA1	-	CPU and CLA1 share this section
MemCfg_TestMode	-	MEMCFG_TEST_FUNC_DIAG	Diagnostic mode, similar to functional mode but NMI is not generated.

    Register Differences

f2837xd	f280013x	Description
DXLOCK.LOCK_D0	-	D0 RAM access protection and master select fields lock
DXLOCK.LOCK_D1	-	D1 RAM access protection and master select fields lock
DXCOMMIT.COMMIT_D0	-	D0 RAM access protection and master select permanent
DXCOMMIT.COMMIT_D1	-	D1 RAM access protection and master select permanent
DXACCPROT0.FETCHPROT_D0	-	Fetch Protection For D0 RAM
DXACCPROT0.CPUWRPROT_D0	-	CPU WR Protection For D0 RAM
DXACCPROT0.FETCHPROT_D1	-	Fetch Protection For D1 RAM
DXACCPROT0.CPUWRPROT_D1	-	CPU WR Protection For D1 RAM
DXTEST.TEST_D0	-	Selects the different modes for D0 RAM
DXTEST.TEST_D1	-	Selects the different modes for D1 RAM
DXINIT.INIT_D0	-	RAM Initialization control for D0 RAM.
DXINIT.INIT_D1	-	RAM Initialization control for D1 RAM.
DXINITDONE.INITDONE_D0	-	RAM Initialization status for D0 RAM.
DXINITDONE.INITDONE_D1	-	RAM Initialization status for D1 RAM.
LSXLOCK.LOCK_LS2	-	LS2 RAM access protection and master select fields
LSXLOCK.LOCK_LS3	-	LS3 RAM access protection and master select fields
LSXLOCK.LOCK_LS4	-	LS4 RAM access protection and master select fields
LSXLOCK.LOCK_LS5	-	LS5 RAM access protection and master select fields
LSXCOMMIT.COMMIT_LS2	-	LS2 RAM access protection and master select
LSXCOMMIT.COMMIT_LS3	-	LS3 RAM access protection and master select
LSXCOMMIT.COMMIT_LS4	-	LS4 RAM access protection and master select
LSXCOMMIT.COMMIT_LS5	-	LS5 RAM access protection and master select
LSXMSEL	-	Local Shared RAM Master Sel Register
LSXMSEL.MSEL_LS0	-	Master Select for LS0 RAM
LSXMSEL.MSEL_LS1	-	Master Select for LS1 RAM
LSXMSEL.MSEL_LS2	-	Master Select for LS2 RAM
LSXMSEL.MSEL_LS3	-	Master Select for LS3 RAM
LSXMSEL.MSEL_LS4	-	Master Select for LS4 RAM
LSXMSEL.MSEL_LS5	-	Master Select for LS5 RAM
LSXCLAPGM	-	Local Shared RAM Prog/Exe control Register
LSXCLAPGM.CLAPGM_LS0	-	Selects LS0 RAM as program vs data memory for CLA
LSXCLAPGM.CLAPGM_LS1	-	Selects LS1 RAM as program vs data memory for CLA
LSXCLAPGM.CLAPGM_LS2	-	Selects LS2 RAM as program vs data memory for CLA
LSXCLAPGM.CLAPGM_LS3	-	Selects LS3 RAM as program vs data memory for CLA
LSXCLAPGM.CLAPGM_LS4	-	Selects LS4 RAM as program vs data memory for CLA
LSXCLAPGM.CLAPGM_LS5	-	Selects LS5 RAM as program vs data memory for CLA
LSXACCPROT0.FETCHPROT_LS2	-	Fetch Protection For LS2 RAM
LSXACCPROT0.CPUWRPROT_LS2	-	CPU WR Protection For LS2 RAM
LSXACCPROT0.FETCHPROT_LS3	-	Fetch Protection For LS3 RAM
LSXACCPROT0.CPUWRPROT_LS3	-	CPU WR Protection For LS3 RAM
LSXACCPROT1	-	Local Shared RAM Config Register 1
LSXACCPROT1.FETCHPROT_LS4	-	Fetch Protection For LS4 RAM
LSXACCPROT1.CPUWRPROT_LS4	-	CPU WR Protection For LS4 RAM
LSXACCPROT1.FETCHPROT_LS5	-	Fetch Protection For LS5 RAM
LSXACCPROT1.CPUWRPROT_LS5	-	CPU WR Protection For LS5 RAM
LSXTEST.TEST_LS2	-	Selects the different modes for LS2 RAM
LSXTEST.TEST_LS3	-	Selects the different modes for LS3 RAM
LSXTEST.TEST_LS4	-	Selects the different modes for LS4 RAM
LSXTEST.TEST_LS5	-	Selects the different modes for LS5 RAM
LSXINIT.INIT_LS2	-	RAM Initialization control for LS2 RAM.
LSXINIT.INIT_LS3	-	RAM Initialization control for LS3 RAM.
LSXINIT.INIT_LS4	-	RAM Initialization control for LS4 RAM.
LSXINIT.INIT_LS5	-	RAM Initialization control for LS5 RAM.
LSXINITDONE.INITDONE_LS2	-	RAM Initialization status for LS2 RAM.
LSXINITDONE.INITDONE_LS3	-	RAM Initialization status for LS3 RAM.
LSXINITDONE.INITDONE_LS4	-	RAM Initialization status for LS4 RAM.
LSXINITDONE.INITDONE_LS5	-	RAM Initialization status for LS5 RAM.
GSXLOCK	-	Global Shared RAM Config Lock Register
GSXLOCK.LOCK_GS0	-	GS0 RAM access protection and master select fields
GSXLOCK.LOCK_GS1	-	GS1 RAM access protection and master select fields
GSXLOCK.LOCK_GS2	-	GS2 RAM access protection and master select fields
GSXLOCK.LOCK_GS3	-	GS3 RAM access protection and master select fields
GSXLOCK.LOCK_GS4	-	GS4 RAM access protection and master select fields
GSXLOCK.LOCK_GS5	-	GS5 RAM access protection and master select fields
GSXLOCK.LOCK_GS6	-	GS6 RAM access protection and master select fields
GSXLOCK.LOCK_GS7	-	GS7 RAM access protection and master select fields
GSXLOCK.LOCK_GS8	-	GS8 RAM access protection and master select fields
GSXLOCK.LOCK_GS9	-	GS9 RAM access protection and master select fields
GSXLOCK.LOCK_GS10	-	GS10 RAM access protection and master select fields
GSXLOCK.LOCK_GS11	-	GS11 RAM access protection and master select fields
GSXLOCK.LOCK_GS12	-	GS12 RAM access protection and master select fields
GSXLOCK.LOCK_GS13	-	GS13 RAM access protection and master select fields
GSXLOCK.LOCK_GS14	-	GS14 RAM access protection and master select fields
GSXLOCK.LOCK_GS15	-	GS15 RAM access protection and master select fields
GSXCOMMIT	-	Global Shared RAM Config Lock Commit Register
GSXCOMMIT.COMMIT_GS0	-	GS0 RAM access protection and master select
GSXCOMMIT.COMMIT_GS1	-	GS1 RAM access protection and master select
GSXCOMMIT.COMMIT_GS2	-	GS2 RAM access protection and master select
GSXCOMMIT.COMMIT_GS3	-	GS3 RAM access protection and master select
GSXCOMMIT.COMMIT_GS4	-	GS4 RAM access protection and master select
GSXCOMMIT.COMMIT_GS5	-	GS5 RAM access protection and master select
GSXCOMMIT.COMMIT_GS6	-	GS6 RAM access protection and master select
GSXCOMMIT.COMMIT_GS7	-	GS7 RAM access protection and master select
GSXCOMMIT.COMMIT_GS8	-	GS8 RAM access protection and master select
GSXCOMMIT.COMMIT_GS9	-	GS9 RAM access protection and master select
GSXCOMMIT.COMMIT_GS10	-	GS10 RAM access protection and master select
GSXCOMMIT.COMMIT_GS11	-	GS11 RAM access protection and master select
GSXCOMMIT.COMMIT_GS12	-	GS12 RAM access protection and master select
GSXCOMMIT.COMMIT_GS13	-	GS13 RAM access protection and master select
GSXCOMMIT.COMMIT_GS14	-	GS14 RAM access protection and master select
GSXCOMMIT.COMMIT_GS15	-	GS15 RAM access protection and master select
GSXMSEL	-	Global Shared RAM Master Sel Register
GSXMSEL.MSEL_GS0	-	Master Select for GS0 RAM
GSXMSEL.MSEL_GS1	-	Master Select for GS1 RAM
GSXMSEL.MSEL_GS2	-	Master Select for GS2 RAM
GSXMSEL.MSEL_GS3	-	Master Select for GS3 RAM
GSXMSEL.MSEL_GS4	-	Master Select for GS4 RAM
GSXMSEL.MSEL_GS5	-	Master Select for GS5 RAM
GSXMSEL.MSEL_GS6	-	Master Select for GS6 RAM
GSXMSEL.MSEL_GS7	-	Master Select for GS7 RAM
GSXMSEL.MSEL_GS8	-	Master Select for GS8 RAM
GSXMSEL.MSEL_GS9	-	Master Select for GS9 RAM
GSXMSEL.MSEL_GS10	-	Master Select for GS10 RAM
GSXMSEL.MSEL_GS11	-	Master Select for GS11 RAM
GSXMSEL.MSEL_GS12	-	Master Select for GS12 RAM
GSXMSEL.MSEL_GS13	-	Master Select for GS13 RAM
GSXMSEL.MSEL_GS14	-	Master Select for GS14 RAM
GSXMSEL.MSEL_GS15	-	Master Select for GS15 RAM
GSXACCPROT0	-	Global Shared RAM Config Register 0
GSXACCPROT0.FETCHPROT_GS0	-	Fetch Protection For GS0 RAM
GSXACCPROT0.CPUWRPROT_GS0	-	CPU WR Protection For GS0 RAM
GSXACCPROT0.DMAWRPROT_GS0	-	DMA WR Protection For GS0 RAM
GSXACCPROT0.FETCHPROT_GS1	-	Fetch Protection For GS1 RAM
GSXACCPROT0.CPUWRPROT_GS1	-	CPU WR Protection For GS1 RAM
GSXACCPROT0.DMAWRPROT_GS1	-	DMA WR Protection For GS1 RAM
GSXACCPROT0.FETCHPROT_GS2	-	Fetch Protection For GS2 RAM
GSXACCPROT0.CPUWRPROT_GS2	-	CPU WR Protection For GS2 RAM
GSXACCPROT0.DMAWRPROT_GS2	-	DMA WR Protection For GS2 RAM
GSXACCPROT0.FETCHPROT_GS3	-	Fetch Protection For GS3 RAM
GSXACCPROT0.CPUWRPROT_GS3	-	CPU WR Protection For GS3 RAM
GSXACCPROT0.DMAWRPROT_GS3	-	DMA WR Protection For GS3 RAM
GSXACCPROT1	-	Global Shared RAM Config Register 1
GSXACCPROT1.FETCHPROT_GS4	-	Fetch Protection For GS4 RAM
GSXACCPROT1.CPUWRPROT_GS4	-	CPU WR Protection For GS4 RAM
GSXACCPROT1.DMAWRPROT_GS4	-	DMA WR Protection For GS4 RAM
GSXACCPROT1.FETCHPROT_GS5	-	Fetch Protection For GS5 RAM
GSXACCPROT1.CPUWRPROT_GS5	-	CPU WR Protection For GS5 RAM
GSXACCPROT1.DMAWRPROT_GS5	-	DMA WR Protection For GS5RAM
GSXACCPROT1.FETCHPROT_GS6	-	Fetch Protection For GS6 RAM
GSXACCPROT1.CPUWRPROT_GS6	-	CPU WR Protection For GS6 RAM
GSXACCPROT1.DMAWRPROT_GS6	-	DMA WR Protection For GS6RAM
GSXACCPROT1.FETCHPROT_GS7	-	Fetch Protection For GS7 RAM
GSXACCPROT1.CPUWRPROT_GS7	-	CPU WR Protection For GS7 RAM
GSXACCPROT1.DMAWRPROT_GS7	-	DMA WR Protection For GS7RAM
GSXACCPROT2	-	Global Shared RAM Config Register 2
GSXACCPROT2.FETCHPROT_GS8	-	Fetch Protection For GS8 RAM
GSXACCPROT2.CPUWRPROT_GS8	-	CPU WR Protection For GS8 RAM
GSXACCPROT2.DMAWRPROT_GS8	-	DMA WR Protection For GS8 RAM
GSXACCPROT2.FETCHPROT_GS9	-	Fetch Protection For GS9 RAM
GSXACCPROT2.CPUWRPROT_GS9	-	CPU WR Protection For GS9 RAM
GSXACCPROT2.DMAWRPROT_GS9	-	DMA WR Protection For GS9RAM
GSXACCPROT2.FETCHPROT_GS10	-	Fetch Protection For GS10 RAM
GSXACCPROT2.CPUWRPROT_GS10	-	CPU WR Protection For GS10 RAM
GSXACCPROT2.DMAWRPROT_GS10	-	DMA WR Protection For GS10RAM
GSXACCPROT2.FETCHPROT_GS11	-	Fetch Protection For GS11 RAM
GSXACCPROT2.CPUWRPROT_GS11	-	CPU WR Protection For GS11 RAM
GSXACCPROT2.DMAWRPROT_GS11	-	DMA WR Protection For GS11RAM
GSXACCPROT3	-	Global Shared RAM Config Register 3
GSXACCPROT3.FETCHPROT_GS12	-	Fetch Protection For GS12 RAM
GSXACCPROT3.CPUWRPROT_GS12	-	CPU WR Protection For GS12 RAM
GSXACCPROT3.DMAWRPROT_GS12	-	DMA WR Protection For GS12 RAM
GSXACCPROT3.FETCHPROT_GS13	-	Fetch Protection For GS13 RAM
GSXACCPROT3.CPUWRPROT_GS13	-	CPU WR Protection For GS13 RAM
GSXACCPROT3.DMAWRPROT_GS13	-	DMA WR Protection For GS13RAM
GSXACCPROT3.FETCHPROT_GS14	-	Fetch Protection For GS14 RAM
GSXACCPROT3.CPUWRPROT_GS14	-	CPU WR Protection For GS14 RAM
GSXACCPROT3.DMAWRPROT_GS14	-	DMA WR Protection For GS14RAM
GSXACCPROT3.FETCHPROT_GS15	-	Fetch Protection For GS15 RAM
GSXACCPROT3.CPUWRPROT_GS15	-	CPU WR Protection For GS15 RAM
GSXACCPROT3.DMAWRPROT_GS15	-	DMA WR Protection For GS15RAM
GSXTEST	-	Global Shared RAM TEST Register
GSXTEST.TEST_GS0	-	Selects the different modes for GS0 RAM
GSXTEST.TEST_GS1	-	Selects the different modes for GS1 RAM
GSXTEST.TEST_GS2	-	Selects the different modes for GS2 RAM
GSXTEST.TEST_GS3	-	Selects the different modes for GS3 RAM
GSXTEST.TEST_GS4	-	Selects the different modes for GS4 RAM
GSXTEST.TEST_GS5	-	Selects the different modes for GS5 RAM
GSXTEST.TEST_GS6	-	Selects the different modes for GS6 RAM
GSXTEST.TEST_GS7	-	Selects the different modes for GS7 RAM
GSXTEST.TEST_GS8	-	Selects the different modes for GS8 RAM
GSXTEST.TEST_GS9	-	Selects the different modes for GS9 RAM
GSXTEST.TEST_GS10	-	Selects the different modes for GS10 RAM
GSXTEST.TEST_GS11	-	Selects the different modes for GS11 RAM
GSXTEST.TEST_GS12	-	Selects the different modes for GS12 RAM
GSXTEST.TEST_GS13	-	Selects the different modes for GS13 RAM
GSXTEST.TEST_GS14	-	Selects the different modes for GS14 RAM
GSXTEST.TEST_GS15	-	Selects the different modes for GS15 RAM
GSXINIT	-	Global Shared RAM Init Register
GSXINIT.INIT_GS0	-	RAM Initialization control for GS0 RAM.
GSXINIT.INIT_GS1	-	RAM Initialization control for GS1 RAM.
GSXINIT.INIT_GS2	-	RAM Initialization control for GS2 RAM.
GSXINIT.INIT_GS3	-	RAM Initialization control for GS3 RAM.
GSXINIT.INIT_GS4	-	RAM Initialization control for GS4 RAM.
GSXINIT.INIT_GS5	-	RAM Initialization control for GS5 RAM.
GSXINIT.INIT_GS6	-	RAM Initialization control for GS6 RAM.
GSXINIT.INIT_GS7	-	RAM Initialization control for GS7 RAM.
GSXINIT.INIT_GS8	-	RAM Initialization control for GS8 RAM.
GSXINIT.INIT_GS9	-	RAM Initialization control for GS9 RAM.
GSXINIT.INIT_GS10	-	RAM Initialization control for GS10 RAM.
GSXINIT.INIT_GS11	-	RAM Initialization control for GS11 RAM.
GSXINIT.INIT_GS12	-	RAM Initialization control for GS12 RAM.
GSXINIT.INIT_GS13	-	RAM Initialization control for GS13 RAM.
GSXINIT.INIT_GS14	-	RAM Initialization control for GS14 RAM.
GSXINIT.INIT_GS15	-	RAM Initialization control for GS15 RAM.
GSXINITDONE	-	Global Shared RAM InitDone Status Register
GSXINITDONE.INITDONE_GS0	-	RAM Initialization status for GS0 RAM.
GSXINITDONE.INITDONE_GS1	-	RAM Initialization status for GS1 RAM.
GSXINITDONE.INITDONE_GS2	-	RAM Initialization status for GS2 RAM.
GSXINITDONE.INITDONE_GS3	-	RAM Initialization status for GS3 RAM.
GSXINITDONE.INITDONE_GS4	-	RAM Initialization status for GS4 RAM.
GSXINITDONE.INITDONE_GS5	-	RAM Initialization status for GS5 RAM.
GSXINITDONE.INITDONE_GS6	-	RAM Initialization status for GS6 RAM.
GSXINITDONE.INITDONE_GS7	-	RAM Initialization status for GS7 RAM.
GSXINITDONE.INITDONE_GS8	-	RAM Initialization status for GS8 RAM.
GSXINITDONE.INITDONE_GS9	-	RAM Initialization status for GS9 RAM.
GSXINITDONE.INITDONE_GS10	-	RAM Initialization status for GS10 RAM.
GSXINITDONE.INITDONE_GS11	-	RAM Initialization status for GS11 RAM.
GSXINITDONE.INITDONE_GS12	-	RAM Initialization status for GS12 RAM.
GSXINITDONE.INITDONE_GS13	-	RAM Initialization status for GS13 RAM.
GSXINITDONE.INITDONE_GS14	-	RAM Initialization status for GS14 RAM.
GSXINITDONE.INITDONE_GS15	-	RAM Initialization status for GS15 RAM.
MSGXTEST	-	Message RAM TEST Register
MSGXTEST.TEST_CPUTOCPU	-	CPU to CPU Mode Select
MSGXTEST.TEST_CPUTOCLA1	-	CPU to CLA1 MSG RAM Mode Select
MSGXTEST.TEST_CLA1TOCPU	-	CLA1 to CPU MSG RAM Mode Select
MSGXINIT	-	Message RAM Init Register
MSGXINIT.INIT_CPUTOCPU	-	Initialization control for CPU to CPU MSG RAM
MSGXINIT.INIT_CPUTOCLA1	-	Initialization control for CPUTOCLA1 MSG RAM
MSGXINIT.INIT_CLA1TOCPU	-	Initialization control for CLA1TOCPU MSG RAM
MSGXINITDONE	-	Message RAM InitDone Status Register
MSGXINITDONE.INITDONE_CPUTOCPU	-	Initialization status for CPU to CPU MSG
MSGXINITDONE.INITDONE_CPUTOCLA1	-	Initialization status for CPU to CLA1
MSGXINITDONE.INITDONE_CLA1TOCPU	-	Initialization status for CLA1 to CPU
EMIF1LOCK	-	EMIF1 Config Lock Register
EMIF1LOCK.LOCK_EMIF1	-	EMIF1 access protection and master select fields
EMIF1COMMIT	-	EMIF1 Config Lock Commit Register
EMIF1COMMIT.COMMIT_EMIF1	-	EMIF1 access protection and master select
EMIF1MSEL	-	EMIF1 Master Sel Register
EMIF1MSEL.MSEL_EMIF1	-	Master Select for EMIF1.
EMIF1MSEL.KEY	-	KEY to enable the write into MSEL_EMIF1
EMIF1ACCPROT0	-	EMIF1 Config Register 0
EMIF1ACCPROT0.FETCHPROT_EMIF1	-	Fetch Protection For EMIF1
EMIF1ACCPROT0.CPUWRPROT_EMIF1	-	CPU WR Protection For EMIF1
EMIF1ACCPROT0.DMAWRPROT_EMIF1	-	DMA WR Protection For EMIF1
EMIF2LOCK	-	EMIF2 Config Lock Register
EMIF2LOCK.LOCK_EMIF2	-	EMIF2 access protection and master select permanent
EMIF2COMMIT	-	EMIF2 Config Lock Commit Register
EMIF2COMMIT.COMMIT_EMIF2	-	EMIF2 access protection and master select
EMIF2ACCPROT0	-	EMIF2 Config Register 0
EMIF2ACCPROT0.FETCHPROT_EMIF2	-	Fetch Protection For EMIF2
EMIF2ACCPROT0.CPUWRPROT_EMIF2	-	CPU WR Protection For EMIF2
NMAVFLG	-	Non-Master Access Violation Flag Register
NMAVFLG.CPUREAD	-	Non Master CPU Read Access Violation Flag
NMAVFLG.CPUWRITE	-	Non Master CPU Write Access Violation Flag
NMAVFLG.CPUFETCH	-	Non Master CPU Fetch Access Violation Flag
NMAVFLG.DMAWRITE	-	Non Master DMA Write Access Violation Flag
NMAVFLG.CLA1READ	-	Non Master CLA1 Read Access Violation Flag
NMAVFLG.CLA1WRITE	-	Non Master CLA1 Write Access Violation Flag
NMAVFLG.CLA1FETCH	-	Non Master CLA1 Fetch Access Violation Flag
NMAVSET	-	Non-Master Access Violation Flag Set Register
NMAVSET.CPUREAD	-	Non Master CPU Read Access Violation Flag Set
NMAVSET.CPUWRITE	-	Non Master CPU Write Access Violation Flag Set
NMAVSET.CPUFETCH	-	Non Master CPU Fetch Access Violation Flag Set
NMAVSET.DMAWRITE	-	Non Master DMA Write Access Violation Flag Set
NMAVSET.CLA1READ	-	Non Master CLA1 Read Access Violation Flag Set
NMAVSET.CLA1WRITE	-	Non Master CLA1 Write Access Violation Flag Set
NMAVSET.CLA1FETCH	-	Non Master CLA1 Fetch Access Violation Flag Set
NMAVCLR	-	Non-Master Access Violation Flag Clear Register
NMAVCLR.CPUREAD	-	Non Master CPU Read Access Violation Flag Clear
NMAVCLR.CPUWRITE	-	Non Master CPU Write Access Violation Flag Clear
NMAVCLR.CPUFETCH	-	Non Master CPU Fetch Access Violation Flag Clear
NMAVCLR.DMAWRITE	-	Non Master DMA Write Access Violation Flag Clear
NMAVCLR.CLA1READ	-	Non Master CLA1 Read Access Violation Flag Clear
NMAVCLR.CLA1WRITE	-	Non Master CLA1 Write Access Violation Flag Clear
NMAVCLR.CLA1FETCH	-	Non Master CLA1 Fetch Access Violation Flag Clear
NMAVINTEN	-	Non-Master Access Violation Interrupt Enable Register
NMAVINTEN.CPUREAD	-	Non Master CPU Read Access Violation Interrupt
NMAVINTEN.CPUWRITE	-	Non Master CPU Write Access Violation Interrupt
NMAVINTEN.CPUFETCH	-	Non Master CPU Fetch Access Violation Interrupt
NMAVINTEN.DMAWRITE	-	Non Master DMA Write Access Violation Interrupt
NMAVINTEN.CLA1READ	-	Non Master CLA1 Read Access Violation Interrupt
NMAVINTEN.CLA1WRITE	-	Non Master CLA1 Write Access Violation Interrupt
NMAVINTEN.CLA1FETCH	-	Non Master CLA1 Fetch Access Violation Interrupt
NMCPURDAVADDR	-	Non-Master CPU Read Access Violation Address
NMCPUWRAVADDR	-	Non-Master CPU Write Access Violation Address
NMCPUFAVADDR	-	Non-Master CPU Fetch Access Violation Address
NMDMAWRAVADDR	-	Non-Master DMA Write Access Violation Address
NMCLA1RDAVADDR	-	Non-Master CLA1 Read Access Violation Address
NMCLA1WRAVADDR	-	Non-Master CLA1 Write Access Violation Address
NMCLA1FAVADDR	-	Non-Master CLA1 Fetch Access Violation Address
MAVFLG.DMAWRITE	-	Master DMA Write Access Violation Flag
MAVSET.DMAWRITE	-	Master DMA Write Access Violation Flag Set
MAVCLR.DMAWRITE	-	Master DMA Write Access Violation Flag Clear
MAVINTEN.DMAWRITE	-	Master DMA Write Access Violation Interrupt Enable
MDMAWRAVADDR	-	Master DMA Write Access Violation Address
UCERRFLG.DMARDERR	-	DMA Uncorrectable Read Error Flag
UCERRFLG.CLA1RDERR	-	CLA1 Uncorrectable Read Error Flag
UCERRSET.DMARDERR	-	DMA Uncorrectable Read Error Flag Set
UCERRSET.CLA1RDERR	-	CLA1 Uncorrectable Read Error Flag Set
UCERRCLR.DMARDERR	-	DMA Uncorrectable Read Error Flag Clear
UCERRCLR.CLA1RDERR	-	CLA1 Uncorrectable Read Error Flag Clear
UCDMAREADDR	-	Uncorrectable DMA Read Error Address
UCCLA1READDR	-	Uncorrectable CLA1 Read Error Address
CERRFLG.DMARDERR	-	DMA Correctable Read Error Flag
CERRFLG.CLA1RDERR	-	CLA1 Correctable Read Error Flag
CERRSET.DMARDERR	-	DMA Correctable Read Error Flag Set
CERRSET.CLA1RDERR	-	CLA1 Correctable Read Error Flag Set
CERRCLR.DMARDERR	-	DMA Correctable Read Error Flag Clear
CERRCLR.CLA1RDERR	-	CLA1 Correctable Read Error Flag Clear
ROMWAITSTATE	-	ROM Wait State Configuration Register
ROMWAITSTATE.WSDISABLE	-	C28x ROM Wait State Enable/Disable Control
ROMPREFETCH	-	ROM Prefetch Configuration Register
ROMPREFETCH.PFENABLE	-	ROM Prefetch Enable/Disable Control
-	DXLOCK.LOCK_M0	M0 RAM Lock bits
-	DXLOCK.LOCK_M1	M1 RAM Lock bits
-	DXLOCK.LOCK_PIEVECT	PIEVECT RAM Lock bits
-	DXCOMMIT.COMMIT_M0	M0 RAM Permanent Lock bits
-	DXCOMMIT.COMMIT_M1	M1 RAM Permanent Lock bits
-	DXCOMMIT.COMMIT_PIEVECT	PIEVECT RAM Permanent Lock bits
-	DXACCPROT0.FETCHPROT_M0	Fetch Protection For M0 RAM
-	DXACCPROT0.CPUWRPROT_M0	CPU WR Protection For M0 RAM
-	DXACCPROT0.FETCHPROT_M1	Fetch Protection For M1 RAM
-	DXACCPROT0.CPUWRPROT_M1	CPU WR Protection For M1 RAM
-	DXACCPROT1	Dedicated RAM Config Register
-	DXACCPROT1.CPUWRPROT_PIEVECT	CPU WR Protection For PIEVECT RAM
-	DXTEST.TEST_PIEVECT	Selects the different modes for PIEVECT RAM
-	DXINIT.INIT_PIEVECT	RAM Initialization control for PIEVECT RAM.
-	DXINITDONE.INITDONE_PIEVECT	RAM Initialization status for PIEVECT RAM.
-	DXRAMTEST_LOCK	Lock register to Dx RAM TEST registers
-	DXRAMTEST_LOCK.M0	DxTEST.TEST_M0 LOCK
-	DXRAMTEST_LOCK.M1	DxTEST.TEST_M1 LOCK
-	DXRAMTEST_LOCK.PIEVECT	DxTEST.TEST_PIEVECT LOCK
-	DXRAMTEST_LOCK.KEY	Key for writing DxRAMTEST_LOCK
-	LSXRAMTEST_LOCK	Lock register to LSx RAM TEST registers
-	LSXRAMTEST_LOCK.LS0	LSxTEST.TEST_LS0 LOCK
-	LSXRAMTEST_LOCK.LS1	LSxTEST.TEST_LS1 LOCK
-	LSXRAMTEST_LOCK.KEY	KEY to enable write to lock
-	ROM_LOCK	ROM Config Lock Register
-	ROM_LOCK.LOCK_BOOTROM	BOOTROM Lock bits
-	ROM_LOCK.KEY	Key for writing ROM LOCK
-	ROM_TEST	ROM TEST Register
-	ROM_TEST.TEST_BOOTROM	Selects the different modes for BOOTROM
-	ROM_FORCE_ERROR	ROM Force Error register
-	ROM_FORCE_ERROR.FORCE_BOOTROM_ERROR	Force Bootrom Parity Error
-	FLUCERRSTATUS	Flash read uncorrectable ecc err status
-	FLUCERRSTATUS.UNC_ERR_L	Lower 64 bits Uncorrectable error occurred
-	FLUCERRSTATUS.DIAG_L_FAIL	Diagnostics of ECC on lower 64 bits.
-	FLUCERRSTATUS.UNC_ERR_H	Upper 64 bits Uncorrectable error occurred
-	FLUCERRSTATUS.DIAG_H_FAIL	Diagnostics of ECC on upper 64 bits.
-	FLCERRSTATUS	Flash read correctable ecc err status
-	FLCERRSTATUS.FAIL_0_L	Lower 64bits Single Bit Error Corrected
-	FLCERRSTATUS.FAIL_1_L	Lower 64bits Single Bit Error Corrected
-	FLCERRSTATUS.FAIL_0_H	Upper 64bits Single Bit Error Corrected
-	FLCERRSTATUS.FAIL_1_H	Upper 64bits Single Bit Error Corrected
-	FLCERRSTATUS.ERR_POS_L	Bit Position of Single bit Error in
-	FLCERRSTATUS.ERR_TYPE_L	Error Type in lower 64 bits
-	FLCERRSTATUS.ERR_POS_H	Bit Position of Single bit Error in
-	FLCERRSTATUS.ERR_TYPE_H	Error Type in upper 64 bits
-	CERRTHRES.CERRTHRES	Correctable error threshold.
-	CPU_RAM_TEST_ERROR_STS	Ram Test: Error Status Register
-	CPU_RAM_TEST_ERROR_STS.COR_ERROR	COR_ERROR flag
-	CPU_RAM_TEST_ERROR_STS.UNC_ERROR	UNC_ERROR flag
-	CPU_RAM_TEST_ERROR_STS.CLR_COR_ERROR	COR_ERROR flag clear bit
-	CPU_RAM_TEST_ERROR_STS.CLR_UNC_ERROR	UNC_ERROR flag clear bit
-	CPU_RAM_TEST_ERROR_STS_CLR	Ram Test: Error Status Clear Register
-	CPU_RAM_TEST_ERROR_STS_CLR.COR_ERROR	COR_ERROR flag clear bit
-	CPU_RAM_TEST_ERROR_STS_CLR.UNC_ERROR	UNC_ERROR flag clear bit
-	CPU_RAM_TEST_ERROR_ADDR	Ram Test: Error address register

    MemCfg_lockConfig

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D)   ||
	6	6		((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS)  ||
n	7		-	((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)  ||
	8	7		(memSections == MEMCFG_SECT_ALL));
	9	8
	10	9		//
	11	10		// Set the bit that blocks writes to the sections' configuration registers.
	12	11		//
	13	12		EALLOW;
	14	13
	15	14		switch(memSections & MEMCFG_SECT_TYPE_MASK)
	16	15		{
	17	16		case MEMCFG_SECT_TYPE_D:
	18	17		HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK)  |= MEMCFG_SECT_NUM_MASK &
	19	18		memSections;
	20	19		break;
	21	20
	22	21		case MEMCFG_SECT_TYPE_LS:
	23	22		HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK &
	24	23		memSections;
	25	24		break;
	26	25
n	27		-	case MEMCFG_SECT_TYPE_GS:
	28		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK &
	29		-	memSections;
	30		-	break;
	31		-
	32	26		case MEMCFG_SECT_TYPE_MASK:
	33	27		//
	34	28		// Lock configuration for all sections.
	35	29		//
	36	30		HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK)   |= MEMCFG_SECT_NUM_MASK &
	37	31		MEMCFG_SECT_DX_ALL;
	38	32		HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK)  |= MEMCFG_SECT_NUM_MASK &
	39	33		MEMCFG_SECT_LSX_ALL;
n	40		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK)  |= MEMCFG_SECT_NUM_MASK &
	41		-	MEMCFG_SECT_GSX_ALL;
	42	34		break;
	43	35
	44	36		default:
	45	37		//
	46	38		// Do nothing. Invalid memSections. Make sure you aren't OR-ing
	47	39		// values for two different types of memory sections.
	48	40		//
	49	41		break;
	50	42		}
	51	43
	52	44		EDIS;
	53	45		}
	54	46

    MemCfg_unlockConfig

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D)   ||
	6	6		((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS)  ||
n	7		-	((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)  ||
	8	7		(memSections == MEMCFG_SECT_ALL));
	9	8
	10	9		//
	11	10		// Clear the bit that blocks writes to the sections' configuration
	12	11		// registers.
	13	12		//
	14	13		EALLOW;
	15	14
	16	15		switch(memSections & MEMCFG_SECT_TYPE_MASK)
	17	16		{
	18	17		case MEMCFG_SECT_TYPE_D:
	19	18		HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK)  &= ~(MEMCFG_SECT_NUM_MASK &
	20	19		memSections);
	21	20		break;
	22	21
	23	22		case MEMCFG_SECT_TYPE_LS:
	24	23		HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK &
	25	24		memSections);
	26	25		break;
	27	26
n	28		-	case MEMCFG_SECT_TYPE_GS:
	29		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK &
	30		-	memSections);
	31		-	break;
	32		-
	33	27
	34	28		case MEMCFG_SECT_TYPE_MASK:
	35	29		//
	36	30		// Unlock configuration for all sections.
	37	31		//
	38	32		HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &=
	39	33		~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_DX_ALL));
	40	34		HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &=
	41	35		~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_LSX_ALL));
n	42		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &=
	43		-	~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_GSX_ALL));
	44	36		break;
	45	37
	46	38		default:
	47	39		//
	48	40		// Do nothing. Invalid memSections. Make sure you aren't OR-ing
	49	41		// values for two different types of memory sections.
	50	42		//
	51	43		break;
	52	44		}
	53	45
	54	46		EDIS;
	55	47		}
	56	48

    MemCfg_commitConfig

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D)   ||
	6	6		((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS)  ||
n	7		-	((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)  ||
	8	7		(memSections == MEMCFG_SECT_ALL));
	9	8
	10	9		//
	11	10		// Set the bit that permanently blocks writes to the sections'
	12	11		// configuration registers.
	13	12		//
	14	13		EALLOW;
	15	14
	16	15		switch(memSections & MEMCFG_SECT_TYPE_MASK)
	17	16		{
	18	17		case MEMCFG_SECT_TYPE_D:
	19	18		HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT)  |= MEMCFG_SECT_NUM_MASK &
	20	19		memSections;
	21	20		break;
	22	21
	23	22		case MEMCFG_SECT_TYPE_LS:
	24	23		HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
	25	24		memSections;
	26	25		break;
	27	26
n	28		-	case MEMCFG_SECT_TYPE_GS:
	29		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
	30		-	memSections;
	31		-	break;
	32		-
	33	27
	34	28		case MEMCFG_SECT_TYPE_MASK:
	35	29		//
	36	30		// Commit configuration for all sections.
	37	31		//
	38	32		HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT)   |= MEMCFG_SECT_NUM_MASK &
	39	33		MEMCFG_SECT_DX_ALL;
	40	34		HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT)  |= MEMCFG_SECT_NUM_MASK &
	41	35		MEMCFG_SECT_LSX_ALL;
n	42		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT)  |= MEMCFG_SECT_NUM_MASK &
	43		-	MEMCFG_SECT_GSX_ALL;
	44	36		break;
	45	37
	46	38		default:
	47	39		//
	48	40		// Do nothing. Invalid memSections. Make sure you aren't OR-ing
	49	41		// values for two different types of RAM.
	50	42		//
	51	43		break;
	52	44		}
	53	45
	54	46		EDIS;
	55	47		}
	56	48

    MemCfg_setProtection

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t shiftVal = 0U;
	3	3		uint32_t maskVal;
	4	4		uint32_t regVal;
	5	5		uint32_t sectionNum;
	6	6		uint32_t regOffset;
	7	7
	8	8		//
	9	9		// Check the arguments.
	10	10		//
	11	11		ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS)   ||
n	12		-	((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D)    ||
	13		-	((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS));
		12	+	((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D));
	14	13
	15	14		//
	16	15		// Calculate how far the protect mode value needs to be shifted. Each
	17	16		// section number is represented by a bit in the lower word of memSection
	18	17		// and 8 bits in the corresponding ACCPROT register.
	19	18		//
	20	19		sectionNum = memSection & MEMCFG_SECT_NUM_MASK;
	21	20
	22	21		while(sectionNum != 1U)
	23	22		{
	24	23		sectionNum = sectionNum >> 1U;
	25	24		shiftVal += 8U;
	26	25		}
	27	26
	28	27		//
	29	28		// Calculate register offset. Also, make sure the shift value is no greater
	30	29		// than 31.
	31	30		//
	32	31		regOffset = (shiftVal & ~(0x1FU)) >> 4U;
	33	32		shiftVal &= 0x0001FU;
	34	33		maskVal = (uint32_t)MEMCFG_XACCPROTX_M << shiftVal;
	35	34		regVal = protectMode << shiftVal;
	36	35
	37	36		//
	38	37		// Write the access protection mode into the appropriate field
	39	38		//
	40	39		EALLOW;
	41	40
	42	41		switch(memSection & MEMCFG_SECT_TYPE_MASK)
	43	42		{
	44	43		case MEMCFG_SECT_TYPE_D:
	45	44		HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) &= ~maskVal;
	46	45		HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) |= regVal;
	47	46		break;
	48	47
	49	48		case MEMCFG_SECT_TYPE_LS:
	50	49		HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) &= ~maskVal;
	51	50		HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) |= regVal;
	52	51		break;
	53	52
n	54		-	case MEMCFG_SECT_TYPE_GS:
	55		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) &= ~maskVal;
	56		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) |= regVal;
	57		-	break;
	58		-
	59	53
	60	54		default:
	61	55		//
	62	56		// Do nothing. Invalid memSection.
	63	57		//
	64	58		break;
	65	59		}
	66	60
	67	61		EDIS;
	68	62		}
	69	63

    MemCfg_setLSRAMControllerSel

    MemCfg_setGSRAMControllerSel

    MemCfg_setTestMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t shiftVal = 0U;
	3	3		uint32_t maskVal;
	4	4		uint32_t regVal;
	5	5		uint32_t sectionNum;
	6	6
	7	7		//
	8	8		// Check the arguments.
	9	9		//
	10	10		ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D)    ||
	11	11		((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS)   ||
n	12		-	((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)   ||
	13		-	((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG));
		12	+	((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_ROM));
	14	13
	15	14		//
	16	15		// Calculate how far the protect mode value needs to be shifted. Each
	17	16		// section number is represented by a bit in the lower word of memSection
	18	17		// and 2 bits in the corresponding TEST register.
	19	18		//
	20	19		sectionNum = memSection & MEMCFG_SECT_NUM_MASK;
	21	20
	22	21		while(sectionNum != 1U)
	23	22		{
	24	23		sectionNum = sectionNum >> 1U;
	25	24		shiftVal += 2U;
	26	25		}
	27	26
	28	27		maskVal = (uint32_t)MEMCFG_XTEST_M << shiftVal;
	29	28		regVal = (uint32_t)testMode << shiftVal;
	30	29
	31	30		//
	32	31		// Write the test mode into the appropriate field
	33	32		//
	34	33		EALLOW;
	35	34
	36	35		switch(memSection & MEMCFG_SECT_TYPE_MASK)
	37	36		{
	38	37		case MEMCFG_SECT_TYPE_D:
	39	38		HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) &= ~maskVal;
	40	39		HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) |= regVal;
	41	40		break;
	42	41
	43	42		case MEMCFG_SECT_TYPE_LS:
	44	43		HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) &= ~maskVal;
	45	44		HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) |= regVal;
	46	45		break;
	47	46
n	48		-	case MEMCFG_SECT_TYPE_GS:
	49		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) &= ~maskVal;
	50		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) |= regVal;
	51		-	break;
	52		-
	53		-	case MEMCFG_SECT_TYPE_MSG:
		47	+	case MEMCFG_SECT_TYPE_ROM:
	54		-	HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) &= ~maskVal;
		48	+	HWREG(MEMCFG_BASE + MEMCFG_O_ROM_TEST) &= ~maskVal;
	55		-	HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) |= regVal;
		49	+	HWREG(MEMCFG_BASE + MEMCFG_O_ROM_TEST) |= regVal;
	56	50		break;
	57	51
	58	52		default:
	59	53		//
	60	54		// Do nothing. Invalid memSection.
	61	55		//
	62	56		break;
	63	57		}
	64	58
	65	59		EDIS;
	66	60		}
	67	61

    MemCfg_initSections

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		//
	5	5		ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D)   ||
	6	6		((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS)  ||
n	7		-	((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)  ||
	8		-	((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) ||
	9	7		(ramSections == MEMCFG_SECT_ALL));
	10	8
	11	9		//
	12	10		// Set the bit in the various initialization registers that starts
	13	11		// initialization.
	14	12		//
	15	13		EALLOW;
	16	14
	17	15		switch(ramSections & MEMCFG_SECT_TYPE_MASK)
	18	16		{
	19	17		case MEMCFG_SECT_TYPE_D:
	20	18		HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT)   |= MEMCFG_SECT_NUM_MASK &
	21	19		ramSections;
	22	20		break;
	23	21
	24	22		case MEMCFG_SECT_TYPE_LS:
	25	23		HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT)  |= MEMCFG_SECT_NUM_MASK &
	26	24		ramSections;
	27	25		break;
	28	26
n	29		-	case MEMCFG_SECT_TYPE_GS:
	30		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT)  |= MEMCFG_SECT_NUM_MASK &
	31		-	ramSections;
	32		-	break;
	33		-
	34		-	case MEMCFG_SECT_TYPE_MSG:
	35		-	HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK &
	36		-	ramSections;
	37		-	break;
	38	27
	39	28		case MEMCFG_SECT_TYPE_MASK:
	40	29		//
	41	30		// Initialize all sections.
	42	31		//
	43	32		HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT)   |= MEMCFG_SECT_NUM_MASK &
	44	33		MEMCFG_SECT_DX_ALL;
	45	34		HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT)  |= MEMCFG_SECT_NUM_MASK &
	46	35		MEMCFG_SECT_LSX_ALL;
n	47		-	HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT)  |= MEMCFG_SECT_NUM_MASK &
	48		-	MEMCFG_SECT_GSX_ALL;
	49		-	HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK &
	50		-	MEMCFG_SECT_MSGX_ALL;
	51	36		break;
	52	37
	53	38		default:
	54	39		//
	55	40		// Do nothing. Invalid ramSections. Make sure you aren't OR-ing
	56	41		// values for two different types of RAM.
	57	42		//
	58	43		break;
	59	44		}
	60	45
	61	46		EDIS;
	62	47		}
	63	48

    MemCfg_getInitStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t status;
	3	3
	4	4		//
	5	5		// Check the arguments.
	6	6		//
	7	7		ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D)   ||
	8	8		((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS)  ||
n	9		-	((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)  ||
	10		-	((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) ||
	11	9		(ramSections == MEMCFG_SECT_ALL));
	12	10
	13	11		//
	14	12		// Read registers containing the initialization complete status.
	15	13		//
	16	14		switch(ramSections & MEMCFG_SECT_TYPE_MASK)
	17	15		{
	18	16		case MEMCFG_SECT_TYPE_D:
	19	17		status = HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE);
	20	18		break;
	21	19
	22	20		case MEMCFG_SECT_TYPE_LS:
	23	21		status = HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE);
	24	22		break;
	25	23
n	26		-	case MEMCFG_SECT_TYPE_GS:
	27		-	status = HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE);
	28		-	break;
	29		-
	30		-	case MEMCFG_SECT_TYPE_MSG:
	31		-	status = HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE);
	32		-	break;
	33	24
	34	25		case MEMCFG_SECT_TYPE_MASK:
	35	26		//
	36	27		// Return the overall status.
	37	28		//
	38	29		if((HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE) ==
	39	30		MEMCFG_SECT_DX_ALL) &&
	40	31		(HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE) ==
n	41		-	MEMCFG_SECT_LSX_ALL) &&
	42		-	(HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE) ==
	43		-	MEMCFG_SECT_GSX_ALL) &&
	44		-	(HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE) ==
	45		-	MEMCFG_SECT_MSGX_ALL))
		32	+	MEMCFG_SECT_LSX_ALL))
	46	33		{
	47	34		status = MEMCFG_SECT_NUM_MASK;
	48	35		}
	49	36		else
	50	37		{
	51	38		status = 0U;
	52	39		}
	53	40		break;
	54	41
	55	42		default:
	56	43		//
	57	44		// Invalid ramSections. Make sure you aren't OR-ing values for two
	58	45		// different types of RAM.
	59	46		//
	60	47		status = 0U;
	61	48		break;
	62	49		}
	63	50
	64	51		return((ramSections & status) == (ramSections & MEMCFG_SECT_NUM_MASK));
	65	52		}
	66	53

    MemCfg_getViolationAddress

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	uint32_t address;
		2	+	uint32_t address = 0;
	3		-	uint32_t stsNumber;
	4	3
n	5		-	//
		4	+	if(intFlag == MEMCFG_MVIOL_CPUFETCH)
	6		-	// Calculate the the address of the desired violation address register.
	7		-	//
	8		-	if((intFlag & MEMCFG_MVIOL_MASK) != 0U)
	9	5		{
n	10		-	stsNumber = intFlag >> MEMCFG_MVIOL_SHIFT;
	11		-	address = ACCESSPROTECTION_BASE + MEMCFG_O_MCPUFAVADDR;
		6	+	address = HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MCPUFAVADDR);
		7	+	}
		8	+	else if(intFlag == MEMCFG_MVIOL_CPUWRITE)
		9	+	{
		10	+	address = HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MCPUWRAVADDR);
	12	11		}
	13	12		else
	14	13		{
n	15		-	stsNumber = intFlag;
		14	+	ASSERT((bool)false);
	16		-	address = ACCESSPROTECTION_BASE + MEMCFG_O_NMCPURDAVADDR;
	17	15		}
n	18		-
	19		-	while(stsNumber > 1U)
	20		-	{
	21		-	stsNumber = stsNumber >> 1U;
	22		-	address += (uint32_t)(MEMCFG_O_NMCPUWRAVADDR - MEMCFG_O_NMCPURDAVADDR);
	23		-	}
	24		-
	25		-	//
	26		-	// Read and return the access violation address at the calculated location.
	27		-	//
	28		-	return(HWREG(address));
		16	+	return(address);
	29	17		}
	30	18

    MemCfg_getUncorrErrorAddress

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	uint32_t address;
	3		-	uint32_t temp;
	4		-
	5	2		//
n	6		-	// Calculate the the address of the desired error address register.
		3	+	// Check the arguments.
	7	4		//
n	8		-	address = MEMORYERROR_BASE + MEMCFG_O_UCCPUREADDR;
		5	+	if(stsFlag != MEMCFG_UCERR_CPUREAD)
	9		-
	10		-	temp = stsFlag;
	11		-
	12		-	while(temp > 1U)
	13	6		{
n	14		-	temp = temp >> 1U;
		7	+	//
	15		-	address += (uint32_t)(MEMCFG_O_UCDMAREADDR - MEMCFG_O_UCCPUREADDR);
		8	+	// Currently, the only correctable error address that can be read
		9	+	// from a register is one for a CPU read error (MEMCFG_UCERR_CPUREAD).
		10	+	// For the sake of keeping this function portable to possible future
		11	+	// devices with other error types, it still takes a stsFlag parameter.
		12	+	//
		13	+	ASSERT((bool)false);
	16	14		}
	17	15
	18	16		//
n	19		-	// Read and return the error address at the calculated location.
		17	+	// Read and return the error address.
	20	18		//
n	21		-	return(HWREG(address));
		19	+	return(HWREG(MEMORYERROR_BASE + MEMCFG_O_UCCPUREADDR));
	22	20		}
	23	21

    MemCfg_setCLAMemType

    MemCfg_enableViolationInterrupt

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Enable the specified interrupts.
	4	4		//
	5	5		EALLOW;
n	6		-
	7		-	HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) |=
	8		-	intFlags & MEMCFG_NMVIOL_MASK;
	9	6
	10	7		HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) |=
	11	8		(intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT;
	12	9
	13	10		EDIS;
	14	11		}
	15	12

    MemCfg_disableViolationInterrupt

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Disable the specified interrupts.
	4	4		//
	5	5		EALLOW;
n	6		-
	7		-	HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) &=
	8		-	~(intFlags & MEMCFG_NMVIOL_MASK);
	9	6
	10	7		HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) &=
	11	8		~((intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT);
	12	9
	13	10		EDIS;
	14	11		}
	15	12

    MemCfg_getViolationInterruptStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t status;
	3	3
	4	4		//
	5	5		// Read and return RAM access status flags.
	6	6		//
n	7		-	status = (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVFLG)) |
		7	+	status = HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVFLG) <<
	8		-	(HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVFLG) <<
	9		-	MEMCFG_MVIOL_SHIFT);
		8	+	MEMCFG_MVIOL_SHIFT;
	10	9
	11	10		return(status);
	12	11		}
	13	12

    MemCfg_forceViolationInterrupt

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Shift and mask the flags appropriately and write them to the
	4	4		// corresponding SET register.
	5	5		//
	6	6		EALLOW;
	7	7
n	8		-	HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVSET) =
	9		-	intFlags & MEMCFG_NMVIOL_MASK;
	10		-
	11	8		HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVSET) =
	12	9		(intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT;
	13	10
	14	11		EDIS;
	15	12		}
	16	13

    MemCfg_clearViolationInterruptStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Clear the requested access violation flags.
	4	4		//
	5	5		EALLOW;
n	6		-
	7		-	HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVCLR) |=
	8		-	intFlags & MEMCFG_NMVIOL_MASK;
	9	6
	10	7		HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVCLR) |=
	11	8		(intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT;
	12	9
	13	10		EDIS;
	14	11		}
	15	12

    MemCfg_enableROMWaitState

    MemCfg_disableROMWaitState

    MemCfg_enableROMPrefetch

    MemCfg_disableROMPrefetch

    MemCfg_lockTestConfig

    MemCfg_unlockTestConfig

    MemCfg_forceMemError

    MemCfg_getDiagErrorStatus

    MemCfg_clearDiagErrorStatus

    MemCfg_getDiagErrorAddress

nmi

outputxbar

pie

pin_map_legacy

reg_inclusive_terminology

sci

    SCI_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		return(
	3	3		(base == SCIA_BASE) ||
	4	4		(base == SCIB_BASE) ||
n	5		-	(base == SCIC_BASE) ||
	6		-	(base == SCID_BASE)
		5	+	(base == SCIC_BASE)
	7	6		);
	8	7		}
	9	8

sdfm

spi

    SPI_isBaseValid

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		return(
n	3		-	(base == SPIA_BASE) ||
	4		-	(base == SPIB_BASE) ||
	5		-	(base == SPIC_BASE)
		3	+	(base == SPIA_BASE)
	6	4		);
	7	5		}
	8	6

sysctl

    Enumeration Differences

Type	f2837xd	f280013x	Description
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM8SOCA	-	ePWM8 SOCA for ADCSOCAO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM9SOCA	-	ePWM9 SOCA for ADCSOCAO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM10SOCA	-	ePWM10 SOCA for ADCSOCAO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM11SOCA	-	ePWM11 SOCA for ADCSOCAO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM12SOCA	-	ePWM12 SOCA for ADCSOCAO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM8SOCB	-	ePWM8 SOCB for ADCSOCBO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM9SOCB	-	ePWM9 SOCB for ADCSOCBO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM10SOCB	-	ePWM10 SOCB for ADCSOCBO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM11SOCB	-	ePWM11 SOCB for ADCSOCBO
SYSCTL_ADCSOC_SRC	SYSCTL_ADCSOC_SRC_PWM12SOCB	-	ePWM12 SOCB for ADCSOCBO
SYSCTL_AUXPLL	SYSCTL_AUXPLL_DIV_1	-	Auxiliary PLL divide by 1
SYSCTL_AUXPLL	SYSCTL_AUXPLL_DIV_2	-	Auxiliary PLL divide by 2
SYSCTL_AUXPLL	SYSCTL_AUXPLL_DIV_4	-	Auxiliary PLL divide by 4
SYSCTL_AUXPLL	SYSCTL_AUXPLL_DIV_8	-	Auxiliary PLL divide by 8
SYSCTL_AUXPLL	SYSCTL_AUXPLL_IMULT(x)	-	Macro to format integer multiplier value. x is a number from 1 to 127.
SYSCTL_AUXPLL	SYSCTL_AUXPLL_FMULT_NONE	-	No fractional multiplier
SYSCTL_AUXPLL	SYSCTL_AUXPLL_FMULT_0	-	No fractional multiplier
SYSCTL_AUXPLL	SYSCTL_AUXPLL_FMULT_1_4	-	Fractional multiplier - 0.25
SYSCTL_AUXPLL	SYSCTL_AUXPLL_FMULT_1_2	-	Fractional multiplier - 0.50
SYSCTL_AUXPLL	SYSCTL_AUXPLL_FMULT_3_4	-	Fractional multiplier - 0.75
SYSCTL_AUXPLL	SYSCTL_AUXPLL_OSCSRC_OSC2	-	Internal oscillator INTOSC2 as auxiliary clock input
SYSCTL_AUXPLL	SYSCTL_AUXPLL_OSCSRC_XTAL	-	External oscillator (XTAL) as auxiliary clock input
SYSCTL_AUXPLL	SYSCTL_AUXPLL_OSCSRC_AUXCLKIN	-	AUXCLKIN (from GPIO) as auxiliary clock input
SYSCTL_AUXPLL	SYSCTL_AUXPLL_ENABLE	-	Enable AUXPLL
SYSCTL_AUXPLL	SYSCTL_AUXPLL_DISABLE	-	Disable AUXPLL
SYSCTL_CAUSE	-	SYSCTL_CAUSE_SIMRESET_CPU1RSN	SIMRESET_CPU1RSn
SYSCTL_CAUSE	-	SYSCTL_CAUSE_SIMRESET_XRSN	SIMRESET_XRSn
SYSCTL_NMI	SYSCTL_NMI_RAMUNCERR	-	RAM Uncorrectable Error NMI Flag
SYSCTL_NMI	SYSCTL_NMI_FLUNCERR	-	Flash Uncorrectable Error NMI Flag
SYSCTL_NMI	SYSCTL_NMI_CPU1HWBISTERR	-	HW BIST Error NMI Flag
SYSCTL_NMI	SYSCTL_NMI_CPU2HWBISTERR	-	HW BIST Error NMI Flag
SYSCTL_NMI	SYSCTL_NMI_PIEVECTERR	-	PIE Vector Fetch Error Flag
SYSCTL_NMI	SYSCTL_NMI_CLBNMI	-	Configurable Logic Block NMI Flag
SYSCTL_NMI	SYSCTL_NMI_CPU2WDRSN	-	CPU2 WDRSn Reset Indication Flag
SYSCTL_NMI	SYSCTL_NMI_CPU2NMIWDRSN	-	CPU2 NMIWDRSn Reset Indication Flag
SYSCTL_NMI	-	SYSCTL_NMI_UNCERR	Flash/RAM/ROM Uncorrectable Error NMI Flag
SYSCTL_NMI	-	SYSCTL_NMI_SWERR	SW Error Force NMI Flag
SYSCTL_SEC_CONTROLLER	SYSCTL_SEC_CONTROLLER_CLA	-	Configure CLA as the secondary controller
SYSCTL_SEC_CONTROLLER	SYSCTL_SEC_CONTROLLER_DMA	-	Configure DMA a secondary controller
SysCtl_AuxPLLClkDivider	SYSCTL_AUXPLLCLK_DIV_1	-	AUXPLL clock = AUXPLL clock / 1
SysCtl_AuxPLLClkDivider	SYSCTL_AUXPLLCLK_DIV_2	-	AUXPLL clock = AUXPLL clock / 2
SysCtl_AuxPLLClkDivider	SYSCTL_AUXPLLCLK_DIV_4	-	AUXPLL clock = AUXPLL clock / 4
SysCtl_AuxPLLClkDivider	SYSCTL_AUXPLLCLK_DIV_8	-	AUXPLL clock = AUXPLL clock / 8
SysCtl_AuxPLLClkDivider	SYSCTL_AUXPLLCLK_DIV_3	-	AUXPLL clock = AUXPLL clock / 3
SysCtl_AuxPLLClkDivider	SYSCTL_AUXPLLCLK_DIV_5	-	AUXPLL clock = AUXPLL clock / 5
SysCtl_AuxPLLClkDivider	SYSCTL_AUXPLLCLK_DIV_6	-	AUXPLL clock = AUXPLL clock / 6
SysCtl_AuxPLLClkDivider	SYSCTL_AUXPLLCLK_DIV_7	-	AUXPLL clock = AUXPLL clock / 7
SysCtl_CPUSel	SYSCTL_CPUSEL_CPU1	-	Connect the peripheral (indicated by SysCtl_CPUSelPeripheral) to CPU1
SysCtl_CPUSel	SYSCTL_CPUSEL_CPU2	-	Connect the peripheral (indicated by SysCtl_CPUSelPeripheral) to CPU2
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM1	-	CPUSEL EPWM1
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM2	-	CPUSEL EPWM2
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM3	-	CPUSEL EPWM3
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM4	-	CPUSEL EPWM4
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM5	-	CPUSEL EPWM5
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM6	-	CPUSEL EPWM6
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM7	-	CPUSEL EPWM7
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM8	-	CPUSEL EPWM8
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM9	-	CPUSEL EPWM9
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM10	-	CPUSEL EPWM10
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM11	-	CPUSEL EPWM11
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EPWM12	-	CPUSEL EPWM12
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ECAP1	-	CPUSEL ECAP1
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ECAP2	-	CPUSEL ECAP2
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ECAP3	-	CPUSEL ECAP3
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ECAP4	-	CPUSEL ECAP4
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ECAP5	-	CPUSEL ECAP5
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ECAP6	-	CPUSEL ECAP6
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EQEP1	-	CPUSEL EQEP1
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EQEP2	-	CPUSEL EQEP2
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_EQEP3	-	CPUSEL EQEP3
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SD1	-	CPUSEL SD1
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SD2	-	CPUSEL SD2
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SCIA	-	CPUSEL SCIA
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SCIB	-	CPUSEL SCIB
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SCIC	-	CPUSEL SCIC
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SCID	-	CPUSEL SCID
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SPIA	-	CPUSEL SPIA
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SPIB	-	CPUSEL SPIB
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_SPIC	-	CPUSEL SPIC
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_I2CA	-	CPUSEL I2CA
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_I2CB	-	CPUSEL I2CB
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CANA	-	CPUSEL CANA
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CANB	-	CPUSEL CANB
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_MCBSPA	-	CPUSEL MCBSPA
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_MCBSPB	-	CPUSEL MCBSPB
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ADCA	-	CPUSEL ADCA
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ADCB	-	CPUSEL ADCB
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ADCC	-	CPUSEL ADCC
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_ADCD	-	CPUSEL ADCD
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CMPSS1	-	CPUSEL CMPSS1
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CMPSS2	-	CPUSEL CMPSS2
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CMPSS3	-	CPUSEL CMPSS3
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CMPSS4	-	CPUSEL CMPSS4
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CMPSS5	-	CPUSEL CMPSS5
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CMPSS6	-	CPUSEL CMPSS6
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CMPSS7	-	CPUSEL CMPSS7
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_CMPSS8	-	CPUSEL CMPSS8
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_DACA	-	CPUSEL DACA
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_DACB	-	CPUSEL DACB
SysCtl_CPUSelPeriphInstance	SYSCTL_CPUSEL_DACC	-	CPUSEL DACC
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL0_EPWM	-	Configure CPU Select for EPWM
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL1_ECAP	-	Configure CPU Select for ECAP
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL2_EQEP	-	Configure CPU Select for EQEP
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL4_SD	-	Configure CPU Select for SD
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL5_SCI	-	Configure CPU Select for SCI
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL6_SPI	-	Configure CPU Select for SPI
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL7_I2C	-	Configure CPU Select for I2C
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL8_CAN	-	Configure CPU Select for CAN
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL9_MCBSP	-	Configure CPU Select for MCBSP
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL11_ADC	-	Configure CPU Select for ADC
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL12_CMPSS	-	Configure CPU Select for CMPSS
SysCtl_CPUSelPeripheral	SYSCTL_CPUSEL14_DAC	-	Configure CPU Select for DAC
SysCtl_DeviceParametric	SYSCTL_DEVICE_FLASH	-	Device Flash size (KB)
SysCtl_DeviceParametric	SYSCTL_DEVICE_PARTID	-	Device Part ID Format Revision
SysCtl_EMIF1CLKDivider	SYSCTL_EMIF1CLK_DIV_1	-	EMIF1CLK = PLLSYSCLK / 1
SysCtl_EMIF1CLKDivider	SYSCTL_EMIF1CLK_DIV_2	-	EMIF1CLK = PLLSYSCLK / 2
SysCtl_EMIF2CLKDivider	SYSCTL_EMIF2CLK_DIV_1	-	EMIF2CLK = PLLSYSCLK / 1
SysCtl_EMIF2CLKDivider	SYSCTL_EMIF2CLK_DIV_2	-	EMIF2CLK = PLLSYSCLK / 2
SysCtl_EPWMCLKDivider	SYSCTL_EPWMCLK_DIV_1	-	EPWMCLK = PLLSYSCLK / 1
SysCtl_EPWMCLKDivider	SYSCTL_EPWMCLK_DIV_2	-	EPWMCLK = PLLSYSCLK / 2
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_CLA1	-	CLA1 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_DMA	-	DMA clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_HRPWM	-	HRPWM clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_GTBCLKSYNC	-	GTBCLKSYNC clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EMIF1	-	EMIF1 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EMIF2	-	EMIF2 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EPWM8	-	EPWM8 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EPWM9	-	EPWM9 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EPWM10	-	EPWM10 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EPWM11	-	EPWM11 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EPWM12	-	EPWM12 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_ECAP3	-	ECAP3 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_ECAP4	-	ECAP4 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_ECAP5	-	ECAP5 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_ECAP6	-	ECAP6 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EQEP2	-	EQEP2 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_EQEP3	-	EQEP3 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_SD1	-	SD1 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_SD2	-	SD2 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_SCID	-	SCI_D clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_SPIB	-	SPI_B clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_SPIC	-	SPI_C clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_CANB	-	CAN_B clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_MCBSPA	-	MCBSP_A clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_MCBSPB	-	MCBSP_B clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_USBA	-	USB_A clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_UPPA	-	UPP_A clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_ADCB	-	ADC_B clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_ADCD	-	ADC_D clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_CMPSS5	-	CMPSS5 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_CMPSS6	-	CMPSS6 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_CMPSS7	-	CMPSS7 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_CMPSS8	-	CMPSS8 clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_DACA	-	DAC_A clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_DACB	-	DAC_B clock
SysCtl_PeripheralPCLOCKCR	SYSCTL_PERIPH_CLK_DACC	-	DAC_C clock
SysCtl_PeripheralPCLOCKCR	-	SYSCTL_PERIPH_CLK_HRCAL	HRCAL clock
SysCtl_PeripheralPCLOCKCR	-	SYSCTL_PERIPH_CLK_DCC0	DCC0 clock
SysCtl_PeripheralPCLOCKCR	-	SYSCTL_PERIPH_CLK_EPG1	EPG1 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_CPU1CLA1	-	Reset CPU1_CLA1 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_CPU2CLA1	-	Reset CPU2_CLA1 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EMIF1	-	Reset EMIF1 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EMIF2	-	Reset EMIF2 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EPWM8	-	Reset EPWM8 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EPWM9	-	Reset EPWM9 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EPWM10	-	Reset EPWM10 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EPWM11	-	Reset EPWM11 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EPWM12	-	Reset EPWM12 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_ECAP3	-	Reset ECAP3 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_ECAP4	-	Reset ECAP4 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_ECAP5	-	Reset ECAP5 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_ECAP6	-	Reset ECAP6 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EQEP2	-	Reset EQEP2 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_EQEP3	-	Reset EQEP3 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_SD1	-	Reset SD1 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_SD2	-	Reset SD2 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_SCID	-	Reset SCI_D clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_SPIB	-	Reset SPI_B clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_SPIC	-	Reset SPI_C clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_MCBSPA	-	Reset MCBSP_A clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_MCBSPB	-	Reset MCBSP_B clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_USBA	-	Reset USB_A clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_ADCB	-	Reset ADC_B clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_ADCD	-	Reset ADC_D clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_CMPSS5	-	Reset CMPSS5 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_CMPSS6	-	Reset CMPSS6 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_CMPSS7	-	Reset CMPSS7 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_CMPSS8	-	Reset CMPSS8 clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_DACA	-	Reset DAC_A clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_DACB	-	Reset DAC_B clock
SysCtl_PeripheralSOFTPRES	SYSCTL_PERIPH_RES_DACC	-	Reset DAC_C clock
SysCtl_PeripheralSOFTPRES	-	SYSCTL_PERIPH_RES_CANA	Reset CAN_A clock
SysCtl_PeripheralSOFTPRES	-	SYSCTL_PERIPH_RES_DCC0	Reset DCC0 clock
SysCtl_PeripheralSOFTPRES	-	SYSCTL_PERIPH_RES_EPG1	Reset EPG1 clock
SysCtl_PeripheralSOFTPRES	-	SYSCTL_PERIPH_RES_FLASHA	Reset FLASHA clock
SysCtl_SyncInput	SYSCTL_SYNC_IN_EPWM4	-	Sync input to EPWM4
SysCtl_SyncInput	SYSCTL_SYNC_IN_EPWM7	-	Sync input to EPWM7
SysCtl_SyncInput	SYSCTL_SYNC_IN_EPWM10	-	Sync input to EPWM10
SysCtl_SyncInput	SYSCTL_SYNC_IN_ECAP1	-	Sync input to ECAP1
SysCtl_SyncInput	SYSCTL_SYNC_IN_ECAP4	-	Sync input to ECAP4
SysCtl_SyncInputSource	SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT	-	EPWM1SYNCOUT
SysCtl_SyncInputSource	SYSCTL_SYNC_IN_SRC_EPWM4SYNCOUT	-	EPWM4SYNCOUT
SysCtl_SyncInputSource	SYSCTL_SYNC_IN_SRC_EPWM7SYNCOUT	-	EPWM7SYNCOUT
SysCtl_SyncInputSource	SYSCTL_SYNC_IN_SRC_EPWM10SYNCOUT	-	EPWM10SYNCOUT
SysCtl_SyncInputSource	SYSCTL_SYNC_IN_SRC_ECAP1SYNCOUT	-	ECAP1SYNCOUT
SysCtl_SyncInputSource	SYSCTL_SYNC_IN_SRC_EXTSYNCIN1	-	EXTSYNCIN1--Valid for all values of syncInput
SysCtl_SyncInputSource	SYSCTL_SYNC_IN_SRC_EXTSYNCIN2	-	EXTSYNCIN2--Valid for all values of syncInput
SysCtl_SyncOutputSource	SYSCTL_SYNC_OUT_SRC_EPWM10SYNCOUT	-	EPWM10SYNCOUT --> EXTSYNCOUT
SysCtl_SyncOutputSource	-	SYSCTL_SYNC_OUT_SRC_EPWM2SYNCOUT	EPWM2SYNCOUT --> EXTSYNCOUT
SysCtl_SyncOutputSource	-	SYSCTL_SYNC_OUT_SRC_EPWM3SYNCOUT	EPWM3SYNCOUT --> EXTSYNCOUT
SysCtl_SyncOutputSource	-	SYSCTL_SYNC_OUT_SRC_EPWM5SYNCOUT	EPWM5SYNCOUT --> EXTSYNCOUT
SysCtl_SyncOutputSource	-	SYSCTL_SYNC_OUT_SRC_EPWM6SYNCOUT	EPWM6SYNCOUT --> EXTSYNCOUT
SysCtl_SyncOutputSource	-	SYSCTL_SYNC_OUT_SRC_ECAP1SYNCOUT	ECAP1SYNCOUT --> EXTSYNCOUT
SysCtl_SyncOutputSource	-	SYSCTL_SYNC_OUT_SRC_ECAP2SYNCOUT	ECAP2SYNCOUT --> EXTSYNCOUT
SysCtl_SyncOutputSource	-	SYSCTL_SYNC_OUT_SRC_ECAP3SYNCOUT	ECAP3SYNCOUT --> EXTSYNCOUT

    Register Differences

f2837xd	f280013x	Description
DEVCFGLOCK1	-	Lock bit for CPUSELx registers
DEVCFGLOCK1.CPUSEL0	-	Lock bit for CPUSEL0 register
DEVCFGLOCK1.CPUSEL1	-	Lock bit for CPUSEL1 register
DEVCFGLOCK1.CPUSEL2	-	Lock bit for CPUSEL2 register
DEVCFGLOCK1.CPUSEL3	-	Lock bit for CPUSEL3 register
DEVCFGLOCK1.CPUSEL4	-	Lock bit for CPUSEL4 register
DEVCFGLOCK1.CPUSEL5	-	Lock bit for CPUSEL5 register
DEVCFGLOCK1.CPUSEL6	-	Lock bit for CPUSEL6 register
DEVCFGLOCK1.CPUSEL7	-	Lock bit for CPUSEL7 register
DEVCFGLOCK1.CPUSEL8	-	Lock bit for CPUSEL8 register
DEVCFGLOCK1.CPUSEL9	-	Lock bit for CPUSEL9 register
DEVCFGLOCK1.CPUSEL10	-	Lock bit for CPUSEL10 register
DEVCFGLOCK1.CPUSEL11	-	Lock bit for CPUSEL11 register
DEVCFGLOCK1.CPUSEL12	-	Lock bit for CPUSEL12 register
DEVCFGLOCK1.CPUSEL13	-	Lock bit for CPUSEL13 register
DEVCFGLOCK1.CPUSEL14	-	Lock bit for CPUSEL14 register
PARTIDL.FLASH_SIZE	-	Flash size in KB
PARTIDL.PARTID_FORMAT_REVISION	-	Revision of the PARTID format
DC0	-	Device Capability: Device Information
DC0.SINGLE_CORE	-	Single Core vs Dual Core
DC1	-	Device Capability: Processing Block Customization
DC1.CPU1_FPU_TMU	-	CPU1's FPU1+TMU1
DC1.CPU2_FPU_TMU	-	CPU2's FPU2+TMU2
DC1.CPU1_VCU	-	CPU1's VCU
DC1.CPU2_VCU	-	CPU2's VCU
DC1.CPU1_CLA1	-	CPU1.CLA1
DC1.CPU2_CLA1	-	CPU2.CLA1
DC2	-	Device Capability: EMIF Customization
DC2.EMIF1	-	EMIF1
DC2.EMIF2	-	EMIF2
DC3	-	Device Capability: Peripheral Customization
DC3.EPWM1	-	EPWM1
DC3.EPWM2	-	EPWM2
DC3.EPWM3	-	EPWM3
DC3.EPWM4	-	EPWM4
DC3.EPWM5	-	EPWM5
DC3.EPWM6	-	EPWM6
DC3.EPWM7	-	EPWM7
DC3.EPWM8	-	EPWM8
DC3.EPWM9	-	EPWM9
DC3.EPWM10	-	EPWM10
DC3.EPWM11	-	EPWM11
DC3.EPWM12	-	EPWM12
DC4	-	Device Capability: Peripheral Customization
DC4.ECAP1	-	ECAP1
DC4.ECAP2	-	ECAP2
DC4.ECAP3	-	ECAP3
DC4.ECAP4	-	ECAP4
DC4.ECAP5	-	ECAP5
DC4.ECAP6	-	ECAP6
DC5	-	Device Capability: Peripheral Customization
DC5.EQEP1	-	EQEP1
DC5.EQEP2	-	EQEP2
DC5.EQEP3	-	EQEP3
DC6	-	Device Capability: Peripheral Customization
DC6.CLB1	-	CLB1
DC6.CLB2	-	CLB2
DC6.CLB3	-	CLB3
DC6.CLB4	-	CLB4
DC7	-	Device Capability: Peripheral Customization
DC7.SD1	-	SD1
DC7.SD2	-	SD2
DC8	-	Device Capability: Peripheral Customization
DC8.SCI_A	-	SCI_A
DC8.SCI_B	-	SCI_B
DC8.SCI_C	-	SCI_C
DC8.SCI_D	-	SCI_D
DC9	-	Device Capability: Peripheral Customization
DC9.SPI_A	-	SPI_A
DC9.SPI_B	-	SPI_B
DC9.SPI_C	-	SPI_C
DC10	-	Device Capability: Peripheral Customization
DC10.I2C_A	-	I2C_A
DC10.I2C_B	-	I2C_B
DC11	-	Device Capability: Peripheral Customization
DC11.CAN_A	-	CAN_A
DC11.CAN_B	-	CAN_B
DC12	-	Device Capability: Peripheral Customization
DC12.MCBSP_A	-	McBSP_A
DC12.MCBSP_B	-	McBSP_B
DC12.USB_A	-	Decides the capability of the USB_A Module
DC13	-	Device Capability: Peripheral Customization
DC13.UPP_A	-	uPP_A
DC14	-	Device Capability: Analog Modules Customization
DC14.ADC_A	-	ADC_A
DC14.ADC_B	-	ADC_B
DC14.ADC_C	-	ADC_C
DC14.ADC_D	-	ADC_D
DC15	-	Device Capability: Analog Modules Customization
DC15.CMPSS1	-	CMPSS1
DC15.CMPSS2	-	CMPSS2
DC15.CMPSS3	-	CMPSS3
DC15.CMPSS4	-	CMPSS4
DC15.CMPSS5	-	CMPSS5
DC15.CMPSS6	-	CMPSS6
DC15.CMPSS7	-	CMPSS7
DC15.CMPSS8	-	CMPSS8
DC17	-	Device Capability: Analog Modules Customization
DC17.DAC_A	-	Buffered-DAC_A
DC17.DAC_B	-	Buffered-DAC_B
DC17.DAC_C	-	Buffered-DAC_C
DC18	-	Device Capability: CPU1 Lx SRAM Customization
DC18.LS0_1	-	LS0_1
DC18.LS1_1	-	LS1_1
DC18.LS2_1	-	LS2_1
DC18.LS3_1	-	LS3_1
DC18.LS4_1	-	LS4_1
DC18.LS5_1	-	LS5_1
DC19	-	Device Capability: CPU2 Lx SRAM Customization
DC19.LS0_2	-	LS0_2
DC19.LS1_2	-	LS1_2
DC19.LS2_2	-	LS2_2
DC19.LS3_2	-	LS3_2
DC19.LS4_2	-	LS4_2
DC19.LS5_2	-	LS5_2
DC20	-	Device Capability: GSx SRAM Customization
DC20.GS0	-	GS0
DC20.GS1	-	GS1
DC20.GS2	-	GS2
DC20.GS3	-	GS3
DC20.GS4	-	GS4
DC20.GS5	-	GS5
DC20.GS6	-	GS6
DC20.GS7	-	GS7
DC20.GS8	-	GS8
DC20.GS9	-	GS9
DC20.GS10	-	GS10
DC20.GS11	-	GS11
DC20.GS12	-	GS12
DC20.GS13	-	GS13
DC20.GS14	-	GS14
DC20.GS15	-	GS15
PERCNF1	-	Peripheral Configuration register
PERCNF1.ADC_A_MODE	-	ADC_A mode setting bit
PERCNF1.ADC_B_MODE	-	ADC_B mode setting bit
PERCNF1.ADC_C_MODE	-	ADC_C mode setting bit
PERCNF1.ADC_D_MODE	-	ADC_D mode setting bit
PERCNF1.USB_A_PHY	-	USB_A_PHY
FUSEERR	-	e-Fuse error Status register
FUSEERR.ALERR	-	Efuse Autoload Error Status
FUSEERR.ERR	-	Efuse Self Test Error Status
SOFTPRES0	-	Processing Block Software Reset register
SOFTPRES0.CPU1_CLA1	-	CPU1_CLA1 software reset bit
SOFTPRES0.CPU2_CLA1	-	CPU2_CLA1 software reset bit
SOFTPRES1	-	EMIF Software Reset register
SOFTPRES1.EMIF1	-	EMIF1 software reset bit
SOFTPRES1.EMIF2	-	EMIF2 software reset bit
SOFTPRES2.EPWM8	-	EPWM8 software reset bit
SOFTPRES2.EPWM9	-	EPWM9 software reset bit
SOFTPRES2.EPWM10	-	EPWM10 software reset bit
SOFTPRES2.EPWM11	-	EPWM11 software reset bit
SOFTPRES2.EPWM12	-	EPWM12 software reset bit
SOFTPRES3.ECAP3	-	ECAP3 software reset bit
SOFTPRES3.ECAP4	-	ECAP4 software reset bit
SOFTPRES3.ECAP5	-	ECAP5 software reset bit
SOFTPRES3.ECAP6	-	ECAP6 software reset bit
SOFTPRES4.EQEP2	-	EQEP2 software reset bit
SOFTPRES4.EQEP3	-	EQEP3 software reset bit
SOFTPRES6	-	Peripheral Software Reset register
SOFTPRES6.SD1	-	SD1 software reset bit
SOFTPRES6.SD2	-	SD2 software reset bit
SOFTPRES7.SCI_D	-	SCI_D software reset bit
SOFTPRES8.SPI_B	-	SPI_B software reset bit
SOFTPRES8.SPI_C	-	SPI_C software reset bit
SOFTPRES11	-	Peripheral Software Reset register
SOFTPRES11.MCBSP_A	-	McBSP_A software reset bit
SOFTPRES11.MCBSP_B	-	McBSP_B software reset bit
SOFTPRES11.USB_A	-	USB_A software reset bit
SOFTPRES13.ADC_B	-	ADC_B software reset bit
SOFTPRES13.ADC_D	-	ADC_D software reset bit
SOFTPRES14.CMPSS5	-	CMPSS5 software reset bit
SOFTPRES14.CMPSS6	-	CMPSS6 software reset bit
SOFTPRES14.CMPSS7	-	CMPSS7 software reset bit
SOFTPRES14.CMPSS8	-	CMPSS8 software reset bit
SOFTPRES16	-	Peripheral Software Reset register
SOFTPRES16.DAC_A	-	Buffered_DAC_A software reset bit
SOFTPRES16.DAC_B	-	Buffered_DAC_B software reset bit
SOFTPRES16.DAC_C	-	Buffered_DAC_C software reset bit
CPUSEL0	-	CPU Select register for common peripherals
CPUSEL0.EPWM1	-	EPWM1 CPU select bit
CPUSEL0.EPWM2	-	EPWM2 CPU select bit
CPUSEL0.EPWM3	-	EPWM3 CPU select bit
CPUSEL0.EPWM4	-	EPWM4 CPU select bit
CPUSEL0.EPWM5	-	EPWM5 CPU select bit
CPUSEL0.EPWM6	-	EPWM6 CPU select bit
CPUSEL0.EPWM7	-	EPWM7 CPU select bit
CPUSEL0.EPWM8	-	EPWM8 CPU select bit
CPUSEL0.EPWM9	-	EPWM9 CPU select bit
CPUSEL0.EPWM10	-	EPWM10 CPU select bit
CPUSEL0.EPWM11	-	EPWM11 CPU select bit
CPUSEL0.EPWM12	-	EPWM12 CPU select bit
CPUSEL1	-	CPU Select register for common peripherals
CPUSEL1.ECAP1	-	ECAP1 CPU select bit
CPUSEL1.ECAP2	-	ECAP2 CPU select bit
CPUSEL1.ECAP3	-	ECAP3 CPU select bit
CPUSEL1.ECAP4	-	ECAP4 CPU select bit
CPUSEL1.ECAP5	-	ECAP5 CPU select bit
CPUSEL1.ECAP6	-	ECAP6 CPU select bit
CPUSEL2	-	CPU Select register for common peripherals
CPUSEL2.EQEP1	-	EQEP1 CPU select bit
CPUSEL2.EQEP2	-	EQEP2 CPU select bit
CPUSEL2.EQEP3	-	EQEP3 CPU select bit
CPUSEL4	-	CPU Select register for common peripherals
CPUSEL4.SD1	-	SD1 CPU select bit
CPUSEL4.SD2	-	SD2 CPU select bit
CPUSEL5	-	CPU Select register for common peripherals
CPUSEL5.SCI_A	-	SCI_A CPU select bit
CPUSEL5.SCI_B	-	SCI_B CPU select bit
CPUSEL5.SCI_C	-	SCI_C CPU select bit
CPUSEL5.SCI_D	-	SCI_D CPU select bit
CPUSEL6	-	CPU Select register for common peripherals
CPUSEL6.SPI_A	-	SPI_A CPU select bit
CPUSEL6.SPI_B	-	SPI_B CPU select bit
CPUSEL6.SPI_C	-	SPI_C CPU select bit
CPUSEL7	-	CPU Select register for common peripherals
CPUSEL7.I2C_A	-	I2C_A CPU select bit
CPUSEL7.I2C_B	-	I2C_B CPU select bit
CPUSEL8	-	CPU Select register for common peripherals
CPUSEL8.CAN_A	-	CAN_A CPU select bit
CPUSEL8.CAN_B	-	CAN_B CPU select bit
CPUSEL9	-	CPU Select register for common peripherals
CPUSEL9.MCBSP_A	-	McBSP_A CPU select bit
CPUSEL9.MCBSP_B	-	McBSP_B CPU select bit
CPUSEL11	-	CPU Select register for common peripherals
CPUSEL11.ADC_A	-	ADC_A CPU select bit
CPUSEL11.ADC_B	-	ADC_B CPU select bit
CPUSEL11.ADC_C	-	ADC_C CPU select bit
CPUSEL11.ADC_D	-	ADC_D CPU select bit
CPUSEL12	-	CPU Select register for common peripherals
CPUSEL12.CMPSS1	-	CMPSS1 CPU select bit
CPUSEL12.CMPSS2	-	CMPSS2 CPU select bit
CPUSEL12.CMPSS3	-	CMPSS3 CPU select bit
CPUSEL12.CMPSS4	-	CMPSS4 CPU select bit
CPUSEL12.CMPSS5	-	CMPSS5 CPU select bit
CPUSEL12.CMPSS6	-	CMPSS6 CPU select bit
CPUSEL12.CMPSS7	-	CMPSS7 CPU select bit
CPUSEL12.CMPSS8	-	CMPSS8 CPU select bit
CPUSEL14	-	CPU Select register for common peripherals
CPUSEL14.DAC_A	-	Buffered_DAC_A CPU select bit
CPUSEL14.DAC_B	-	Buffered_DAC_B CPU select bit
CPUSEL14.DAC_C	-	Buffered_DAC_C CPU select bit
CPU2RESCTL	-	CPU2 Reset Control Register
CPU2RESCTL.RESET	-	CPU2 Reset Control bit
CPU2RESCTL.KEY	-	Key Qualifier for writes to this register
RSTSTAT	-	Reset Status register for secondary C28x CPUs
RSTSTAT.CPU2RES	-	CPU2 Reset Status bit
RSTSTAT.CPU2NMIWDRST	-	Indicates whether a CPU2.NMIWD reset was issued
RSTSTAT.CPU2HWBISTRST0	-	Indicates whether a HWBIST reset was issued to
RSTSTAT.CPU2HWBISTRST1	-	Indicates whether a HWBIST reset was issued to
LPMSTAT	-	LPM Status Register for secondary C28x CPUs
LPMSTAT.CPU2LPMSTAT	-	CPU2 LPM Status
SYSDBGCTL	-	System Debug Control register
SYSDBGCTL.BIT_0	-	Used in PLL startup. Only reset by POR.
CLKSEM	-	Clock Control Semaphore Register
CLKSEM.SEM	-	Semaphore for CLKCFG Ownership by CPU1 or CPU2
CLKSEM.KEY	-	Key Qualifier for writes to this register
CLKCFGLOCK1.SYSPLLCTL2	-	Lock bit for SYSPLLCTL2 register
CLKCFGLOCK1.SYSPLLCTL3	-	Lock bit for SYSPLLCTL3 register
CLKCFGLOCK1.AUXPLLCTL1	-	Lock bit for AUXPLLCTL1 register
CLKCFGLOCK1.AUXPLLMULT	-	Lock bit for AUXPLLMULT register
CLKCFGLOCK1.AUXCLKDIVSEL	-	Lock bit for AUXCLKDIVSEL register
CLKCFGLOCK1.PERCLKDIVSEL	-	Lock bit for PERCLKDIVSEL register
CLKSRCCTL1.INTOSC2OFF	-	Internal Oscillator 2 Off Bit
CLKSRCCTL1.XTALOFF	-	Crystal (External) Oscillator Off Bit
CLKSRCCTL2.AUXOSCCLKSRCSEL	-	AUXOSCCLK Source Select Bit
CLKSRCCTL2.CANBBCLKSEL	-	CANB Bit Clock Source Select Bit
SYSPLLMULT.FMULT	-	SYSPLL Fractional Multiplier
SYSPLLSTS.SLIPS	-	SYSPLL Slip Status Bit
AUXPLLCTL1	-	AUXPLL Control register-1
AUXPLLCTL1.PLLEN	-	AUXPLL enable/disable bit
AUXPLLCTL1.PLLCLKEN	-	AUXPLL bypassed or included in the AUXPLLCLK path
AUXPLLMULT	-	AUXPLL Multiplier register
AUXPLLMULT.IMULT	-	AUXPLL Integer Multiplier
AUXPLLMULT.FMULT	-	AUXPLL Fractional Multiplier
AUXPLLSTS	-	AUXPLL Status register
AUXPLLSTS.LOCKS	-	AUXPLL Lock Status Bit
AUXPLLSTS.SLIPS	-	AUXPLL Slip Status Bit
AUXCLKDIVSEL	-	Auxillary Clock Divider Select register
AUXCLKDIVSEL.AUXPLLDIV	-	AUXPLLCLK Divide Select
PERCLKDIVSEL	-	Peripheral Clock Divider Selet register
PERCLKDIVSEL.EPWMCLKDIV	-	EPWM Clock Divide Select
PERCLKDIVSEL.EMIF1CLKDIV	-	EMIF1 Clock Divide Select
PERCLKDIVSEL.EMIF2CLKDIV	-	EMIF2 Clock Divide Select
CPUSYSLOCK1.HIBBOOTMODE	-	Lock bit for HIBBOOTMODE register
CPUSYSLOCK1.IORESTOREADDR	-	Lock bit for IORESTOREADDR Register
CPUSYSLOCK1.PCLKCR1	-	Lock bit for PCLKCR1 Register
CPUSYSLOCK1.PCLKCR5	-	Lock bit for PCLKCR5 Register
CPUSYSLOCK1.PCLKCR11	-	Lock bit for PCLKCR11 Register
CPUSYSLOCK1.PCLKCR12	-	Lock bit for PCLKCR12 Register
CPUSYSLOCK1.PCLKCR15	-	Lock bit for PCLKCR15 Register
CPUSYSLOCK1.PCLKCR16	-	Lock bit for PCLKCR16 Register
CPUSYSLOCK1.SECMSEL	-	Lock bit for SECMSEL Register
HIBBOOTMODE	-	HIB Boot Mode Register
IORESTOREADDR	-	IORestore() routine Address Register
IORESTOREADDR.ADDR	-	restoreIO() routine address
PCLKCR0.CLA1	-	CLA1 Clock Enable Bit
PCLKCR0.DMA	-	DMA Clock Enable bit
PCLKCR0.HRPWM	-	HRPWM Clock Enable Bit
PCLKCR0.GTBCLKSYNC	-	EPWM Time Base Clock Global sync
PCLKCR1	-	Peripheral Clock Gating Registers
PCLKCR1.EMIF1	-	EMIF1 Clock Enable bit
PCLKCR1.EMIF2	-	EMIF2 Clock Enable bit
PCLKCR2.EPWM8	-	EPWM8 Clock Enable bit
PCLKCR2.EPWM9	-	EPWM9 Clock Enable bit
PCLKCR2.EPWM10	-	EPWM10 Clock Enable bit
PCLKCR2.EPWM11	-	EPWM11 Clock Enable bit
PCLKCR2.EPWM12	-	EPWM12 Clock Enable bit
PCLKCR3.ECAP3	-	ECAP3 Clock Enable bit
PCLKCR3.ECAP4	-	ECAP4 Clock Enable bit
PCLKCR3.ECAP5	-	ECAP5 Clock Enable bit
PCLKCR3.ECAP6	-	ECAP6 Clock Enable bit
PCLKCR4.EQEP2	-	EQEP2 Clock Enable bit
PCLKCR4.EQEP3	-	EQEP3 Clock Enable bit
PCLKCR6	-	Peripheral Clock Gating Registers
PCLKCR6.SD1	-	SD1 Clock Enable bit
PCLKCR6.SD2	-	SD2 Clock Enable bit
PCLKCR7.SCI_D	-	SCI_D Clock Enable bit
PCLKCR8.SPI_B	-	SPI_B Clock Enable bit
PCLKCR8.SPI_C	-	SPI_C Clock Enable bit
PCLKCR10.CAN_B	-	CAN_B Clock Enable bit
PCLKCR11	-	Peripheral Clock Gating Registers
PCLKCR11.MCBSP_A	-	McBSP_A Clock Enable bit
PCLKCR11.MCBSP_B	-	McBSP_B Clock Enable bit
PCLKCR11.USB_A	-	USB_A Clock Enable bit
PCLKCR12	-	Peripheral Clock Gating Registers
PCLKCR12.UPP_A	-	uPP_A Clock Enable bit
PCLKCR13.ADC_B	-	ADC_B Clock Enable bit
PCLKCR13.ADC_D	-	ADC_D Clock Enable bit
PCLKCR14.CMPSS5	-	CMPSS5 Clock Enable bit
PCLKCR14.CMPSS6	-	CMPSS6 Clock Enable bit
PCLKCR14.CMPSS7	-	CMPSS7 Clock Enable bit
PCLKCR14.CMPSS8	-	CMPSS8 Clock Enable bit
PCLKCR16	-	Peripheral Clock Gating Registers
PCLKCR16.DAC_A	-	Buffered_DAC_A Clock Enable Bit
PCLKCR16.DAC_B	-	Buffered_DAC_B Clock Enable Bit
PCLKCR16.DAC_C	-	Buffered_DAC_C Clock Enable Bit
SECMSEL	-	Secondary Master Select register for common
SECMSEL.PF1SEL	-	Secondary Master Select for VBUS32_1 Bridge
SECMSEL.PF2SEL	-	Secondary Master Select for VBUS32_2 Bridge
LPMCR.M0M1MODE	-	Configuration for M0 and M1 mode during HIB
LPMCR.IOISODIS	-	IO Isolation Disable
RESC.HWBISTN	-	HWBISTn Reset Cause Indication Bit
RESC.HIBRESETN	-	HIBRESETn Reset Cause Indication Bit
RESC.TRSTN_PIN_STATUS	-	TRSTn Status
WDWCR.FIRSTKEY	-	First Key Detect Flag
CLA1TASKSRCSELLOCK	-	CLA1 Task Trigger Source Select Lock Register
CLA1TASKSRCSELLOCK.CLA1TASKSRCSEL1	-	CLA1TASKSRCSEL1 Register Lock bit
CLA1TASKSRCSELLOCK.CLA1TASKSRCSEL2	-	CLA1TASKSRCSEL2 Register Lock bit
DMACHSRCSELLOCK	-	DMA Channel Triger Source Select Lock Register
DMACHSRCSELLOCK.DMACHSRCSEL1	-	DMACHSRCSEL1 Register Lock bit
DMACHSRCSELLOCK.DMACHSRCSEL2	-	DMACHSRCSEL2 Register Lock bit
CLA1TASKSRCSEL1	-	CLA1 Task Trigger Source Select Register-1
CLA1TASKSRCSEL1.TASK1	-	Selects the Trigger Source for TASK1 of
CLA1TASKSRCSEL1.TASK2	-	Selects the Trigger Source for TASK2 of
CLA1TASKSRCSEL1.TASK3	-	Selects the Trigger Source for TASK3 of
CLA1TASKSRCSEL1.TASK4	-	Selects the Trigger Source for TASK4 of
CLA1TASKSRCSEL2	-	CLA1 Task Trigger Source Select Register-2
CLA1TASKSRCSEL2.TASK5	-	Selects the Trigger Source for TASK5 of
CLA1TASKSRCSEL2.TASK6	-	Selects the Trigger Source for TASK6 of
CLA1TASKSRCSEL2.TASK7	-	Selects the Trigger Source for TASK7 of
CLA1TASKSRCSEL2.TASK8	-	Selects the Trigger Source for TASK8 of
DMACHSRCSEL1	-	DMA Channel Trigger Source Select Register-1
DMACHSRCSEL1.CH1	-	Selects the Trigger and Sync Source CH1 of DMA
DMACHSRCSEL1.CH2	-	Selects the Trigger and Sync Source CH2 of DMA
DMACHSRCSEL1.CH3	-	Selects the Trigger and Sync Source CH3 of DMA
DMACHSRCSEL1.CH4	-	Selects the Trigger and Sync Source CH4 of DMA
DMACHSRCSEL2	-	DMA Channel Trigger Source Select Register-2
DMACHSRCSEL2.CH5	-	Selects the Trigger and Sync Source CH5 of DMA
DMACHSRCSEL2.CH6	-	Selects the Trigger and Sync Source CH6 of DMA
SYNCSELECT.EPWM4SYNCIN	-	Selects Sync Input Source for EPWM4
SYNCSELECT.EPWM7SYNCIN	-	Selects Sync Input Source for EPWM7
SYNCSELECT.EPWM10SYNCIN	-	Selects Sync Input Source for EPWM10
SYNCSELECT.ECAP1SYNCIN	-	Selects Sync Input Source for ECAP1
SYNCSELECT.ECAP4SYNCIN	-	Selects Sync Input Source for ECAP4
ADCSOCOUTSELECT.PWM8SOCAEN	-	PWM8SOCAEN Enable for ADCSOCAO
ADCSOCOUTSELECT.PWM9SOCAEN	-	PWM9SOCAEN Enable for ADCSOCAO
ADCSOCOUTSELECT.PWM10SOCAEN	-	PWM10SOCAEN Enable for ADCSOCAO
ADCSOCOUTSELECT.PWM11SOCAEN	-	PWM11SOCAEN Enable for ADCSOCAO
ADCSOCOUTSELECT.PWM12SOCAEN	-	PWM12SOCAEN Enable for ADCSOCAO
ADCSOCOUTSELECT.PWM8SOCBEN	-	PWM8SOCBEN Enable for ADCSOCBO
ADCSOCOUTSELECT.PWM9SOCBEN	-	PWM9SOCBEN Enable for ADCSOCBO
ADCSOCOUTSELECT.PWM10SOCBEN	-	PWM10SOCBEN Enable for ADCSOCBO
ADCSOCOUTSELECT.PWM11SOCBEN	-	PWM11SOCBEN Enable for ADCSOCBO
ADCSOCOUTSELECT.PWM12SOCBEN	-	PWM12SOCBEN Enable for ADCSOCBO
-	REVID.REVID	Device Revision ID. This is specific to the Device
-	TRIMERRSTS	TRIM Error Status register
-	TRIMERRSTS.LERR	TRIM Load error status
-	SOFTPRES10	CAN Software Reset register
-	SOFTPRES10.CAN_A	CAN_A software reset bit
-	SOFTPRES21	DCC Software Reset register
-	SOFTPRES21.DCC0	DCC Module reset bit
-	SOFTPRES27	EPG Software Reset register
-	SOFTPRES27.EPG1	EPG Module Reset Bit
-	SOFTPRES28	Flash Software Reset register
-	SOFTPRES28.FLASHA	Flash Wrapper Module Reset Bit
-	TAP_STATUS	Status of JTAG State machine & Debugger Connect
-	TAP_STATUS.TAP_STATE	Present TAP State
-	TAP_STATUS.DCON	Debugger Connect Indication
-	ECAPTYPE	Configures ECAP Type for the device
-	ECAPTYPE.TYPE	Configure ECAP type
-	ECAPTYPE.LOCK	Lock bit for the register
-	CLKCFGLOCK1.XTALCR	Lock bit for XTALCR & XTALCR2 register
-	CLKSRCCTL1.INTOSC2CLKMODE	Select IntR or ExtR mode for INTOSC2
-	SYSPLLMULT.ODIV	Output Clock Divider
-	SYSPLLMULT.REFDIV	Reference Clock Divider
-	SYSPLLSTS.SLIPS_NOTSUPPORTED	SYSPLL Slip Status Bit
-	SYSPLLSTS.REF_LOSTS	SYSPLL "Reference Lost" Status Bit
-	SYSCLKDIVSEL.PLLSYSCLKDIV_LSB	Odd clock divider
-	MCDCR.SYSREF_LOSTS	SYSPLL "Reference Lost" Status Bit
-	MCDCR.SYSREF_LOSTSCLR	Clear for Ref clock lost status
-	MCDCR.SYSREF_LOST_MCD_EN	Enable for PLL REF_CLK_LOST as MCD cause
-	X1CNT.CLR	X1 Counter Clear
-	XTALCR	XTAL Control Register
-	XTALCR.OSCOFF	XTAL Oscillator powered-down
-	XTALCR.SE	XTAL Oscilator in Single-Ended mode
-	XTALCR2	XTAL Control Register for pad init
-	XTALCR2.XIF	XI Initial value deposited before XOSC start
-	XTALCR2.XOF	XO Initial value deposited before XOSC start
-	XTALCR2.FEN	XOSC pads initialisation enable
-	CLKFAILCFG	Clock Fail cause Configuration
-	CLKFAILCFG.DCC0_ERROR_EN	DCC0 Error causes Clock fail NMI, ERROR
-	CPUSYSLOCK1.PCLKCR20	Lock bit for PCLKCR20 Register
-	CPUSYSLOCK1.PCLKCR21	Lock bit for PCLKCR21 Register
-	CPUSYSLOCK1.PCLKCR22	Lock bit for PCLKCR22 Register
-	CPUSYSLOCK2	Lock bit for CPUSYS registers
-	CPUSYSLOCK2.PCLKCR27	Lock bit for PCLKCR27 Register
-	CPUSYSLOCK2.USER_REG1_SYSRSN	Lock bit for USER_REG1_SYSRSn
-	CPUSYSLOCK2.USER_REG2_SYSRSN	Lock bit for USER_REG2_SYSRSn
-	CPUSYSLOCK2.USER_REG1_XRSN	Lock bit for USER_REG1_XRSn
-	CPUSYSLOCK2.USER_REG2_XRSN	Lock bit for USER_REG2_XRSn
-	CPUSYSLOCK2.USER_REG1_PORESETN	Lock bit for USER_REG1_PORESETn
-	CPUSYSLOCK2.USER_REG2_PORESETN	Lock bit for USER_REG2_PORESETn
-	CPUSYSLOCK2.USER_REG3_PORESETN	Lock bit for USER_REG3_PORESETn
-	CPUSYSLOCK2.USER_REG4_PORESETN	Lock bit for USER_REG4_PORESETn
-	PCLKCR0.HRCAL	HRCAL Clock Enable Bit
-	PCLKCR21	Peripheral Clock Gating Register - DCC
-	PCLKCR21.DCC0	DCC0 Clock Enable Bit
-	PCLKCR27	Peripheral Clock Gating Register - EPG
-	PCLKCR27.EPG1	EPG1 Clock Enable Bit
-	SIMRESET	Simulated Reset Register
-	SIMRESET.CPU1RSN	Generates a reset to CPU
-	SIMRESET.XRSN	Generates a simulated XRSn
-	SIMRESET.KEY	Key value to enable write
-	RESCCLR	Reset Cause Clear Register
-	RESCCLR.POR	POR Reset Cause Indication Bit
-	RESCCLR.XRSN	XRSn Reset Cause Indication Bit
-	RESCCLR.WDRSN	WDRSn Reset Cause Indication Bit
-	RESCCLR.NMIWDRSN	NMIWDRSn Reset Cause Indication Bit
-	RESCCLR.SCCRESETN	SCCRESETn Reset Cause Indication Bit
-	RESCCLR.SIMRESET_CPU1RSN	SIMRESET_CPU1RSn Reset Cause Indication Bit
-	RESCCLR.SIMRESET_XRSN	SIMRESET_XRSn Reset Cause Indication Bit
-	RESC.SIMRESET_CPU1RSN	SIMRESET_CPU1RSn Reset Cause Indication Bit
-	RESC.SIMRESET_XRSN	SIMRESET_XRSn Reset Cause Indication Bit
-	RESC.DCON	Debugger conntion status to C28x
-	USER_REG1_SYSRSN	Software Configurable registers reset by SYSRSn
-	USER_REG2_SYSRSN	Software Configurable registers reset by SYSRSn
-	USER_REG1_XRSN	Software Configurable registers reset by XRSn
-	USER_REG2_XRSN	Software Configurable registers reset by XRSn
-	USER_REG1_PORESETN	Software Configurable registers reset by PORESETn
-	USER_REG2_PORESETN	Software Configurable registers reset by PORESETn
-	USER_REG3_PORESETN	Software Configurable registers reset by PORESETn
-	USER_REG4_PORESETN	Software Configurable registers reset by PORESETn
-	WDCR.WDPRECLKDIV	WD Pre Clock Divider
-	SYS_ERR_INT_FLG	Status of interrupts due to multiple different errors
-	SYS_ERR_INT_FLG.GINT	Global Interrupt flag
-	SYS_ERR_INT_FLG.CORRECTABLE_ERR	RAM/Flash correctable error flag
-	SYS_ERR_INT_FLG.RAM_ACC_VIOL	A RAM access vioation flag.
-	SYS_ERR_INT_FLG.EPG1_INT	EPG1_INT Interrupt flag.
-	SYS_ERR_INT_FLG.FPU_UFLOW	FPU_UFLOW Interrupt flag.
-	SYS_ERR_INT_FLG.FPU_OFLOW	FPU_OFLOW Interrupt flag.
-	SYS_ERR_INT_CLR	SYS_ERR_INT_FLG clear register
-	SYS_ERR_INT_CLR.GINT	Global Interrupt flag Clear bit
-	SYS_ERR_INT_CLR.CORRECTABLE_ERR	CORRECTABLE_ERR interrupt flag clear
-	SYS_ERR_INT_CLR.RAM_ACC_VIOL	RAM_ACC_VIOL interrupt flag clear
-	SYS_ERR_INT_CLR.EPG1_INT	EPG1_INT interrupt flag clear bit
-	SYS_ERR_INT_CLR.FPU_UFLOW	FPU_UFLOW interrupt flag clear bit
-	SYS_ERR_INT_CLR.FPU_OFLOW	FPU_OFLOW interrupt flag clear bit
-	SYS_ERR_INT_SET	SYS_ERR_INT_FLG set register
-	SYS_ERR_INT_SET.CORRECTABLE_ERR	CORRECTABLE_ERR interrupt flag
-	SYS_ERR_INT_SET.RAM_ACC_VIOL	RAM_ACC_VIOL interrupt flag set
-	SYS_ERR_INT_SET.EPG1_INT	EPG1_INT interrupt flag set bit
-	SYS_ERR_INT_SET.FPU_UFLOW	FPU_UFLOW interrupt flag set bit
-	SYS_ERR_INT_SET.FPU_OFLOW	FPU_OFLOW interrupt flag set bit
-	SYS_ERR_INT_SET.KEY	KEY field
-	SYS_ERR_MASK	SYS_ERR_MASK register
-	SYS_ERR_MASK.CORRECTABLE_ERR	CORRECTABLE_ERR flag mask bit
-	SYS_ERR_MASK.RAM_ACC_VIOL	RAM_ACC_VIOL flag mask bit
-	SYS_ERR_MASK.EPG1_INT	EPG1_INT flag mask bit
-	SYS_ERR_MASK.FPU_UFLOW	FPU_UFLOW flag mask bit
-	SYS_ERR_MASK.FPU_OFLOW	FPU_OFLOW flag mask bit
-	SYS_ERR_MASK.KEY	KEY field

    SysCtl_pollCpuTimer

    SysCtl_getClock

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t temp;
	3	3		uint32_t oscSource;
	4	4		uint32_t clockOut;
	5	5
	6	6		//
	7	7		// Don't proceed if an MCD failure is detected.
	8	8		//
	9	9		if(SysCtl_isMCDClockFailureDetected())
	10	10		{
	11	11		//
	12	12		// OSCCLKSRC2 failure detected. Returning the INTOSC1 rate. You need
	13	13		// to handle the MCD and clear the failure.
	14	14		//
	15	15		clockOut = SYSCTL_DEFAULT_OSC_FREQ;
	16	16		}
	17	17		else
	18	18		{
	19	19		//
	20	20		// If one of the internal oscillators is being used, start from the
	21	21		// known default frequency.  Otherwise, use clockInHz parameter.
	22	22		//
	23	23		oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &
	24	24		(uint32_t)SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M;
	25	25
	26	26		if((oscSource == (SYSCTL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) ||
	27	27		(oscSource == (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S)))
	28	28		{
	29	29		clockOut = SYSCTL_DEFAULT_OSC_FREQ;
	30	30		}
	31	31		else
	32	32		{
	33	33		clockOut = clockInHz;
	34	34		}
	35	35
	36	36		//
	37	37		// If the PLL is enabled calculate its effect on the clock
	38	38		//
	39	39		if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &
	40	40		(SYSCTL_SYSPLLCTL1_PLLEN | SYSCTL_SYSPLLCTL1_PLLCLKEN)) == 3U)
	41	41		{
	42	42		//
n	43		-	// Calculate portion from fractional multiplier
	44		-	//
	45		-	temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) &
	46		-	SYSCTL_SYSPLLMULT_FMULT_M) >>
	47		-	SYSCTL_SYSPLLMULT_FMULT_S)) / 4U;
	48		-
	49		-	//
	50		-	// Calculate integer multiplier and fixed divide by 2
		43	+	// Calculate integer multiplier
	51	44		//
	52	45		clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) &
	53	46		SYSCTL_SYSPLLMULT_IMULT_M) >>
	54	47		SYSCTL_SYSPLLMULT_IMULT_S);
	55	48
	56	49		//
n	57		-	// Add in fractional portion
		50	+	// Calculate PLL divider
	58	51		//
		52	+	temp = ((((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) &
		53	+	SYSCTL_SYSPLLMULT_REFDIV_M) >>
		54	+	SYSCTL_SYSPLLMULT_REFDIV_S) + 1U) *
		55	+	(((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) &
		56	+	SYSCTL_SYSPLLMULT_ODIV_M) >>
		57	+	SYSCTL_SYSPLLMULT_ODIV_S) + 1U));
		58	+
		59	+	//
		60	+	//  Divide dividers
		61	+	//
		62	+	if(temp != 0U)
		63	+	{
	59		-	clockOut += temp;
		64	+	clockOut /= temp;
		65	+	}
	60	66		}
	61	67
	62	68		if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
	63	69		SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) != 0U)
	64	70		{
		71	+	uint32_t divider = 2U *
	65		-	clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
		72	+	(HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
	66		-	SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M));
		73	+	SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M);
		74	+	if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
		75	+	SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_LSB) != 0U)
		76	+	{
		77	+	divider++;
		78	+	}
		79	+
		80	+	clockOut /= divider;
	67	81		}
	68	82		}
	69	83
	70	84		return(clockOut);
	71	85		}
	72	86

    SysCtl_getAuxClock

    SysCtl_setClock

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	uint16_t divSel;
		2	+	uint16_t divSel, pllen, oscclksrcsel, pllLockStatus, xtalval;
	3		-	uint16_t iMult = 0U, fMult = 0U, pllMult = 0U, div;
		3	+	uint32_t oscSource, pllMult, mult;
	4		-	bool status, sysclkInvalidFreq = true;
		4	+	uint32_t timeout, refdiv;
	5		-	uint16_t i, tempSCSR, tempWDCR, tempWDWCR, intStatus;
		5	+	bool status = false;
	6		-	uint16_t t1TCR, t1TPR, t1TPRH, t2TCR, t2TPR, t2TPRH, t2CLKCTL;
	7		-	uint32_t t1PRD, t2PRD, ctr1;
	8		-	float32_t sysclkToInClkError, mult;
	9	6
	10	7		//
	11	8		// Check the arguments.
	12	9		//
n	13		-	ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid
		10	+	ASSERT((config & SYSCTL_OSCSRC_M) <= SYSCTL_OSCSRC_M);
		11	+	ASSERT(((config & SYSCTL_PLL_CONFIG_M) == SYSCTL_PLL_ENABLE) ||
		12	+	((config & SYSCTL_PLL_CONFIG_M) == SYSCTL_PLL_BYPASS) ||
		13	+	((config & SYSCTL_PLL_CONFIG_M) == SYSCTL_PLL_DISABLE));
	14	14
	15	15		//
	16	16		// Don't proceed to the PLL initialization if an MCD failure is detected.
	17	17		//
	18	18		if(SysCtl_isMCDClockFailureDetected())
	19	19		{
	20	20		//
	21	21		// OSCCLKSRC2 failure detected. Returning false. You'll need to clear
	22	22		// the MCD error.
	23	23		//
	24	24		status = false;
	25	25		}
	26	26		else
	27	27		{
		28	+	if((config & SYSCTL_OSCSRC_EXTROSC2) != 0U)
	28		-	//
		29	+	{
	29		-	// Configure oscillator source
		30	+	//
		31	+	// Switch OSCCLKSRC to INTOSC1 before switching INTOSC2 from INTR
		32	+	// to EXTR
		33	+	//
		34	+	SysCtl_selectOscSource(SYSCTL_OSCSRC_OSC1);
		35	+	SysCtl_delay(200U);
		36	+
		37	+	//
		38	+	// Write EXTROSCCSR1 delay based on 10nf cap.
		39	+	//
		40	+	HWREG(ANALOGSUBSYS_BASE + ASYSCTL_O_EXTROSCCSR1) = 0x0000C00U;
		41	+
		42	+	//
		43	+	// Switch INTOSC to XROSC
		44	+	//
		45	+	SysCtl_setIntOSC2_Mode(SYSCTL_INTOSC2_MODE_EXTR);
		46	+	SysCtl_delay(10000U);
		47	+
		48	+	while(ASysCtl_getExtROscStatus() != ASYSCTL_EXTR_ENABLE_COMPLETE);
	30		-	//
		49	+	}
	31		-	SysCtl_selectOscSource(config & SYSCTL_OSCSRC_M);
	32	50
	33	51		//
	34	52		// Bypass PLL
	35	53		//
	36	54		EALLOW;
	37	55		HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
	38	56		~SYSCTL_SYSPLLCTL1_PLLCLKEN;
	39	57		EDIS;
	40	58
	41	59		//
	42	60		// Delay of at least 120 OSCCLK cycles required post PLL bypass
	43	61		//
	44	62		SysCtl_delay(23U);
	45	63
	46	64		//
n	47		-	// Configure PLL if enabled
		65	+	// Derive the current and previous oscillator clock source values
	48		-	//
	49		-	EALLOW;
	50		-	if((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE)
	51		-	{
		66	+	//
	52		-	if((HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) &
		67	+	oscclksrcsel = HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &
	53		-	SYSCTL_SYSDBGCTL_BIT_0) != 0U)
		68	+	(uint16_t)SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M;
		69	+
		70	+	xtalval = (HWREGH(CLKCFG_BASE + SYSCTL_O_XTALCR) &
		71	+	(uint16_t)SYSCTL_XTALCR_SE);
		72	+
		73	+	oscSource = (config & SYSCTL_OSCSRC_M) >> SYSCTL_OSCSRC_S;
		74	+
		75	+	//
		76	+	// Check if the oscillator clock source has changed
		77	+	//
		78	+	if((oscclksrcsel | xtalval) != oscSource)
		79	+	{
	54		-	{
		80	+	//
	55		-	//
		81	+	// Turn off PLL
	56		-	// The user can optionally insert handler code here. This will
	57		-	// only be executed if a watchdog reset occurred after a failed
	58		-	// system PLL initialization. See your device user's guide for
	59		-	// more information.
	60		-	//
	61		-	// If the application has a watchdog reset handler, this bit
	62		-	// should be checked to determine if the watchdog reset
	63		-	// occurred because of the PLL.
	64		-	//
	65		-	// No action here will continue with retrying the PLL as
	66		-	// normal.
	67		-	//
	68		-	}
		82	+	//
	69		-
		83	+	EALLOW;
	70		-	//
	71		-	// Set dividers to /1
	72		-	//
	73		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = 0U;
		84	+	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
		85	+	~SYSCTL_SYSPLLCTL1_PLLEN;
		86	+	EDIS;
	74	87
		88	+	//
		89	+	// Delay of at least 66 OSCCLK cycles required between
		90	+	// powerdown to powerup of PLL
		91	+	//
		92	+	SysCtl_delay(12U);
		93	+
		94	+	//
		95	+	// Configure oscillator source
		96	+	//
		97	+	SysCtl_selectOscSource(config & SYSCTL_OSCSRC_M);
		98	+
		99	+	//
		100	+	// Delay of at least 60 OSCCLK cycles
		101	+	//
		102	+	SysCtl_delay(11U);
		103	+	}
		104	+
		105	+	//
		106	+	// Set dividers to /1 to ensure the fastest PLL configuration
		107	+	//
		108	+	SysCtl_setPLLSysClk(1U);
		109	+
		110	+	//
		111	+	// Configure PLL if PLL usage is enabled or bypassed in config
		112	+	//
		113	+	if(((config & SYSCTL_PLL_CONFIG_M) == SYSCTL_PLL_ENABLE) ||
		114	+	((config & SYSCTL_PLL_CONFIG_M) == SYSCTL_PLL_BYPASS))
		115	+	{
	75	116		//
	76	117		// Get the PLL multiplier settings from config
	77	118		//
n	78		-	iMult |= (uint16_t)(config & SYSCTL_IMULT_M);
		119	+	pllMult  = ((config & SYSCTL_IMULT_M) <<
	79		-	fMult |= (uint16_t)((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S);
	80		-	pllMult |= (iMult << SYSCTL_SYSPLLMULT_IMULT_S) |
	81		-	(fMult << SYSCTL_SYSPLLMULT_FMULT_S);
		120	+	SYSCTL_SYSPLLMULT_IMULT_S);
	82	121
		122	+	pllMult |= (((config & SYSCTL_REFDIV_M) >>
		123	+	SYSCTL_REFDIV_S) <<
		124	+	SYSCTL_SYSPLLMULT_REFDIV_S);
		125	+
		126	+	pllMult |= (((config & SYSCTL_ODIV_M) >>
		127	+	SYSCTL_ODIV_S) <<
		128	+	SYSCTL_SYSPLLMULT_ODIV_S);
		129	+
	83	130		//
n	84		-	// Lock the PLL five times. This helps ensure a successful start.
		131	+	// Get the PLL multipliers currently programmed
	85		-	// Five is the minimum recommended number. The user can increase
	86		-	// this number according to allotted system initialization time.
	87	132		//
n	88		-	for(i = 0U; i < 5U; i++)
		133	+	mult  = ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) &
		134	+	SYSCTL_SYSPLLMULT_IMULT_M) >>
		135	+	SYSCTL_SYSPLLMULT_IMULT_S);
		136	+
		137	+	mult |= (HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) &
		138	+	SYSCTL_SYSPLLMULT_REFDIV_M);
		139	+
		140	+	mult |= (HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) &
		141	+	SYSCTL_SYSPLLMULT_ODIV_M);
		142	+
		143	+	pllen = (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &
		144	+	SYSCTL_SYSPLLCTL1_PLLEN);
		145	+
		146	+	//
		147	+	// Lock PLL only if the multipliers need an update or PLL needs
		148	+	// to be powered on / enabled
		149	+	//
		150	+	if((mult !=  pllMult) || (pllen != 1U))
	89	151		{
	90	152		//
	91	153		// Turn off PLL
	92	154		//
		155	+	EALLOW;
	93	156		HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
	94	157		~SYSCTL_SYSPLLCTL1_PLLEN;
		158	+	EDIS;
	95	159
n	96		-	asm(" RPT #60 || NOP");
		160	+	//
		161	+	// Delay of at least 66 OSCCLK cycles required between
		162	+	// powerdown to powerup of PLL
		163	+	//
		164	+	SysCtl_delay(12U);
	97	165
	98	166		//
	99	167		// Write multiplier, which automatically turns on the PLL
	100	168		//
		169	+	EALLOW;
	101		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) = pllMult;
		170	+	HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) = pllMult;
	102	171
	103	172		//
		173	+	// Enable/ turn on PLL
		174	+	//
		175	+	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) |=
		176	+	SYSCTL_SYSPLLCTL1_PLLEN;
		177	+
		178	+	//
	104		-	// Wait for the SYSPLL lock counter
		179	+	// Wait for the SYSPLL lock counter or a timeout
		180	+	// This timeout needs to be computed based on OSCCLK
		181	+	// with a factor of REFDIV.
		182	+	// Lock time is 1024 OSCCLK * (REFDIV+1)
	105	183		//
		184	+	refdiv  = ((config & SYSCTL_REFDIV_M) >> SYSCTL_REFDIV_S);
		185	+
		186	+	timeout = (1024U * (refdiv + 1U));
	106		-	while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) &
		187	+	pllLockStatus = HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) &
	107		-	SYSCTL_SYSPLLSTS_LOCKS) == 0U)
		188	+	SYSCTL_SYSPLLSTS_LOCKS;
		189	+
		190	+	while((pllLockStatus != 1U) && (timeout != 0U))
	108	191		{
		192	+	pllLockStatus = HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) &
		193	+	SYSCTL_SYSPLLSTS_LOCKS;
	109		-	//
		194	+	timeout--;
	110		-	// Consider to servicing the watchdog using
	111		-	// SysCtl_serviceWatchdog()
	112		-	//
	113	195		}
		196	+	EDIS;
		197	+
		198	+	//
		199	+	// Check PLL Frequency using DCC
		200	+	//
		201	+	status = SysCtl_isPLLValid(
		202	+	(config & SYSCTL_DCC_BASE_M ),
		203	+	(config & SYSCTL_OSCSRC_M),
		204	+	(config & (SYSCTL_IMULT_M | SYSCTL_ODIV_M |
		205	+	SYSCTL_REFDIV_M)));
		206	+
		207	+	}
		208	+	else
	114		-	}
		209	+	{
		210	+	//
		211	+	// Re-Lock of PLL not needed since the multipliers
		212	+	// are not updated
		213	+	//
		214	+	status = true;
	115		-	}
		215	+	}
	116		-
	117		-	//
	118		-	// Configure Dividers. Set divider to produce slower output frequency
	119		-	// to limit current increase.
	120		-	//
	121		-	divSel = (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S;
	122		-
	123		-	if(divSel != (126U / 2U))
	124		-	{
		216	+	}
		217	+	else if((config & SYSCTL_PLL_CONFIG_M) == SYSCTL_PLL_DISABLE)
		218	+	{
		219	+	//
		220	+	// Turn off PLL when the PLL is disabled in config
		221	+	//
		222	+	EALLOW;
	125		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
		223	+	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
	126		-	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
		224	+	~SYSCTL_SYSPLLCTL1_PLLEN;
	127		-	~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | (divSel + 1U);
		225	+	EDIS;
		226	+
		227	+	//
		228	+	// PLL is bypassed and not in use
		229	+	// Status is updated to true to allow configuring the dividers later
		230	+	//
		231	+	status = true;
	128	232		}
	129	233		else
	130	234		{
n	131		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
	132		-	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
	133		-	~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel;
	134		-	}
	135		-
	136		-	//
		235	+	//
	137		-	//      *CAUTION*
		236	+	// Empty
	138		-	// It is recommended to use the following watchdog code to monitor the
	139		-	// PLLstartup sequence. If your application has already cleared the
	140		-	// watchdog SCRS[WDOVERRIDE] bit this cannot be done. It is recommended
	141		-	// not to clear this bit until after the PLL has been initiated.
	142		-	//
		237	+	//
	143		-
	144		-	//
	145		-	// Backup User Watchdog
	146		-	//
	147		-	tempSCSR = HWREGH(WD_BASE + SYSCTL_O_SCSR);
	148		-	tempWDCR = HWREGH(WD_BASE + SYSCTL_O_WDCR);
	149		-	tempWDWCR = HWREGH(WD_BASE + SYSCTL_O_WDWCR);
	150		-
	151		-	//
	152		-	// Disable windowed functionality, reset counter
	153		-	//
	154		-	HWREGH(WD_BASE + SYSCTL_O_WDWCR) = 0x0U;
	155		-	SysCtl_serviceWatchdog();
	156		-
	157		-	//
	158		-	// Disable global interrupts
	159		-	//
	160		-	intStatus = __disable_interrupts();
	161		-
	162		-	//
	163		-	// Configure for watchdog reset and to run at max frequency
	164		-	//
	165		-	EALLOW;
	166		-	HWREGH(WD_BASE + SYSCTL_O_SCSR) = 0x0U;
	167		-	HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS;
	168		-
	169		-	//
	170		-	// This bit is reset only by power-on-reset (POR) and will not be
	171		-	// cleared by a WD reset
	172		-	//
	173		-	HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) |= SYSCTL_SYSDBGCTL_BIT_0;
	174		-
	175		-	//
	176		-	// Enable PLLSYSCLK is fed from system PLL clock
	177		-	//
	178		-	HWREGH(CLKCFG_BASE +
	179		-	SYSCTL_O_SYSPLLCTL1) |= SYSCTL_SYSPLLCTL1_PLLCLKEN;
	180		-
	181		-	EDIS;
	182		-
	183		-	//
	184		-	// Delay to ensure system is clocking from PLL prior to clearing
	185		-	// status bit
	186		-	//
	187		-	SysCtl_delay(3U);
	188		-
	189		-	//
	190		-	// Slip Bit Monitor and SYSCLK Frequency Check using timers
	191		-	// Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer
	192		-	// counts are off by +/- 10%. At a minimum, SYSCLK check is performed.
	193		-	// Re-lock attempt is carried out if SLIPS bit is set.
	194		-	// This while loop is monitored by watchdog.
	195		-	// In the event that the PLL does not successfully lock, the loop will
	196		-	// be aborted by watchdog reset.
	197		-	//
	198		-	while(((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) &&
	199		-	(sysclkInvalidFreq == true))
	200		-	{
		238	+	}
		239	+
		240	+	//
		241	+	// If PLL locked successfully, configure the dividers
		242	+	// Or if PLL is bypassed, only configure the dividers
		243	+	//
		244	+	if(status)
		245	+	{
		246	+	//
		247	+	// Set divider to produce slower output frequency to limit current
		248	+	// increase.
		249	+	//
		250	+	divSel = (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S;
		251	+
	201	252		EALLOW;
n	202		-
		253	+	if(divSel == 126U)
	203		-	//
		254	+	{
	204		-	// Perform PLL re-lock only if SLIPS bit is set, otherwise monitor
	205		-	// SYSCLK frequency with timers
	206		-	//
	207		-	if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) &
		255	+	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
	208		-	SYSCTL_SYSPLLSTS_SLIPS) == 1U)
		256	+	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
		257	+	~(SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M |
		258	+	SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_LSB)) |
		259	+	(divSel / 2U);
	209		-	{
		260	+	}
		261	+	else if((divSel % 2U) == 1U)
	210		-	//
		262	+	{
	211		-	// Bypass PLL
	212		-	//
	213		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
		263	+	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
		264	+	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
		265	+	~SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) |
		266	+	((divSel / 2U) + 1U) |
	214		-	~SYSCTL_SYSPLLCTL1_PLLCLKEN;
		267	+	SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_LSB;
	215		-
	216		-	//
		268	+	}
	217		-	// Delay of at least 120 OSCCLK cycles required post PLL bypass
		269	+	else
	218		-	//
		270	+	{
	219		-	SysCtl_delay(23U);
	220		-
	221		-	//
	222		-	// Turn off PLL
	223		-	//
	224		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
		271	+	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
	225		-	~SYSCTL_SYSPLLCTL1_PLLEN;
		272	+	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
		273	+	~(SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M |
		274	+	SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_LSB)) |
		275	+	((divSel / 2U) + 1U);
		276	+	}
	226	277
n	227		-	SysCtl_delay(3U);
		278	+	EDIS;
	228	279
n	229		-	//
		280	+	//
	230		-	// Write multiplier, which automatically turns on the PLL
		281	+	// Feed system clock from SYSPLL only if PLL usage is enabled
	231		-	//
		282	+	//
	232		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) |= pllMult;
		283	+	if((config & SYSCTL_PLL_CONFIG_M) == SYSCTL_PLL_ENABLE)
	233		-
	234		-	//
	235		-	// Wait for the SYSPLL lock counter
	236		-	//
	237		-	while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) &
	238		-	SYSCTL_SYSPLLSTS_LOCKS) == 0U)
	239		-	{
		284	+	{
	240		-	;
	241		-	}
	242	285
	243	286		//
	244	287		// Enable PLLSYSCLK is fed from system PLL clock
	245	288		//
		289	+	EALLOW;
	246	290		HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) |=
n	247		-	SYSCTL_SYSPLLCTL1_PLLCLKEN;
		291	+	SYSCTL_SYSPLLCTL1_PLLCLKEN;
	248		-
	249		-	//
		292	+	EDIS;
	250		-	// Delay to ensure system is clocking from PLL prior to
	251		-	// clearing status bit
	252		-	//
	253		-	SysCtl_delay(3U);
	254		-	}
	255	293
n	256		-	//
	257		-	// Backup timer1 and timer2 settings
	258		-	//
	259		-	t1TCR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR);
	260		-	t1PRD = HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD);
	261		-	t1TPR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR);
	262		-	t1TPRH = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH);
	263		-	t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL);
	264		-	t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR);
	265		-	t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD);
	266		-	t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR);
	267		-	t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH);
	268		-
	269		-	//
	270		-	// Set up timers 1 and 2
	271		-	// Configure timer1 to count SYSCLK cycles
	272		-	//
	273		-
	274		-	//
	275		-	// Stop timer 1
	276		-	// Seed timer1 counter
	277		-	// Set sysclock divider
	278		-	// Reload timer with value in PRD
	279		-	// Clear interrupt flag
	280		-	// Enable interrupt
	281		-	//
	282		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
	283		-	HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR1SYSCLKCTR;
	284		-	HWREG(CPUTIMER1_BASE + CPUTIMER_O_TPR) = 0U;
	285		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;
	286		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF;
	287		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE;
	288		-
	289		-	//
	290		-	// Configure timer2 to count Input clock cycles
	291		-	//
	292		-	switch (config & SYSCTL_OSCSRC_M)
	293		-	{
		294	+	}
	294		-	case SYSCTL_OSCSRC_OSC1:
	295		-	//
	296		-	// Clk Src = INT_OSC1
	297		-	//
	298		-	HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &=
	299		-	~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M;
	300		-	HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= 1U;
	301		-	break;
	302	295
n	303		-	case SYSCTL_OSCSRC_OSC2:
	304		-	//
	305		-	// Clk Src = INT_OSC2
	306		-	//
	307		-	HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &=
	308		-	~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M;
	309		-	HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= 2U;
	310		-	break;
	311		-
	312		-	case SYSCTL_OSCSRC_XTAL:
	313		-	//
	314		-	// Clk Src = XTAL
	315		-	//
	316		-	HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &=
	317		-	~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M;
	318		-	HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= 3U;
	319		-	break;
	320		-
	321		-	default:
	322		-	//
	323		-	// Do nothing. Not a valid clock source value.
	324		-	//
	325		-	break;
	326		-	}
		296	+	//
	327		-
		297	+	// ~200 PLLSYSCLK delay to allow voltage regulator to stabilize
	328		-	//
		298	+	// prior to increasing entire system clock frequency.
	329		-	// Clear interrupt flag
	330		-	// Enable interrupt
	331		-	// Stop timer 2
	332		-	// Seed timer2 counter
	333		-	// Set sysclock divider
	334		-	// Reload timer with value in PRD
	335		-	//
	336		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF;
	337		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE;
	338		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
	339		-	HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR2INPCLKCTR;
	340		-	HWREG(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U;
	341		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;
	342		-
	343		-	//
	344		-	// Stop/Start timer counters
	345		-	//
	346		-
	347		-	//
	348		-	// Stop timer 1
	349		-	// Stop timer 2
	350		-	// Reload timer1 with value in PRD
	351		-	// Reload timer2 with value in PRD
	352		-	// Clear timer2 interrupt flag
	353		-	// Start timer2
	354		-	// Start timer1
	355		-	//
	356		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
	357		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
	358		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;
	359		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;
	360		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF;
	361		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS;
	362		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS;
	363		-
	364		-	//
	365		-	// Wait for Timers - Stop if either timer overflows
	366		-	//
	367		-	while(((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &
	368		-	CPUTIMER_TCR_TIF) == 0U)  &&
	369		-	((HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) &
	370		-	CPUTIMER_TCR_TIF) == 0U))
	371		-	{
		299	+	//
	372		-	;
		300	+	SysCtl_delay(40U);
		301	+
	373		-	}
		302	+	//
	374		-
		303	+	// Set the divider to user value
	375		-	//
	376		-	// Stop timer 1 and 2
	377		-	//
	378		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
	379		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
	380		-
	381		-	//
	382		-	// Calculate elapsed counts on timer1
	383		-	//
	384		-	ctr1 = (uint32_t)TMR1SYSCLKCTR - HWREG(CPUTIMER1_BASE +
	385		-	CPUTIMER_O_TIM);
	386		-
	387		-	//
	388		-	// Restore timer settings
	389		-	//
	390		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) = t1TCR;
	391		-	HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = t1PRD;
	392		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR) = t1TPR;
	393		-	HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH) = t1TPRH;
	394		-	HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL;
	395		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR;
	396		-	HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD;
	397		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR;
	398		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH;
	399		-
	400		-	//
	401		-	// Calculate Clock Error:
	402		-	// Error = (mult/div) - (timer1 count/timer2 count)
	403		-	//
	404		-	mult = (float32_t)iMult + ((float32_t)fMult / 4.0F);
	405		-
	406		-	if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & 0x3FU) == 0U)
	407		-	{
		304	+	//
	408		-	div = 1U;
	409		-	}
		305	+	EALLOW;
	410		-	else
		306	+	SysCtl_setPLLSysClk(divSel);
	411		-	{
	412		-	div = (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
	413		-	0x3FU) << 1;
	414		-	}
	415		-
	416		-	sysclkToInClkError = (mult / (float32_t)div) -
	417		-	((float32_t)ctr1 / (float32_t)TMR2INPCLKCTR);
	418		-
	419		-	//
	420		-	// sysclkInvalidFreq will be set to true if sysclkToInClkError is
	421		-	// off by 10%
	422		-	//
	423		-	sysclkInvalidFreq = ((sysclkToInClkError > 0.10F) ||
	424		-	(sysclkToInClkError < -0.10F));
	425		-
	426	307		EDIS;
	427	308		}
n	428		-
	429		-	//
	430		-	// Clear bit
	431		-	//
	432		-	EALLOW;
	433		-	HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) &= ~SYSCTL_SYSDBGCTL_BIT_0;
	434		-	EDIS;
	435		-
	436		-	//
	437		-	// Restore user watchdog, first resetting counter
	438		-	//
	439		-	SysCtl_serviceWatchdog();
	440		-
	441		-	//
	442		-	// Set the KEY bits and make sure not to set the WDOVERRIDE bit
	443		-	//
	444		-	EALLOW;
	445		-	HWREGH(WD_BASE + SYSCTL_O_WDCR) = tempWDCR | SYSCTL_WD_CHKBITS;
	446		-	HWREGH(WD_BASE + SYSCTL_O_WDWCR) = tempWDWCR;
	447		-	HWREGH(WD_BASE + SYSCTL_O_SCSR) = tempSCSR & ~SYSCTL_SCSR_WDOVERRIDE;
	448		-	EDIS;
	449		-
	450		-	//
	451		-	// Restore state of ST1[INTM]. This was set by the
	452		-	// __disable_interrupts() intrinsic previously.
	453		-	//
	454		-	if((intStatus & 0x1U) == 0U)
	455		-	{
		309	+	else
	456		-	EINT;
	457		-	}
		310	+	{
	458		-
		311	+	ESTOP0; // If the frequency is out of range, stop here.
	459		-	//
	460		-	// Restore state of ST1[DBGM]. This was set by the
	461		-	// __disable_interrupts() intrinsic previously.
	462		-	//
	463		-	if((intStatus & 0x2U) == 0U)
	464		-	{
		312	+	}
	465		-	SYSCTL_CLRC_DBGM;
	466		-	}
	467		-
	468		-	//
	469		-	// ~200 PLLSYSCLK delay to allow voltage regulator to stabilize prior
	470		-	// to increasing entire system clock frequency.
	471		-	//
	472		-	SysCtl_delay(40U);
	473		-
	474		-	//
	475		-	// Set the divider to user value
	476		-	//
	477		-	EALLOW;
	478		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
	479		-	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
	480		-	~SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel;
	481		-	EDIS;
	482		-
	483		-	status = true;
	484	313		}
	485	314
	486	315		return(status);
	487	316		}
	488	317

    SysCtl_setAuxClock

    SysCtl_selectXTAL

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	uint16_t t2TCR, t2TPR, t2TPRH, t2CLKCTL;
		2	+	EALLOW;
	3		-	uint32_t t2PRD;
	4	3
	5	4		//
n	6		-	// Backup CPU timer2 settings
		5	+	// Enable XOSC pads initialization and set X1, X2 high
	7	6		//
n	8		-	t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL);
		7	+	HWREGH(CLKCFG_BASE + SYSCTL_O_XTALCR2) |= SYSCTL_XTALCR2_FEN |
	9		-	t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR);
		8	+	SYSCTL_XTALCR2_XIF |
	10		-	t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD);
		9	+	SYSCTL_XTALCR2_XOF;
	11		-	t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR);
		10	+	//
	12		-	t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH);
		11	+	// Wait for few cycles to allow load capacitors to charge
		12	+	//
		13	+	SYSCTL_XTAL_CHARGE_DELAY;
	13	14
	14	15		//
n	15		-	// Backup AUX clock settings
		16	+	// Turn on XTAL and select crystal mode
	16	17		//
n	17		-	uint16_t clksrcctl2 = HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2);
	18		-	uint16_t auxpllctl1 = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1);
	19		-	uint16_t auxclkdivsel = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL);
	20		-
	21		-	//
	22		-	// Set AUX clock source to XTAL, bypass mode.
	23		-	// AUXCLK is used as the CPUTimer Clock source. SYSCLK frequency must be
	24		-	// atleast twice the frequency of AUXCLK. SYSCLK = INTOSC2(10MHz)
	25		-	// Set the AUX divider to 8. The above condition will be met for XTAL
	26		-	// frequencies up to 40MHz
	27		-	//
	28		-	EALLOW;
	29		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) =
	30		-	(HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &
	31		-	~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) |
	32		-	(1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S);
	33		-	HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = 0x0U;
	34		-	HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = SYSCTL_AUXPLLCLK_DIV_8;
	35		-
	36		-
	37		-	//
	38		-	// Disable cpu timer 2 interrupt
	39		-	//
	40		-	CPUTimer_disableInterrupt(CPUTIMER2_BASE);
	41		-
	42		-	//
	43		-	// Stop cpu timer 2 if running
	44		-	//
	45		-	CPUTimer_stopTimer(CPUTIMER2_BASE);
	46		-
	47		-	//
	48		-	// Initialize cpu timer 2 period
	49		-	//
	50		-	CPUTimer_setPeriod(CPUTIMER2_BASE, XTAL_CPUTIMER_PERIOD);
	51		-
	52		-	//
	53		-	// Set cpu timer 2 clock source to XTAL
	54		-	//
	55		-	CPUTimer_selectClockSource(CPUTIMER2_BASE, CPUTIMER_CLOCK_SOURCE_AUX,
	56		-	CPUTIMER_CLOCK_PRESCALER_1);
	57		-
	58		-	//
	59		-	// Clear cpu timer 2 overflow flag
	60		-	//
	61		-	CPUTimer_clearOverflowFlag(CPUTIMER2_BASE);
	62		-
	63		-	//
	64		-	// Start cpu timer 2
	65		-	//
	66		-	CPUTimer_startTimer(CPUTIMER2_BASE);
	67		-
	68		-	EALLOW;
	69		-	//
	70		-	// Turn on XTAL
	71		-	//
	72		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_XTALOFF;
		18	+	HWREGH(CLKCFG_BASE + SYSCTL_O_XTALCR) &= ~SYSCTL_XTALCR_OSCOFF;
		19	+	HWREGH(CLKCFG_BASE + SYSCTL_O_XTALCR) &= ~SYSCTL_XTALCR_SE;
	73	20		EDIS;
	74	21
	75	22		//
n	76		-	// Wait for the X1 clock to overflow cpu timer 2
		23	+	// Wait for the X1 clock to saturate
	77	24		//
n	78		-	SysCtl_pollCpuTimer();
		25	+	SysCtl_pollX1Counter();
	79	26
	80	27		//
	81	28		// Select XTAL as the oscillator source
	82	29		//
	83	30		EALLOW;
	84	31		HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) =
	85	32		((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &
	86	33		(~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) |
	87	34		(SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S));
	88	35		EDIS;
	89	36
	90	37		//
n	91		-	// If a missing clock failure was detected, try waiting for the cpu timer 2
		38	+	// If a missing clock failure was detected, try waiting for the X1 counter
	92		-	// to overflow again.
		39	+	// to saturate again. Consider modifying this code to add a 10ms timeout.
	93	40		//
	94	41		while(SysCtl_isMCDClockFailureDetected())
	95	42		{
	96	43		//
	97	44		// Clear the MCD failure
	98	45		//
	99	46		SysCtl_resetMCD();
	100	47
	101	48		//
n	102		-	// Wait for the X1 clock to overflow cpu timer 2
		49	+	// Wait for the X1 clock to saturate
	103	50		//
n	104		-	SysCtl_pollCpuTimer();
		51	+	SysCtl_pollX1Counter();
	105	52
	106	53		//
	107	54		// Select XTAL as the oscillator source
	108	55		//
	109	56		EALLOW;
	110	57		HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) =
	111	58		((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &
	112	59		(~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) |
	113	60		(SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S));
	114	61		EDIS;
	115	62		}
n	116		-
	117		-	//
	118		-	// Stop cpu timer 2
	119		-	//
	120		-	CPUTimer_stopTimer(CPUTIMER2_BASE);
	121		-
	122		-	//
	123		-	// Restore Timer 2 configuration
	124		-	//
	125		-	EALLOW;
	126		-	HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL;
	127		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR;
	128		-	HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD;
	129		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR;
	130		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH;
	131		-	HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;
	132		-
	133		-	//
	134		-	// Restore AUX clock settings
	135		-	//
	136		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = clksrcctl2;
	137		-	HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = auxpllctl1;
	138		-	HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = auxclkdivsel;
	139		-	EDIS;
	140		-
	141		-	EDIS;
	142	63		}
	143	64

    SysCtl_selectOscSource

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT((oscSource == SYSCTL_OSCSRC_OSC1) ||
	3	3		(oscSource == SYSCTL_OSCSRC_OSC2) ||
		4	+	(oscSource == SYSCTL_OSCSRC_XTAL) ||
	4		-	(oscSource == SYSCTL_OSCSRC_XTAL));
		5	+	(oscSource == SYSCTL_OSCSRC_XTAL_SE));
	5	6
	6	7		//
	7	8		// Select the specified source.
	8	9		//
	9	10		EALLOW;
	10	11		switch(oscSource)
	11	12		{
	12	13		case SYSCTL_OSCSRC_OSC2:
	13	14		//
n	14		-	// Turn on INTOSC2
	15		-	//
	16		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &=
	17		-	~SYSCTL_CLKSRCCTL1_INTOSC2OFF;
	18		-
	19		-	SYSCTL_CLKSRCCTL1_DELAY;
	20		-
	21		-	//
	22	15		// Clk Src = INTOSC2
	23	16		//
	24	17		HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &=
	25	18		~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M;
n	26		-
	27		-	SYSCTL_CLKSRCCTL1_DELAY;
	28		-
	29		-	//
	30		-	// Turn off XTALOSC
	31		-	//
	32		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |=
	33		-	SYSCTL_CLKSRCCTL1_XTALOFF;
	34	19
	35	20		break;
	36	21
	37	22		case SYSCTL_OSCSRC_XTAL:
	38	23		//
	39	24		// Select XTAL in crystal mode and wait for it to power up
	40	25		//
	41	26		SysCtl_selectXTAL();
	42	27		break;
	43	28
		29	+	case SYSCTL_OSCSRC_XTAL_SE:
		30	+	//
		31	+	// Select XTAL in single-ended mode and wait for it to power up
		32	+	//
		33	+	SysCtl_selectXTALSingleEnded();
		34	+	break;
		35	+
	44	36		case SYSCTL_OSCSRC_OSC1:
	45	37		//
	46	38		// Clk Src = INTOSC1
	47	39		//
	48	40		HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) =
	49	41		(HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &
	50	42		~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M) |
	51	43		(SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S);
n	52		-
	53		-	SYSCTL_CLKSRCCTL1_DELAY;
	54		-
	55		-	//
	56		-	//Turn off XTALOSC
	57		-	//
	58		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |=
	59		-	SYSCTL_CLKSRCCTL1_XTALOFF;
	60	44
	61	45		break;
	62	46
	63	47		default:
	64	48		//
	65	49		// Do nothing. Not a valid oscSource value.
	66	50		//
	67	51		break;
	68	52		}
	69	53		EDIS;
	70	54		}
	71	55

    SysCtl_selectOscSourceAuxPLL

    SysCtl_getDeviceParametric

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t value;
	3	3
	4	4		//
	5	5		// Get requested parametric value
	6	6		//
	7	7		switch(parametric)
	8	8		{
	9	9		case SYSCTL_DEVICE_QUAL:
	10	10		//
	11	11		// Qualification Status
	12	12		//
	13	13		value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
	14	14		SYSCTL_PARTIDL_QUAL_M) >> SYSCTL_PARTIDL_QUAL_S);
	15	15		break;
	16	16
	17	17		case SYSCTL_DEVICE_PINCOUNT:
	18	18		//
	19	19		// Pin Count
	20	20		//
	21	21		value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
	22	22		SYSCTL_PARTIDL_PIN_COUNT_M) >>
	23	23		SYSCTL_PARTIDL_PIN_COUNT_S);
	24	24		break;
	25	25
	26	26		case SYSCTL_DEVICE_INSTASPIN:
	27	27		//
	28	28		// InstaSPIN Feature Set
	29	29		//
	30	30		value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
	31	31		SYSCTL_PARTIDL_INSTASPIN_M) >>
	32	32		SYSCTL_PARTIDL_INSTASPIN_S);
n	33		-	break;
	34		-
	35		-	case SYSCTL_DEVICE_FLASH:
	36		-	//
	37		-	// Flash Size (KB)
	38		-	//
	39		-	value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
	40		-	SYSCTL_PARTIDL_FLASH_SIZE_M) >>
	41		-	SYSCTL_PARTIDL_FLASH_SIZE_S);
	42		-	break;
	43		-
	44		-	case SYSCTL_DEVICE_PARTID:
	45		-	//
	46		-	// PARTID Format Revision
	47		-	//
	48		-	value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
	49		-	SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M) >>
	50		-	SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S);
	51	33		break;
	52	34
	53	35		case SYSCTL_DEVICE_FAMILY:
	54	36		//
	55	37		// Device Family
	56	38		//
	57	39		value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) &
	58	40		SYSCTL_PARTIDH_FAMILY_M) >> SYSCTL_PARTIDH_FAMILY_S);
	59	41		break;
	60	42
	61	43		case SYSCTL_DEVICE_PARTNO:
	62	44		//
	63	45		// Part Number
	64	46		//
	65	47		value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) &
	66	48		SYSCTL_PARTIDH_PARTNO_M) >> SYSCTL_PARTIDH_PARTNO_S);
	67	49		break;
	68	50
	69	51		case SYSCTL_DEVICE_CLASSID:
	70	52		//
	71	53		// Class ID
	72	54		//
	73	55		value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) &
	74	56		SYSCTL_PARTIDH_DEVICE_CLASS_ID_M) >>
	75	57		SYSCTL_PARTIDH_DEVICE_CLASS_ID_S);
	76	58		break;
	77	59
	78	60		default:
	79	61		//
	80	62		// Not a valid value for PARTID register
	81	63		//
	82	64		value = 0U;
	83	65		break;
	84	66		}
	85	67
	86	68		return((uint16_t)value);
	87	69		}
	88	70

    SysCtl_deviceCal

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	//
	3		-	// Save the core registers used by Device_cal function in the stack
	4		-	//
	5		-	SYSCTL_DEVICECAL_CONTEXT_SAVE;
	6	2
	7	3		//
	8	4		// Call the Device_cal function
	9	5		//
	10	6		Device_cal();
	11	7
n	12		-	//
	13		-	// Restore the core registers
	14		-	//
	15		-	SYSCTL_DEVICECAL_CONTEXT_RESTORE;
	16	8		}
	17	9

    SysCtl_resetPeripheral

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint16_t regIndex;
	3	3		uint16_t bitIndex;
	4	4
	5	5		//
	6	6		// Decode the peripheral variable.
	7	7		//
	8	8		regIndex = (uint16_t)2U * ((uint16_t)peripheral &
	9	9		(uint16_t)SYSCTL_PERIPH_REG_M);
	10	10		bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >>
	11	11		SYSCTL_PERIPH_BIT_S;
	12	12
	13	13		EALLOW;
	14	14
	15	15		//
	16	16		// Sets the appropriate reset bit and then clears it.
	17	17		//
	18	18		HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) |=  (1UL << bitIndex);
	19	19		HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) &= ~(1UL << bitIndex);
	20	20
	21	21		//
	22	22		// Call Device_cal function
	23	23		//
n	24		-	if((((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0xDU) ||      // ADCx
		24	+	if(((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0xDU)          // ADCx
	25		-	(((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0x10U)        // DACx
	26		-	)
	27	25		{
	28	26		SysCtl_deviceCal();
	29	27		}
	30	28
	31	29		EDIS;
	32	30		}
	33	31

    SysCtl_getResetCause

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t resetCauses;
	3	3
	4	4		//
	5	5		// Read CPU reset register
	6	6		//
	7	7		resetCauses = HWREG(CPUSYS_BASE + SYSCTL_O_RESC) &
	8	8		((uint32_t)SYSCTL_RESC_POR | (uint32_t)SYSCTL_RESC_XRSN |
	9	9		(uint32_t)SYSCTL_RESC_WDRSN |
	10	10		(uint32_t)SYSCTL_RESC_NMIWDRSN |
	11	11		(uint32_t)SYSCTL_RESC_SCCRESETN
		12	+	| (uint32_t)SYSCTL_CAUSE_SIMRESET_CPU1RSN
		13	+	| (uint32_t)SYSCTL_CAUSE_SIMRESET_XRSN
	12	14		);
	13	15
	14	16		//
	15	17		// Set POR and XRS Causes from boot ROM Status
	16	18		//
	17	19		if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_POR) ==
	18	20		(uint32_t)SYSCTL_BOOT_ROM_POR)
	19	21		{
	20	22		resetCauses |= SYSCTL_RESC_POR;
	21	23		}
	22	24		if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_XRS) ==
	23	25		(uint32_t)SYSCTL_BOOT_ROM_XRS)
	24	26		{
	25	27		resetCauses |= SYSCTL_RESC_XRSN;
	26	28		}
	27	29
	28	30		//
	29	31		// Return the reset reasons.
	30	32		//
	31	33		return(resetCauses);
	32	34		}
	33	35

    SysCtl_clearResetCause

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Clear the given reset reasons.
	4	4		//
n	5		-	HWREG(CPUSYS_BASE + SYSCTL_O_RESC) = rstCauses;
		5	+	HWREG(CPUSYS_BASE + SYSCTL_O_RESCCLR) = rstCauses;
	6	6		}
	7	7

    SysCtl_setEPWMClockDivider

    SysCtl_setEMIF1ClockDivider

    SysCtl_setEMIF2ClockDivider

    SysCtl_turnOnOsc

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(
n	3		-	(oscSource == SYSCTL_OSCSRC_OSC2) ||
	4	3		(oscSource == SYSCTL_OSCSRC_XTAL)
	5	4		);
	6	5
	7	6		EALLOW;
	8	7
	9	8		switch(oscSource)
	10	9		{
n	11		-	case SYSCTL_OSCSRC_OSC2:
	12		-	//
	13		-	// Turn on INTOSC2
	14		-	//
	15		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &=
	16		-	~SYSCTL_CLKSRCCTL1_INTOSC2OFF;
	17		-	break;
	18		-
	19	10		case SYSCTL_OSCSRC_XTAL:
	20	11		//
	21	12		// Turn on XTALOSC
	22	13		//
n	23		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &=
		14	+	HWREGH(CLKCFG_BASE + SYSCTL_O_XTALCR) &= ~SYSCTL_XTALCR_OSCOFF;
	24		-	~SYSCTL_CLKSRCCTL1_XTALOFF;
	25	15
	26	16		break;
	27	17
	28	18		default:
	29	19		//
	30	20		// Do nothing. Not a valid oscSource value.
	31	21		//
	32	22		break;
	33	23		}
	34	24
	35	25		EDIS;
	36	26		}
	37	27

    SysCtl_turnOffOsc

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		ASSERT(
n	3		-	(oscSource == SYSCTL_OSCSRC_OSC2) ||
	4	3		(oscSource == SYSCTL_OSCSRC_XTAL)
	5	4		);
	6	5
	7	6		EALLOW;
	8	7
	9	8		switch(oscSource)
	10	9		{
n	11		-	case SYSCTL_OSCSRC_OSC2:
	12		-	//
	13		-	// Turn off INTOSC2
	14		-	//
	15		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |=
	16		-	SYSCTL_CLKSRCCTL1_INTOSC2OFF;
	17		-	break;
	18		-
	19	10		case SYSCTL_OSCSRC_XTAL:
	20	11		//
	21	12		// Turn off XTALOSC
	22	13		//
n	23		-	HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |=
		14	+	HWREGH(CLKCFG_BASE + SYSCTL_O_XTALCR) |= SYSCTL_XTALCR_OSCOFF;
	24		-	SYSCTL_CLKSRCCTL1_XTALOFF;
	25	15		break;
	26	16
	27	17		default:
	28	18		//
	29	19		// Do nothing. Not a valid oscSource value.
	30	20		//
	31	21		break;
	32	22		}
	33	23
	34	24		EDIS;
	35	25		}
	36	26

    SysCtl_enterHaltMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
n	2		-	#if defined(CPU2)
	3		-	EALLOW;
	4		-	//
	5		-	// Configure the device to go into IDLE mode when IDLE is executed.
	6		-	//
	7		-	HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) =
	8		-	(HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) &
	9		-	~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE;
	10		-
	11		-	EDIS;
	12		-	asm(" IDLE");
	13		-
	14		-	#elif defined(CPU1)
	15	2		EALLOW;
	16	3
	17	4		//
	18	5		// Configure the device to go into HALT mode when IDLE is executed.
	19	6		//
	20	7		HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) =
	21	8		(HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) &
	22	9		~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HALT;
	23	10
n	24		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
	25		-	~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN);
	26		-
	27	11		EDIS;
	28	12
	29	13		#ifndef _DUAL_HEADERS
	30	14		IDLE;
	31	15		#else
	32	16		IDLE_ASM;
	33	17		#endif
n	34		-	#endif
	35	18		}
	36	19

    SysCtl_enterHibernateMode

    SysCtl_clearWatchdogResetStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		EALLOW;
	3	3
	4	4		//
	5	5		// Read and return the status of the watchdog reset status flag.
	6	6		//
n	7		-	HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) = SYSCTL_RESC_WDRSN;
		7	+	HWREGH(CPUSYS_BASE + SYSCTL_O_RESCCLR) = SYSCTL_RESCCLR_WDRSN;
	8	8
	9	9		EDIS;
	10	10		}
	11	11

    SysCtl_isNMIFlagSet

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		// Make sure if reserved bits are not set in nmiFlags.
	5	5		//
	6	6		ASSERT((nmiFlags & ~(
n	7		-	SYSCTL_NMI_NMIINT           |
		7	+	SYSCTL_NMI_NMIINT       |
	8		-	SYSCTL_NMI_CLOCKFAIL        |
		8	+	SYSCTL_NMI_CLOCKFAIL    |
	9		-	SYSCTL_NMI_RAMUNCERR        |
		9	+	SYSCTL_NMI_UNCERR       |
	10		-	SYSCTL_NMI_FLUNCERR         |
	11		-	SYSCTL_NMI_CPU1HWBISTERR    |
	12		-	SYSCTL_NMI_CPU2HWBISTERR    |
	13		-	SYSCTL_NMI_PIEVECTERR       |
	14		-	SYSCTL_NMI_CLBNMI           |
	15		-	SYSCTL_NMI_CPU2WDRSN        |
	16		-	SYSCTL_NMI_CPU2NMIWDRSN
		10	+	SYSCTL_NMI_SWERR
	17	11		)) == 0U);
	18	12
	19	13		//
	20	14		// Read the flag register and return true if any of them are set.
	21	15		//
	22	16		return((HWREGH(NMI_BASE + NMI_O_FLG) & nmiFlags) != 0U);
	23	17		}
	24	18

    SysCtl_clearNMIStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		// Make sure if reserved bits are not set in nmiFlags.
	5	5		//
	6	6		ASSERT((nmiFlags & ~(
n	7		-	SYSCTL_NMI_NMIINT           |
		7	+	SYSCTL_NMI_NMIINT       |
	8		-	SYSCTL_NMI_CLOCKFAIL        |
		8	+	SYSCTL_NMI_CLOCKFAIL    |
	9		-	SYSCTL_NMI_RAMUNCERR        |
		9	+	SYSCTL_NMI_UNCERR       |
	10		-	SYSCTL_NMI_FLUNCERR         |
	11		-	SYSCTL_NMI_CPU1HWBISTERR    |
	12		-	SYSCTL_NMI_CPU2HWBISTERR    |
	13		-	SYSCTL_NMI_PIEVECTERR       |
	14		-	SYSCTL_NMI_CLBNMI           |
	15		-	SYSCTL_NMI_CPU2WDRSN        |
	16		-	SYSCTL_NMI_CPU2NMIWDRSN
		10	+	SYSCTL_NMI_SWERR
	17	11		)) == 0U);
	18	12
	19	13		EALLOW;
	20	14
	21	15		//
	22	16		// Clear the individual flags as well as NMI Interrupt flag
	23	17		//
	24	18		HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags;
	25	19		HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT;
	26	20
	27	21		EDIS;
	28	22		}
	29	23

    SysCtl_forceNMIFlags

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		// Make sure if reserved bits are not set in nmiFlags.
	5	5		//
	6	6		ASSERT((nmiFlags & ~(
n	7		-	SYSCTL_NMI_NMIINT           |
		7	+	SYSCTL_NMI_NMIINT       |
	8		-	SYSCTL_NMI_CLOCKFAIL        |
		8	+	SYSCTL_NMI_CLOCKFAIL    |
	9		-	SYSCTL_NMI_RAMUNCERR        |
		9	+	SYSCTL_NMI_UNCERR       |
	10		-	SYSCTL_NMI_FLUNCERR         |
	11		-	SYSCTL_NMI_CPU1HWBISTERR    |
	12		-	SYSCTL_NMI_CPU2HWBISTERR    |
	13		-	SYSCTL_NMI_PIEVECTERR       |
	14		-	SYSCTL_NMI_CLBNMI           |
	15		-	SYSCTL_NMI_CPU2WDRSN        |
	16		-	SYSCTL_NMI_CPU2NMIWDRSN
		10	+	SYSCTL_NMI_SWERR
	17	11		)) == 0U);
	18	12
	19	13		EALLOW;
	20	14
	21	15		//
	22	16		// Set the Flags for the individual interrupts in the NMI flag
	23	17		// force register
	24	18		//
	25	19		HWREGH(NMI_BASE + NMI_O_FLGFRC) |= nmiFlags;
	26	20
	27	21		EDIS;
	28	22		}
	29	23

    SysCtl_isNMIShadowFlagSet

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the arguments.
	4	4		// Make sure if reserved bits are not set in nmiFlags.
	5	5		//
	6	6		ASSERT((nmiFlags & ~(
n	7		-	SYSCTL_NMI_NMIINT           |
		7	+	SYSCTL_NMI_NMIINT       |
	8		-	SYSCTL_NMI_CLOCKFAIL        |
		8	+	SYSCTL_NMI_CLOCKFAIL    |
	9		-	SYSCTL_NMI_RAMUNCERR        |
		9	+	SYSCTL_NMI_UNCERR       |
	10		-	SYSCTL_NMI_FLUNCERR         |
	11		-	SYSCTL_NMI_CPU1HWBISTERR    |
	12		-	SYSCTL_NMI_CPU2HWBISTERR    |
	13		-	SYSCTL_NMI_PIEVECTERR       |
	14		-	SYSCTL_NMI_CLBNMI           |
	15		-	SYSCTL_NMI_CPU2WDRSN        |
	16		-	SYSCTL_NMI_CPU2NMIWDRSN
		10	+	SYSCTL_NMI_SWERR
	17	11		)) == 0U);
	18	12
	19	13		//
	20	14		// Read the flag register and return true if any of them are set.
	21	15		//
	22	16		return((HWREGH(NMI_BASE + NMI_O_SHDFLG) & nmiFlags) != 0U);
	23	17		}
	24	18

    SysCtl_setSyncInputConfig

    SysCtl_selectSecController

    SysCtl_selectCPUForPeripheralInstance

    SysCtl_selectCPUForPeripheral

    SysCtl_lockCPUSelectRegs

    SysCtl_getEfuseError

    SysCtl_setPLLSysClk

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Clears the divider then configures it.
	4	4		//
	5	5		EALLOW;
		6	+	if((divider % 2U) == 1U)
		7	+	{
	6		-	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
		8	+	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
	7		-	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
		9	+	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
	8		-	~(SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)) | divider;
		10	+	~SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) |
		11	+	(divider / 2U) |
		12	+	SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_LSB;
		13	+	}
		14	+	else
		15	+	{
		16	+	HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
		17	+	(HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
		18	+	~(SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M |
		19	+	SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_LSB)) |
		20	+	(divider / 2U);
		21	+	}
	9	22		EDIS;
	10	23		}
	11	24

    SysCtl_setAuxPLLClk

    SysCtl_isPresentUSBPHY

    SysCtl_pollX1Counter

    SysCtl_selectXTALSingleEnded

    SysCtl_isPLLValid

    SysCtl_configureType

    SysCtl_isConfigTypeLocked

    SysCtl_lockClkConfig

    SysCtl_lockSysConfig

    SysCtl_setExternalOscMode

    SysCtl_clearExternalOscCounterValue

    SysCtl_setIntOSC2_Mode

    SysCtl_setWatchdogPredivider

    SysCtl_simulateReset

    SysCtl_getInterruptStatus

    SysCtl_clearInterruptStatus

    SysCtl_setInterruptStatus

    SysCtl_getInterruptStatusMask

    SysCtl_setInterruptStatusMask

    SysCtl_isErrorTriggered

    SysCtl_getErrorPinStatus

    SysCtl_forceError

    SysCtl_clearError

    SysCtl_selectErrPinPolarity

    SysCtl_lockErrControl

    SysCtl_setUserRegister

    SysCtl_getUserRegister

types

upp

usb

xbar

    Enumeration Differences

Type	f2837xd	f280013x	Description
XBAR_CLBMuxConfig	XBAR_CLB_MUX00_CMPSS1_CTRIPH	-	CLB MUX00 CMPSS1 CTRIPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX00_CMPSS1_CTRIPH_OR_L	-	CLB MUX00 CMPSS1 CTRIPH OR L
XBAR_CLBMuxConfig	XBAR_CLB_MUX00_ADCAEVT1	-	CLB MUX00 ADCAEVT1
XBAR_CLBMuxConfig	XBAR_CLB_MUX00_ECAP1_OUT	-	CLB MUX00 ECAP1 OUT
XBAR_CLBMuxConfig	XBAR_CLB_MUX01_CMPSS1_CTRIPL	-	CLB MUX01 CMPSS1 CTRIPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX01_INPUTXBAR1	-	CLB MUX01 INPUTXBAR1
XBAR_CLBMuxConfig	XBAR_CLB_MUX01_CLB1_OUT4	-	CLB MUX01 CLB1 OUT4
XBAR_CLBMuxConfig	XBAR_CLB_MUX01_ADCCEVT1	-	CLB MUX01 ADCCEVT1
XBAR_CLBMuxConfig	XBAR_CLB_MUX02_CMPSS2_CTRIPH	-	CLB MUX02 CMPSS2 CTRIPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX02_CMPSS2_CTRIPH_OR_L	-	CLB MUX02 CMPSS2 CTRIPH OR L
XBAR_CLBMuxConfig	XBAR_CLB_MUX02_ADCAEVT2	-	CLB MUX02 ADCAEVT2
XBAR_CLBMuxConfig	XBAR_CLB_MUX02_ECAP2_OUT	-	CLB MUX02 ECAP2 OUT
XBAR_CLBMuxConfig	XBAR_CLB_MUX03_CMPSS2_CTRIPL	-	CLB MUX03 CMPSS2 CTRIPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX03_INPUTXBAR2	-	CLB MUX03 INPUTXBAR2
XBAR_CLBMuxConfig	XBAR_CLB_MUX03_CLB1_OUT5	-	CLB MUX03 CLB1 OUT5
XBAR_CLBMuxConfig	XBAR_CLB_MUX03_ADCCEVT2	-	CLB MUX03 ADCCEVT2
XBAR_CLBMuxConfig	XBAR_CLB_MUX04_CMPSS3_CTRIPH	-	CLB MUX04 CMPSS3 CTRIPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX04_CMPSS3_CTRIPH_OR_L	-	CLB MUX04 CMPSS3 CTRIPH OR L
XBAR_CLBMuxConfig	XBAR_CLB_MUX04_ADCAEVT3	-	CLB MUX04 ADCAEVT3
XBAR_CLBMuxConfig	XBAR_CLB_MUX04_ECAP3_OUT	-	CLB MUX04 ECAP3 OUT
XBAR_CLBMuxConfig	XBAR_CLB_MUX05_CMPSS3_CTRIPL	-	CLB MUX05 CMPSS3 CTRIPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX05_INPUTXBAR3	-	CLB MUX05 INPUTXBAR3
XBAR_CLBMuxConfig	XBAR_CLB_MUX05_CLB2_OUT4	-	CLB MUX05 CLB2 OUT4
XBAR_CLBMuxConfig	XBAR_CLB_MUX05_ADCCEVT3	-	CLB MUX05 ADCCEVT3
XBAR_CLBMuxConfig	XBAR_CLB_MUX06_CMPSS4_CTRIPH	-	CLB MUX06 CMPSS4 CTRIPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX06_CMPSS4_CTRIPH_OR_L	-	CLB MUX06 CMPSS4 CTRIPH OR L
XBAR_CLBMuxConfig	XBAR_CLB_MUX06_ADCAEVT4	-	CLB MUX06 ADCAEVT4
XBAR_CLBMuxConfig	XBAR_CLB_MUX06_ECAP4_OUT	-	CLB MUX06 ECAP4 OUT
XBAR_CLBMuxConfig	XBAR_CLB_MUX07_CMPSS4_CTRIPL	-	CLB MUX07 CMPSS4 CTRIPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX07_INPUTXBAR4	-	CLB MUX07 INPUTXBAR4
XBAR_CLBMuxConfig	XBAR_CLB_MUX07_CLB2_OUT5	-	CLB MUX07 CLB2 OUT5
XBAR_CLBMuxConfig	XBAR_CLB_MUX07_ADCCEVT4	-	CLB MUX07 ADCCEVT4
XBAR_CLBMuxConfig	XBAR_CLB_MUX08_CMPSS5_CTRIPH	-	CLB MUX08 CMPSS5 CTRIPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX08_CMPSS5_CTRIPH_OR_L	-	CLB MUX08 CMPSS5 CTRIPH OR L
XBAR_CLBMuxConfig	XBAR_CLB_MUX08_ADCBEVT1	-	CLB MUX08 ADCBEVT1
XBAR_CLBMuxConfig	XBAR_CLB_MUX08_ECAP5_OUT	-	CLB MUX08 ECAP5 OUT
XBAR_CLBMuxConfig	XBAR_CLB_MUX09_CMPSS5_CTRIPL	-	CLB MUX09 CMPSS5 CTRIPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX09_INPUTXBAR5	-	CLB MUX09 INPUTXBAR5
XBAR_CLBMuxConfig	XBAR_CLB_MUX09_CLB3_OUT4	-	CLB MUX09 CLB3 OUT4
XBAR_CLBMuxConfig	XBAR_CLB_MUX09_ADCDEVT1	-	CLB MUX09 ADCDEVT1
XBAR_CLBMuxConfig	XBAR_CLB_MUX10_CMPSS6_CTRIPH	-	CLB MUX10 CMPSS6 CTRIPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX10_CMPSS6_CTRIPH_OR_L	-	CLB MUX10 CMPSS6 CTRIPH OR L
XBAR_CLBMuxConfig	XBAR_CLB_MUX10_ADCBEVT2	-	CLB MUX10 ADCBEVT2
XBAR_CLBMuxConfig	XBAR_CLB_MUX10_ECAP6_OUT	-	CLB MUX10 ECAP6 OUT
XBAR_CLBMuxConfig	XBAR_CLB_MUX11_CMPSS6_CTRIPL	-	CLB MUX11 CMPSS6 CTRIPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX11_INPUTXBAR6	-	CLB MUX11 INPUTXBAR6
XBAR_CLBMuxConfig	XBAR_CLB_MUX11_CLB3_OUT5	-	CLB MUX11 CLB3 OUT5
XBAR_CLBMuxConfig	XBAR_CLB_MUX11_ADCDEVT2	-	CLB MUX11 ADCDEVT2
XBAR_CLBMuxConfig	XBAR_CLB_MUX12_CMPSS7_CTRIPH	-	CLB MUX12 CMPSS7 CTRIPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX12_CMPSS7_CTRIPH_OR_L	-	CLB MUX12 CMPSS7 CTRIPH OR L
XBAR_CLBMuxConfig	XBAR_CLB_MUX12_ADCBEVT3	-	CLB MUX12 ADCBEVT3
XBAR_CLBMuxConfig	XBAR_CLB_MUX13_CMPSS7_CTRIPL	-	CLB MUX13 CMPSS7 CTRIPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX13_ADCSOCA	-	CLB MUX13 ADCSOCA
XBAR_CLBMuxConfig	XBAR_CLB_MUX13_CLB4_OUT4	-	CLB MUX13 CLB4 OUT4
XBAR_CLBMuxConfig	XBAR_CLB_MUX13_ADCDEVT3	-	CLB MUX13 ADCDEVT3
XBAR_CLBMuxConfig	XBAR_CLB_MUX14_CMPSS8_CTRIPH	-	CLB MUX14 CMPSS8 CTRIPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX14_CMPSS8_CTRIPH_OR_L	-	CLB MUX14 CMPSS8 CTRIPH OR L
XBAR_CLBMuxConfig	XBAR_CLB_MUX14_ADCBEVT4	-	CLB MUX14 ADCBEVT4
XBAR_CLBMuxConfig	XBAR_CLB_MUX14_EXTSYNCOUT	-	CLB MUX14 EXTSYNCOUT
XBAR_CLBMuxConfig	XBAR_CLB_MUX15_CMPSS8_CTRIPL	-	CLB MUX15 CMPSS8 CTRIPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX15_ADCSOCB	-	CLB MUX15 ADCSOCB
XBAR_CLBMuxConfig	XBAR_CLB_MUX15_CLB4_OUT5	-	CLB MUX15 CLB4 OUT5
XBAR_CLBMuxConfig	XBAR_CLB_MUX15_ADCDEVT4	-	CLB MUX15 ADCDEVT4
XBAR_CLBMuxConfig	XBAR_CLB_MUX16_SD1FLT1_COMPH	-	CLB MUX16 SD1FLT1 COMPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX16_SD1FLT1_COMPH_OR_COMPL	-	CLB MUX16 SD1FLT1 COMPH OR COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX17_SD1FLT1_COMPL	-	CLB MUX17 SD1FLT1 COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX18_SD1FLT2_COMPH	-	CLB MUX18 SD1FLT2 COMPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX18_SD1FLT2_COMPH_OR_COMPL	-	CLB MUX18 SD1FLT2 COMPH OR COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX19_SD1FLT2_COMPL	-	CLB MUX19 SD1FLT2 COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX20_SD1FLT3_COMPH	-	CLB MUX20 SD1FLT3 COMPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX20_SD1FLT3_COMPH_OR_COMPL	-	CLB MUX20 SD1FLT3 COMPH OR COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX21_SD1FLT3_COMPL	-	CLB MUX21 SD1FLT3 COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX22_SD1FLT4_COMPH	-	CLB MUX22 SD1FLT4 COMPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX22_SD1FLT4_COMPH_OR_COMPL	-	CLB MUX22 SD1FLT4 COMPH OR COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX23_SD1FLT4_COMPL	-	CLB MUX23 SD1FLT4 COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX24_SD2FLT1_COMPH	-	CLB MUX24 SD2FLT1 COMPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX24_SD2FLT1_COMPH_OR_COMPL	-	CLB MUX24 SD2FLT1 COMPH OR COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX25_SD2FLT1_COMPL	-	CLB MUX25 SD2FLT1 COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX26_SD2FLT2_COMPH	-	CLB MUX26 SD2FLT2 COMPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX26_SD2FLT2_COMPH_OR_COMPL	-	CLB MUX26 SD2FLT2 COMPH OR COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX27_SD2FLT2_COMPL	-	CLB MUX27 SD2FLT2 COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX28_SD2FLT3_COMPH	-	CLB MUX28 SD2FLT3 COMPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX28_SD2FLT3_COMPH_OR_COMPL	-	CLB MUX28 SD2FLT3 COMPH OR COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX29_SD2FLT3_COMPL	-	CLB MUX29 SD2FLT3 COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX30_SD2FLT4_COMPH	-	CLB MUX30 SD2FLT4 COMPH
XBAR_CLBMuxConfig	XBAR_CLB_MUX30_SD2FLT4_COMPH_OR_COMPL	-	CLB MUX30 SD2FLT4 COMPH OR COMPL
XBAR_CLBMuxConfig	XBAR_CLB_MUX31_SD2FLT4_COMPL	-	CLB MUX31 SD2FLT4 COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX01_CLB1_OUT4	-	EPWM MUX01 CLB1 OUT4
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX03_CLB1_OUT5	-	EPWM MUX03 CLB1 OUT5
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX04_ECAP3_OUT	-	EPWM MUX04 ECAP3 OUT
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX05_CLB2_OUT4	-	EPWM MUX05 CLB2 OUT4
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX06_ECAP4_OUT	-	EPWM MUX06 ECAP4 OUT
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX07_CLB2_OUT5	-	EPWM MUX07 CLB2 OUT5
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX08_CMPSS5_CTRIPH	-	EPWM MUX08 CMPSS5 CTRIPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX08_CMPSS5_CTRIPH_OR_L	-	EPWM MUX08 CMPSS5 CTRIPH OR L
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX08_ADCBEVT1	-	EPWM MUX08 ADCBEVT1
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX08_ECAP5_OUT	-	EPWM MUX08 ECAP5 OUT
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX09_CMPSS5_CTRIPL	-	EPWM MUX09 CMPSS5 CTRIPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX09_CLB3_OUT4	-	EPWM MUX09 CLB3 OUT4
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX09_ADCDEVT1	-	EPWM MUX09 ADCDEVT1
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX10_CMPSS6_CTRIPH	-	EPWM MUX10 CMPSS6 CTRIPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX10_CMPSS6_CTRIPH_OR_L	-	EPWM MUX10 CMPSS6 CTRIPH OR L
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX10_ADCBEVT2	-	EPWM MUX10 ADCBEVT2
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX10_ECAP6_OUT	-	EPWM MUX10 ECAP6 OUT
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX11_CMPSS6_CTRIPL	-	EPWM MUX11 CMPSS6 CTRIPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX11_CLB3_OUT5	-	EPWM MUX11 CLB3 OUT5
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX11_ADCDEVT2	-	EPWM MUX11 ADCDEVT2
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX12_CMPSS7_CTRIPH	-	EPWM MUX12 CMPSS7 CTRIPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX12_CMPSS7_CTRIPH_OR_L	-	EPWM MUX12 CMPSS7 CTRIPH OR L
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX12_ADCBEVT3	-	EPWM MUX12 ADCBEVT3
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX13_CMPSS7_CTRIPL	-	EPWM MUX13 CMPSS7 CTRIPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX13_CLB4_OUT4	-	EPWM MUX13 CLB4 OUT4
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX13_ADCDEVT3	-	EPWM MUX13 ADCDEVT3
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX14_CMPSS8_CTRIPH	-	EPWM MUX14 CMPSS8 CTRIPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX14_CMPSS8_CTRIPH_OR_L	-	EPWM MUX14 CMPSS8 CTRIPH OR L
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX14_ADCBEVT4	-	EPWM MUX14 ADCBEVT4
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX15_CMPSS8_CTRIPL	-	EPWM MUX15 CMPSS8 CTRIPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX15_CLB4_OUT5	-	EPWM MUX15 CLB4 OUT5
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX15_ADCDEVT4	-	EPWM MUX15 ADCDEVT4
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX16_SD1FLT1_COMPH	-	EPWM MUX16 SD1FLT1 COMPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX16_SD1FLT1_COMPH_OR_COMPL	-	EPWM MUX16 SD1FLT1 COMPH OR COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX17_SD1FLT1_COMPL	-	EPWM MUX17 SD1FLT1 COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX18_SD1FLT2_COMPH	-	EPWM MUX18 SD1FLT2 COMPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX18_SD1FLT2_COMPH_OR_COMPL	-	EPWM MUX18 SD1FLT2 COMPH OR COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX19_SD1FLT2_COMPL	-	EPWM MUX19 SD1FLT2 COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX20_SD1FLT3_COMPH	-	EPWM MUX20 SD1FLT3 COMPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX20_SD1FLT3_COMPH_OR_COMPL	-	EPWM MUX20 SD1FLT3 COMPH OR COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX21_SD1FLT3_COMPL	-	EPWM MUX21 SD1FLT3 COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX22_SD1FLT4_COMPH	-	EPWM MUX22 SD1FLT4 COMPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX22_SD1FLT4_COMPH_OR_COMPL	-	EPWM MUX22 SD1FLT4 COMPH OR COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX23_SD1FLT4_COMPL	-	EPWM MUX23 SD1FLT4 COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX24_SD2FLT1_COMPH	-	EPWM MUX24 SD2FLT1 COMPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX24_SD2FLT1_COMPH_OR_COMPL	-	EPWM MUX24 SD2FLT1 COMPH OR COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX25_SD2FLT1_COMPL	-	EPWM MUX25 SD2FLT1 COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX26_SD2FLT2_COMPH	-	EPWM MUX26 SD2FLT2 COMPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX26_SD2FLT2_COMPH_OR_COMPL	-	EPWM MUX26 SD2FLT2 COMPH OR COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX27_SD2FLT2_COMPL	-	EPWM MUX27 SD2FLT2 COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX28_SD2FLT3_COMPH	-	EPWM MUX28 SD2FLT3 COMPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX28_SD2FLT3_COMPH_OR_COMPL	-	EPWM MUX28 SD2FLT3 COMPH OR COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX29_SD2FLT3_COMPL	-	EPWM MUX29 SD2FLT3 COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX30_SD2FLT4_COMPH	-	EPWM MUX30 SD2FLT4 COMPH
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX30_SD2FLT4_COMPH_OR_COMPL	-	EPWM MUX30 SD2FLT4 COMPH OR COMPL
XBAR_EPWMMuxConfig	XBAR_EPWM_MUX31_SD2FLT4_COMPL	-	EPWM MUX31 SD2FLT4 COMPL
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX17_INPUTXBAR7	EPWM MUX17 INPUTXBAR7
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX19_INPUTXBAR8	EPWM MUX19 INPUTXBAR8
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX19_ERRORSTS	EPWM MUX19 ERRORSTS
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX21_INPUTXBAR9	EPWM MUX21 INPUTXBAR9
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX23_INPUTXBAR10	EPWM MUX23 INPUTXBAR10
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX25_INPUTXBAR11	EPWM MUX25 INPUTXBAR11
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX27_INPUTXBAR12	EPWM MUX27 INPUTXBAR12
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX29_INPUTXBAR13	EPWM MUX29 INPUTXBAR13
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX31_ERRORSTS	EPWM MUX31 ERRORSTS
XBAR_EPWMMuxConfig	-	XBAR_EPWM_MUX31_INPUTXBAR14	EPWM MUX31 INPUTXBAR14
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS5_CTRIPL	-	INPUT FLG CMPSS5 CTRIPL
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS5_CTRIPH	-	INPUT FLG CMPSS5 CTRIPH
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS6_CTRIPL	-	INPUT FLG CMPSS6 CTRIPL
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS6_CTRIPH	-	INPUT FLG CMPSS6 CTRIPH
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS7_CTRIPL	-	INPUT FLG CMPSS7 CTRIPL
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS7_CTRIPH	-	INPUT FLG CMPSS7 CTRIPH
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS8_CTRIPL	-	INPUT FLG CMPSS8 CTRIPL
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS8_CTRIPH	-	INPUT FLG CMPSS8 CTRIPH
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS5_CTRIPOUTL	-	INPUT FLG CMPSS5 CTRIPOUTL
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS5_CTRIPOUTH	-	INPUT FLG CMPSS5 CTRIPOUTH
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS6_CTRIPOUTL	-	INPUT FLG CMPSS6 CTRIPOUTL
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS6_CTRIPOUTH	-	INPUT FLG CMPSS6 CTRIPOUTH
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS7_CTRIPOUTL	-	INPUT FLG CMPSS7 CTRIPOUTL
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS7_CTRIPOUTH	-	INPUT FLG CMPSS7 CTRIPOUTH
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS8_CTRIPOUTL	-	INPUT FLG CMPSS8 CTRIPOUTL
XBAR_InputFlag	XBAR_INPUT_FLG_CMPSS8_CTRIPOUTH	-	INPUT FLG CMPSS8 CTRIPOUTH
XBAR_InputFlag	XBAR_INPUT_FLG_CLB1_OUT4	-	INPUT FLG CLB1 OUT4
XBAR_InputFlag	XBAR_INPUT_FLG_CLB1_OUT5	-	INPUT FLG CLB1 OUT5
XBAR_InputFlag	XBAR_INPUT_FLG_CLB2_OUT4	-	INPUT FLG CLB2 OUT4
XBAR_InputFlag	XBAR_INPUT_FLG_CLB2_OUT5	-	INPUT FLG CLB2 OUT5
XBAR_InputFlag	XBAR_INPUT_FLG_CLB3_OUT4	-	INPUT FLG CLB3 OUT4
XBAR_InputFlag	XBAR_INPUT_FLG_CLB3_OUT5	-	INPUT FLG CLB3 OUT5
XBAR_InputFlag	XBAR_INPUT_FLG_CLB4_OUT4	-	INPUT FLG CLB4 OUT4
XBAR_InputFlag	XBAR_INPUT_FLG_CLB4_OUT5	-	INPUT FLG CLB4 OUT5
XBAR_InputFlag	XBAR_INPUT_FLG_ECAP3_OUT	-	INPUT FLG ECAP3 OUT
XBAR_InputFlag	XBAR_INPUT_FLG_ECAP4_OUT	-	INPUT FLG ECAP4 OUT
XBAR_InputFlag	XBAR_INPUT_FLG_ECAP5_OUT	-	INPUT FLG ECAP5 OUT
XBAR_InputFlag	XBAR_INPUT_FLG_ECAP6_OUT	-	INPUT FLG ECAP6 OUT
XBAR_InputFlag	XBAR_INPUT_FLG_ADCBEVT1	-	INPUT FLG ADCBEVT1
XBAR_InputFlag	XBAR_INPUT_FLG_ADCBEVT2	-	INPUT FLG ADCBEVT2
XBAR_InputFlag	XBAR_INPUT_FLG_ADCBEVT3	-	INPUT FLG ADCBEVT3
XBAR_InputFlag	XBAR_INPUT_FLG_ADCBEVT4	-	INPUT FLG ADCBEVT4
XBAR_InputFlag	XBAR_INPUT_FLG_ADCDEVT1	-	INPUT FLG ADCDEVT1
XBAR_InputFlag	XBAR_INPUT_FLG_ADCDEVT2	-	INPUT FLG ADCDEVT2
XBAR_InputFlag	XBAR_INPUT_FLG_ADCDEVT3	-	INPUT FLG ADCDEVT3
XBAR_InputFlag	XBAR_INPUT_FLG_ADCDEVT4	-	INPUT FLG ADCDEVT4
XBAR_InputFlag	XBAR_INPUT_FLG_SD1FLT1_COMPL	-	INPUT FLG SD1FLT1 COMPL
XBAR_InputFlag	XBAR_INPUT_FLG_SD1FLT1_COMPH	-	INPUT FLG SD1FLT1 COMPH
XBAR_InputFlag	XBAR_INPUT_FLG_SD1FLT2_COMPL	-	INPUT FLG SD1FLT2 COMPL
XBAR_InputFlag	XBAR_INPUT_FLG_SD1FLT2_COMPH	-	INPUT FLG SD1FLT2 COMPH
XBAR_InputFlag	XBAR_INPUT_FLG_SD1FLT3_COMPL	-	INPUT FLG SD1FLT3 COMPL
XBAR_InputFlag	XBAR_INPUT_FLG_SD1FLT3_COMPH	-	INPUT FLG SD1FLT3 COMPH
XBAR_InputFlag	XBAR_INPUT_FLG_SD1FLT4_COMPL	-	INPUT FLG SD1FLT4 COMPL
XBAR_InputFlag	XBAR_INPUT_FLG_SD1FLT4_COMPH	-	INPUT FLG SD1FLT4 COMPH
XBAR_InputFlag	XBAR_INPUT_FLG_SD2FLT1_COMPL	-	INPUT FLG SD2FLT1 COMPL
XBAR_InputFlag	XBAR_INPUT_FLG_SD2FLT1_COMPH	-	INPUT FLG SD2FLT1 COMPH
XBAR_InputFlag	XBAR_INPUT_FLG_SD2FLT2_COMPL	-	INPUT FLG SD2FLT2 COMPL
XBAR_InputFlag	XBAR_INPUT_FLG_SD2FLT2_COMPH	-	INPUT FLG SD2FLT2 COMPH
XBAR_InputFlag	XBAR_INPUT_FLG_SD2FLT3_COMPL	-	INPUT FLG SD2FLT3 COMPL
XBAR_InputFlag	XBAR_INPUT_FLG_SD2FLT3_COMPH	-	INPUT FLG SD2FLT3 COMPH
XBAR_InputFlag	XBAR_INPUT_FLG_SD2FLT4_COMPL	-	INPUT FLG SD2FLT4 COMPL
XBAR_InputFlag	XBAR_INPUT_FLG_SD2FLT4_COMPH	-	INPUT FLG SD2FLT4 COMPH
XBAR_InputFlag	-	XBAR_INPUT_FLG_INPUT7	INPUT FLG INPUT7
XBAR_InputFlag	-	XBAR_INPUT_FLG_INPUT8	INPUT FLG INPUT8
XBAR_InputFlag	-	XBAR_INPUT_FLG_INPUT9	INPUT FLG INPUT9
XBAR_InputFlag	-	XBAR_INPUT_FLG_INPUT10	INPUT FLG INPUT10
XBAR_InputFlag	-	XBAR_INPUT_FLG_INPUT11	INPUT FLG INPUT11
XBAR_InputFlag	-	XBAR_INPUT_FLG_INPUT12	INPUT FLG INPUT12
XBAR_InputFlag	-	XBAR_INPUT_FLG_INPUT13	INPUT FLG INPUT13
XBAR_InputFlag	-	XBAR_INPUT_FLG_INPUT14	INPUT FLG INPUT14
XBAR_InputFlag	-	XBAR_INPUT_FLG_ERRORSTS_ERROR	INPUT FLG ERRORSTS ERROR
XBAR_InputNum	-	XBAR_INPUT15	eCAPs
XBAR_InputNum	-	XBAR_INPUT16	eCAPs
XBAR_OutputMuxConfig	XBAR_OUT_MUX01_CLB1_OUT4	-	OUT MUX01 CLB1 OUT4
XBAR_OutputMuxConfig	XBAR_OUT_MUX03_CLB1_OUT5	-	OUT MUX03 CLB1 OUT5
XBAR_OutputMuxConfig	XBAR_OUT_MUX04_ECAP3_OUT	-	OUT MUX04 ECAP3 OUT
XBAR_OutputMuxConfig	XBAR_OUT_MUX05_CLB2_OUT4	-	OUT MUX05 CLB2 OUT4
XBAR_OutputMuxConfig	XBAR_OUT_MUX06_ECAP4_OUT	-	OUT MUX06 ECAP4 OUT
XBAR_OutputMuxConfig	XBAR_OUT_MUX07_CLB2_OUT5	-	OUT MUX07 CLB2 OUT5
XBAR_OutputMuxConfig	XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH	-	OUT MUX08 CMPSS5 CTRIPOUTH
XBAR_OutputMuxConfig	XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH_OR_L	-	OUT MUX08 CMPSS5 CTRIPOUTH OR L
XBAR_OutputMuxConfig	XBAR_OUT_MUX08_ADCBEVT1	-	OUT MUX08 ADCBEVT1
XBAR_OutputMuxConfig	XBAR_OUT_MUX08_ECAP5_OUT	-	OUT MUX08 ECAP5 OUT
XBAR_OutputMuxConfig	XBAR_OUT_MUX09_CMPSS5_CTRIPOUTL	-	OUT MUX09 CMPSS5 CTRIPOUTL
XBAR_OutputMuxConfig	XBAR_OUT_MUX09_CLB3_OUT4	-	OUT MUX09 CLB3 OUT4
XBAR_OutputMuxConfig	XBAR_OUT_MUX09_ADCDEVT1	-	OUT MUX09 ADCDEVT1
XBAR_OutputMuxConfig	XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH	-	OUT MUX10 CMPSS6 CTRIPOUTH
XBAR_OutputMuxConfig	XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH_OR_L	-	OUT MUX10 CMPSS6 CTRIPOUTH OR L
XBAR_OutputMuxConfig	XBAR_OUT_MUX10_ADCBEVT2	-	OUT MUX10 ADCBEVT2
XBAR_OutputMuxConfig	XBAR_OUT_MUX10_ECAP6_OUT	-	OUT MUX10 ECAP6 OUT
XBAR_OutputMuxConfig	XBAR_OUT_MUX11_CMPSS6_CTRIPOUTL	-	OUT MUX11 CMPSS6 CTRIPOUTL
XBAR_OutputMuxConfig	XBAR_OUT_MUX11_CLB3_OUT5	-	OUT MUX11 CLB3 OUT5
XBAR_OutputMuxConfig	XBAR_OUT_MUX11_ADCDEVT2	-	OUT MUX11 ADCDEVT2
XBAR_OutputMuxConfig	XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH	-	OUT MUX12 CMPSS7 CTRIPOUTH
XBAR_OutputMuxConfig	XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH_OR_L	-	OUT MUX12 CMPSS7 CTRIPOUTH OR L
XBAR_OutputMuxConfig	XBAR_OUT_MUX12_ADCBEVT3	-	OUT MUX12 ADCBEVT3
XBAR_OutputMuxConfig	XBAR_OUT_MUX13_CMPSS7_CTRIPOUTL	-	OUT MUX13 CMPSS7 CTRIPOUTL
XBAR_OutputMuxConfig	XBAR_OUT_MUX13_CLB4_OUT4	-	OUT MUX13 CLB4 OUT4
XBAR_OutputMuxConfig	XBAR_OUT_MUX13_ADCDEVT3	-	OUT MUX13 ADCDEVT3
XBAR_OutputMuxConfig	XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH	-	OUT MUX14 CMPSS8 CTRIPOUTH
XBAR_OutputMuxConfig	XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH_OR_L	-	OUT MUX14 CMPSS8 CTRIPOUTH OR L
XBAR_OutputMuxConfig	XBAR_OUT_MUX14_ADCBEVT4	-	OUT MUX14 ADCBEVT4
XBAR_OutputMuxConfig	XBAR_OUT_MUX15_CMPSS8_CTRIPOUTL	-	OUT MUX15 CMPSS8 CTRIPOUTL
XBAR_OutputMuxConfig	XBAR_OUT_MUX15_CLB4_OUT5	-	OUT MUX15 CLB4 OUT5
XBAR_OutputMuxConfig	XBAR_OUT_MUX15_ADCDEVT4	-	OUT MUX15 ADCDEVT4
XBAR_OutputMuxConfig	XBAR_OUT_MUX16_SD1FLT1_COMPH	-	OUT MUX16 SD1FLT1 COMPH
XBAR_OutputMuxConfig	XBAR_OUT_MUX16_SD1FLT1_COMPH_OR_COMPL	-	OUT MUX16 SD1FLT1 COMPH OR COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX17_SD1FLT1_COMPL	-	OUT MUX17 SD1FLT1 COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX18_SD1FLT2_COMPH	-	OUT MUX18 SD1FLT2 COMPH
XBAR_OutputMuxConfig	XBAR_OUT_MUX18_SD1FLT2_COMPH_OR_COMPL	-	OUT MUX18 SD1FLT2 COMPH OR COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX19_SD1FLT2_COMPL	-	OUT MUX19 SD1FLT2 COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX20_SD1FLT3_COMPH	-	OUT MUX20 SD1FLT3 COMPH
XBAR_OutputMuxConfig	XBAR_OUT_MUX20_SD1FLT3_COMPH_OR_COMPL	-	OUT MUX20 SD1FLT3 COMPH OR COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX21_SD1FLT3_COMPL	-	OUT MUX21 SD1FLT3 COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX22_SD1FLT4_COMPH	-	OUT MUX22 SD1FLT4 COMPH
XBAR_OutputMuxConfig	XBAR_OUT_MUX22_SD1FLT4_COMPH_OR_COMPL	-	OUT MUX22 SD1FLT4 COMPH OR COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX23_SD1FLT4_COMPL	-	OUT MUX23 SD1FLT4 COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX24_SD2FLT1_COMPH	-	OUT MUX24 SD2FLT1 COMPH
XBAR_OutputMuxConfig	XBAR_OUT_MUX24_SD2FLT1_COMPH_OR_COMPL	-	OUT MUX24 SD2FLT1 COMPH OR COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX25_SD2FLT1_COMPL	-	OUT MUX25 SD2FLT1 COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX26_SD2FLT2_COMPH	-	OUT MUX26 SD2FLT2 COMPH
XBAR_OutputMuxConfig	XBAR_OUT_MUX26_SD2FLT2_COMPH_OR_COMPL	-	OUT MUX26 SD2FLT2 COMPH OR COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX27_SD2FLT2_COMPL	-	OUT MUX27 SD2FLT2 COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX28_SD2FLT3_COMPH	-	OUT MUX28 SD2FLT3 COMPH
XBAR_OutputMuxConfig	XBAR_OUT_MUX28_SD2FLT3_COMPH_OR_COMPL	-	OUT MUX28 SD2FLT3 COMPH OR COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX29_SD2FLT3_COMPL	-	OUT MUX29 SD2FLT3 COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX30_SD2FLT4_COMPH	-	OUT MUX30 SD2FLT4 COMPH
XBAR_OutputMuxConfig	XBAR_OUT_MUX30_SD2FLT4_COMPH_OR_COMPL	-	OUT MUX30 SD2FLT4 COMPH OR COMPL
XBAR_OutputMuxConfig	XBAR_OUT_MUX31_SD2FLT4_COMPL	-	OUT MUX31 SD2FLT4 COMPL
XBAR_OutputMuxConfig	-	XBAR_OUT_MUX19_ERRSTS	OUT MUX19 ERRSTS
XBAR_OutputMuxConfig	-	XBAR_OUT_MUX30_EPG1_OUT0	OUT MUX30 EPG1 OUT0
XBAR_OutputMuxConfig	-	XBAR_OUT_MUX31_ERRSTS	OUT MUX31 ERRSTS
XBAR_OutputMuxConfig	-	XBAR_OUT_MUX31_EPG1_OUT1	OUT MUX31 EPG1 OUT1

    Register Differences

f2837xd	f280013x	Description
FLG1.CMPSS5_CTRIPL	-	Input Flag for CMPSS5.CTRIPL Signal
FLG1.CMPSS5_CTRIPH	-	Input Flag for CMPSS5.CTRIPH Signal
FLG1.CMPSS6_CTRIPL	-	Input Flag for CMPSS6.CTRIPL Signal
FLG1.CMPSS6_CTRIPH	-	Input Flag for CMPSS6.CTRIPH Signal
FLG1.CMPSS7_CTRIPL	-	Input Flag for CMPSS7.CTRIPL Signal
FLG1.CMPSS7_CTRIPH	-	Input Flag for CMPSS7.CTRIPH Signal
FLG1.CMPSS8_CTRIPL	-	Input Flag for CMPSS8.CTRIPL Signal
FLG1.CMPSS8_CTRIPH	-	Input Flag for CMPSS8.CTRIPH Signal
FLG1.CMPSS5_CTRIPOUTL	-	Input Flag for CMPSS5.CTRIPOUTL Signal
FLG1.CMPSS5_CTRIPOUTH	-	Input Flag for CMPSS5.CTRIPOUTH Signal
FLG1.CMPSS6_CTRIPOUTL	-	Input Flag for CMPSS6.CTRIPOUTL Signal
FLG1.CMPSS6_CTRIPOUTH	-	Input Flag for CMPSS6.CTRIPOUTH Signal
FLG1.CMPSS7_CTRIPOUTL	-	Input Flag for CMPSS7.CTRIPOUTL Signal
FLG1.CMPSS7_CTRIPOUTH	-	Input Flag for CMPSS7.CTRIPOUTH Signal
FLG1.CMPSS8_CTRIPOUTL	-	Input Flag for CMPSS8.CTRIPOUTL Signal
FLG1.CMPSS8_CTRIPOUTH	-	Input Flag for CMPSS8.CTRIPOUTH Signal
FLG2.ADCSOCAO	-	Input Flag for ADCSOCAO Signal
FLG2.ADCSOCBO	-	Input Flag for ADCSOCBO Signal
FLG2.CLB1_OUT4	-	Input Flag for CLB1_OUT4 Signal
FLG2.CLB1_OUT5	-	Input Flag for CLB1_OUT5 Signal
FLG2.CLB2_OUT4	-	Input Flag for CLB2_OUT4 Signal
FLG2.CLB2_OUT5	-	Input Flag for CLB2_OUT5 Signal
FLG2.CLB3_OUT4	-	Input Flag for CLB3_OUT4 Signal
FLG2.CLB3_OUT5	-	Input Flag for CLB3_OUT5 Signal
FLG2.CLB4_OUT4	-	Input Flag for CLB4_OUT4 Signal
FLG2.CLB4_OUT5	-	Input Flag for CLB4_OUT5 Signal
FLG2.ECAP3_OUT	-	Input Flag for ECAP3.OUT Signal
FLG2.ECAP4_OUT	-	Input Flag for ECAP4.OUT Signal
FLG2.ECAP5_OUT	-	Input Flag for ECAP5.OUT Signal
FLG2.ECAP6_OUT	-	Input Flag for ECAP6.OUT Signal
FLG2.ADCBEVT1	-	Input Flag for ADCBEVT1 Signal
FLG2.ADCBEVT2	-	Input Flag for ADCBEVT2 Signal
FLG2.ADCBEVT3	-	Input Flag for ADCBEVT3 Signal
FLG2.ADCBEVT4	-	Input Flag for ADCBEVT4 Signal
FLG3.ADCDEVT1	-	Input Flag for ADCDEVT1 Signal
FLG3.ADCDEVT2	-	Input Flag for ADCDEVT2 Signal
FLG3.ADCDEVT3	-	Input Flag for ADCDEVT3 Signal
FLG3.ADCDEVT4	-	Input Flag for ADCDEVT4 Signal
FLG3.SD1FLT1_COMPL	-	Input Flag for SD1FLT1.COMPL Signal
FLG3.SD1FLT1_COMPH	-	Input Flag for SD1FLT1.COMPH Signal
FLG3.SD1FLT2_COMPL	-	Input Flag for SD1FLT2.COMPL Signal
FLG3.SD1FLT2_COMPH	-	Input Flag for SD1FLT2.COMPH Signal
FLG3.SD1FLT3_COMPL	-	Input Flag for SD1FLT3.COMPL Signal
FLG3.SD1FLT3_COMPH	-	Input Flag for SD1FLT3.COMPH Signal
FLG3.SD1FLT4_COMPL	-	Input Flag for SD1FLT4.COMPL Signal
FLG3.SD1FLT4_COMPH	-	Input Flag for SD1FLT4.COMPH Signal
FLG3.SD2FLT1_COMPL	-	Input Flag for SD2FLT1.COMPL Signal
FLG3.SD2FLT1_COMPH	-	Input Flag for SD2FLT1.COMPH Signal
FLG3.SD2FLT2_COMPL	-	Input Flag for SD2FLT2.COMPL Signal
FLG3.SD2FLT2_COMPH	-	Input Flag for SD2FLT2.COMPH Signal
FLG3.SD2FLT3_COMPL	-	Input Flag for SD2FLT3.COMPL Signal
FLG3.SD2FLT3_COMPH	-	Input Flag for SD2FLT3.COMPH Signal
FLG3.SD2FLT4_COMPL	-	Input Flag for SD2FLT4.COMPL Signal
FLG3.SD2FLT4_COMPH	-	Input Flag for SD2FLT4.COMPH Signal
CLR1.CMPSS5_CTRIPL	-	Input Flag Clear for CMPSS5.CTRIPL Signal
CLR1.CMPSS5_CTRIPH	-	Input Flag Clear for CMPSS5.CTRIPH Signal
CLR1.CMPSS6_CTRIPL	-	Input Flag Clear for CMPSS6.CTRIPL Signal
CLR1.CMPSS6_CTRIPH	-	Input Flag Clear for CMPSS6.CTRIPH Signal
CLR1.CMPSS7_CTRIPL	-	Input Flag Clear for CMPSS7.CTRIPL Signal
CLR1.CMPSS7_CTRIPH	-	Input Flag Clear for CMPSS7.CTRIPH Signal
CLR1.CMPSS8_CTRIPL	-	Input Flag Clear for CMPSS8.CTRIPL Signal
CLR1.CMPSS8_CTRIPH	-	Input Flag Clear for CMPSS8.CTRIPH Signal
CLR1.CMPSS5_CTRIPOUTL	-	Input Flag Clear for CMPSS5.CTRIPOUTL Signal
CLR1.CMPSS5_CTRIPOUTH	-	Input Flag Clear for CMPSS5.CTRIPOUTH Signal
CLR1.CMPSS6_CTRIPOUTL	-	Input Flag Clear for CMPSS6.CTRIPOUTL Signal
CLR1.CMPSS6_CTRIPOUTH	-	Input Flag Clear for CMPSS6.CTRIPOUTH Signal
CLR1.CMPSS7_CTRIPOUTL	-	Input Flag Clear for CMPSS7.CTRIPOUTL Signal
CLR1.CMPSS7_CTRIPOUTH	-	Input Flag Clear for CMPSS7.CTRIPOUTH Signal
CLR1.CMPSS8_CTRIPOUTL	-	Input Flag Clear for CMPSS8.CTRIPOUTL Signal
CLR1.CMPSS8_CTRIPOUTH	-	Input Flag Clear for CMPSS8.CTRIPOUTH Signal
CLR2.ADCSOCAO	-	Input Flag Clear for ADCSOCAO Signal
CLR2.ADCSOCBO	-	Input Flag Clear for ADCSOCBO Signal
CLR2.CLB1_OUT4	-	Input Flag Clear for CLB1_OUT4 Signal
CLR2.CLB1_OUT5	-	Input Flag Clear for CLB1_OUT5 Signal
CLR2.CLB2_OUT4	-	Input Flag Clear for CLB2_OUT4 Signal
CLR2.CLB2_OUT5	-	Input Flag Clear for CLB2_OUT5 Signal
CLR2.CLB3_OUT4	-	Input Flag Clear for CLB3_OUT4 Signal
CLR2.CLB3_OUT5	-	Input Flag Clear for CLB3_OUT5 Signal
CLR2.CLB4_OUT4	-	Input Flag Clear for CLB4_OUT4 Signal
CLR2.CLB4_OUT5	-	Input Flag Clear for CLB4_OUT5 Signal
CLR2.ECAP3_OUT	-	Input Flag Clear for ECAP3.OUT Signal
CLR2.ECAP4_OUT	-	Input Flag Clear for ECAP4.OUT Signal
CLR2.ECAP5_OUT	-	Input Flag Clear for ECAP5.OUT Signal
CLR2.ECAP6_OUT	-	Input Flag Clear for ECAP6.OUT Signal
CLR2.ADCBEVT1	-	Input Flag Clear for ADCBEVT1 Signal
CLR2.ADCBEVT2	-	Input Flag Clear for ADCBEVT2 Signal
CLR2.ADCBEVT3	-	Input Flag Clear for ADCBEVT3 Signal
CLR2.ADCBEVT4	-	Input Flag Clear for ADCBEVT4 Signal
CLR3.ADCDEVT1	-	Input Flag Clear for ADCDEVT1 Signal
CLR3.ADCDEVT2	-	Input Flag Clear for ADCDEVT2 Signal
CLR3.ADCDEVT3	-	Input Flag Clear for ADCDEVT3 Signal
CLR3.ADCDEVT4	-	Input Flag Clear for ADCDEVT4 Signal
CLR3.SD1FLT1_COMPL	-	Input Flag Clear for SD1FLT1.COMPL Signal
CLR3.SD1FLT1_COMPH	-	Input Flag Clear for SD1FLT1.COMPH Signal
CLR3.SD1FLT2_COMPL	-	Input Flag Clear for SD1FLT2.COMPL Signal
CLR3.SD1FLT2_COMPH	-	Input Flag Clear for SD1FLT2.COMPH Signal
CLR3.SD1FLT3_COMPL	-	Input Flag Clear for SD1FLT3.COMPL Signal
CLR3.SD1FLT3_COMPH	-	Input Flag Clear for SD1FLT3.COMPH Signal
CLR3.SD1FLT4_COMPL	-	Input Flag Clear for SD1FLT4.COMPL Signal
CLR3.SD1FLT4_COMPH	-	Input Flag Clear for SD1FLT4.COMPH Signal
CLR3.SD2FLT1_COMPL	-	Input Flag Clear for SD2FLT1.COMPL Signal
CLR3.SD2FLT1_COMPH	-	Input Flag Clear for SD2FLT1.COMPH Signal
CLR3.SD2FLT2_COMPL	-	Input Flag Clear for SD2FLT2.COMPL Signal
CLR3.SD2FLT2_COMPH	-	Input Flag Clear for SD2FLT2.COMPH Signal
CLR3.SD2FLT3_COMPL	-	Input Flag Clear for SD2FLT3.COMPL Signal
CLR3.SD2FLT3_COMPH	-	Input Flag Clear for SD2FLT3.COMPH Signal
CLR3.SD2FLT4_COMPL	-	Input Flag Clear for SD2FLT4.COMPL Signal
CLR3.SD2FLT4_COMPH	-	Input Flag Clear for SD2FLT4.COMPH Signal
-	FLG2.ADCSOCA	Input Flag for ADCSOCA Signal
-	FLG2.ADCSOCB	Input Flag for ADCSOCB Signal
-	FLG2.INPUT7	Input Flag for INPUT7 Signal
-	FLG2.INPUT8	Input Flag for INPUT8 Signal
-	FLG2.INPUT9	Input Flag for INPUT9 Signal
-	FLG2.INPUT10	Input Flag for INPUT10 Signal
-	FLG2.INPUT11	Input Flag for INPUT11 Signal
-	FLG2.INPUT12	Input Flag for INPUT12 Signal
-	FLG2.INPUT13	Input Flag for INPUT13 Signal
-	FLG2.INPUT14	Input Flag for INPUT14 Signal
-	FLG4	X-Bar Input Flag Register 4
-	FLG4.ERRORSTS_ERROR	Input Latch for ERRORSTS_ERROR Signal
-	CLR2.INPUT6	Input Flag Clear for INPUT6 Signal
-	CLR2.ADCSOCA	Input Flag Clear for ADCSOCA Signal
-	CLR2.ADCSOCB	Input Flag Clear for ADCSOCB Signal
-	CLR2.INPUT8	Input Flag Clear for INPUT8 Signal
-	CLR2.INPUT9	Input Flag Clear for INPUT9 Signal
-	CLR2.INPUT10	Input Flag Clear for INPUT10 Signal
-	CLR2.INPUT11	Input Flag Clear for INPUT11 Signal
-	CLR2.INPUT12	Input Flag Clear for INPUT12 Signal
-	CLR2.INPUT13	Input Flag Clear for INPUT13 Signal
-	CLR2.INPUT14	Input Flag Clear for INPUT14 Signal
-	CLR4	X-Bar Input Flag Clear Register 4
-	CLR4.ERRORSTS_ERROR	Input Latch clear for ERRORSTS_ERROR Signal

    XBAR_setOutputMuxConfig

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	//
		3	+	// Check the arguments.
		4	+	//
		5	+	ASSERT(XBAR_isBaseValid(base));
		6	+
	2	7		uint32_t shift;
	3	8		uint16_t offset;
	4	9
	5	10		//
	6	11		// If the configuration is for MUX16-31, we'll need an odd value to index
	7	12		// into the config registers.
	8	13		//
	9	14		if(((uint32_t)muxConfig & 0x2000U) != 0U)
	10	15		{
	11	16		offset = ((uint16_t)output << 1U) + 2U;
	12	17		}
	13	18		else
	14	19		{
	15	20		offset = (uint16_t)output << 1U;
	16	21		}
	17	22
	18	23		//
	19	24		// Extract the shift from the input value.
	20	25		//
	21	26		shift = ((uint32_t)muxConfig >> 8U) & 0x1FU;
	22	27
	23	28		//
	24	29		// Write the requested muxing value for this XBAR output.
	25	30		//
	26	31		EALLOW;
	27	32
n	28		-	HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) =
		33	+	HWREG(base + XBAR_O_OUTPUT1MUX0TO15CFG + offset) =
	29		-	(HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) &
		34	+	(HWREG(base + XBAR_O_OUTPUT1MUX0TO15CFG + offset) &
	30	35		~((uint32_t)0x3U << shift)) |
	31	36		(((uint32_t)muxConfig & 0x3U) << shift);
	32	37
	33	38		EDIS;
	34	39		}
	35	40

    XBAR_setCLBMuxConfig

    XBAR_getInputFlagStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t offset;
	3	3		uint32_t inputMask;
	4	4
	5	5		//
	6	6		// Determine flag register offset.
	7	7		//
	8	8		switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M)
	9	9		{
	10	10		case XBAR_INPUT_FLG_REG_1:
	11	11		offset = XBAR_O_FLG1;
	12	12		break;
	13	13
	14	14		case XBAR_INPUT_FLG_REG_2:
	15	15		offset = XBAR_O_FLG2;
	16	16		break;
	17	17
	18	18		case XBAR_INPUT_FLG_REG_3:
	19	19		offset = XBAR_O_FLG3;
	20	20		break;
	21	21
		22	+	case XBAR_INPUT_FLG_REG_4:
		23	+	offset = XBAR_O_FLG4;
		24	+	break;
		25	+
	22	26		default:
	23	27		//
	24	28		// This should never happen if a valid inputFlag value is used.
	25	29		//
	26	30		offset = 0U;
	27	31		break;
	28	32		}
	29	33
	30	34		//
	31	35		// Get the status of the X-BAR input latch.
	32	36		//
	33	37		inputMask = (uint32_t)1U << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M);
	34	38
	35	39		return((HWREG(XBAR_BASE + offset) & inputMask) != 0U);
	36	40		}
	37	41

    XBAR_clearInputFlag

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		uint32_t offset;
	3	3		uint32_t inputMask;
	4	4
	5	5		//
	6	6		// Determine flag clear register offset.
	7	7		//
	8	8		switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M)
	9	9		{
	10	10		case XBAR_INPUT_FLG_REG_1:
	11	11		offset = XBAR_O_CLR1;
	12	12		break;
	13	13
	14	14		case XBAR_INPUT_FLG_REG_2:
	15	15		offset = XBAR_O_CLR2;
	16	16		break;
	17	17
	18	18		case XBAR_INPUT_FLG_REG_3:
	19	19		offset = XBAR_O_CLR3;
	20	20		break;
	21	21
		22	+	case XBAR_INPUT_FLG_REG_4:
		23	+	offset = XBAR_O_CLR4;
		24	+	break;
		25	+
	22	26		default:
	23	27		//
	24	28		// This should never happen if a valid inputFlag value is used.
	25	29		//
	26	30		offset = 0U;
	27	31		break;
	28	32		}
	29	33
	30	34		//
	31	35		// Set the bit that clears the X-BAR input latch.
	32	36		//
	33	37		inputMask = 1UL << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M);
	34	38		HWREG(XBAR_BASE + offset) = inputMask;
	35	39		}
	36	40

    XBAR_enableOutputMux

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	uint16_t outputNum = (uint16_t)output;
		3	+	//
		4	+	// Check the arguments.
		5	+	//
		6	+	ASSERT(XBAR_isBaseValid(base));
		7	+
	2	8		//
	3	9		// Set the enable bit.
	4	10		//
	5	11		EALLOW;
	6	12
n	7		-	HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) |= muxes;
		13	+	HWREG(OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUXENABLE + (uint16_t)output) |= muxes;
		14	+	HWREG(base + XBAR_O_OUTPUT1MUXENABLE + outputNum) |= muxes;
	8	15
	9	16		EDIS;
	10	17		}
	11	18

    XBAR_disableOutputMux

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	uint16_t outputNum = (uint16_t)output;
		3	+
		4	+	//
		5	+	// Check the arguments.
		6	+	//
		7	+	ASSERT(XBAR_isBaseValid(base));
		8	+
	2	9		//
	3	10		// Clear the enable bit.
	4	11		//
	5	12		EALLOW;
	6	13
n	7		-	HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) &= ~(muxes);
		14	+	HWREG(OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUXENABLE + (uint16_t)output) &= ~(muxes);
		15	+	HWREG(base + XBAR_O_OUTPUT1MUXENABLE + outputNum) &= ~(muxes);
	8	16
	9	17		EDIS;
	10	18		}
	11	19

    XBAR_setOutputLatchMode

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	//
		3	+	// Check the arguments.
		4	+	//
		5	+	ASSERT(XBAR_isBaseValid(base));
		6	+
	2	7		EALLOW;
	3	8
	4	9		//
	5	10		// Set or clear the latch setting bit based on the enable parameter.
	6	11		//
	7	12		if(enable)
	8	13		{
n	9		-	HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) |=
		14	+	HWREGH(base + XBAR_O_OUTPUTLATCHENABLE) |=
	10		-	0x1U << ((uint16_t)output / 2U);
		15	+	0x1U << ((uint16_t)output / 2U);
	11	16		}
	12	17		else
	13	18		{
n	14		-	HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) &=
		19	+	HWREGH(base + XBAR_O_OUTPUTLATCHENABLE) &=
	15		-	~(0x1U << ((uint16_t)output / 2U));
		20	+	~(0x1U << ((uint16_t)output / 2U));
	16	21		}
	17	22
	18	23		EDIS;
	19	24		}
	20	25

    XBAR_getOutputLatchStatus

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	//
		3	+	// Check the arguments.
		4	+	//
		5	+	ASSERT(XBAR_isBaseValid(base));
		6	+
	2	7		//
	3	8		// Get the status of the Output X-BAR output latch.
	4	9		//
n	5		-	return((HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCH) &
		10	+	return((HWREGH(base + XBAR_O_OUTPUTLATCH) &
	6	11		(0x1U << ((uint16_t)output / 2U))) != 0U);
	7	12		}
	8	13

    XBAR_clearOutputLatch

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	//
		3	+	// Check the arguments.
		4	+	//
		5	+	ASSERT(XBAR_isBaseValid(base));
		6	+
	2	7		//
	3	8		// Set the bit that clears the corresponding OUTPUTLATCH bit.
	4	9		//
n	5		-	HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHCLR) |=
		10	+	HWREGH(base + XBAR_O_OUTPUTLATCHCLR) |=
	6	11		0x1U << ((uint16_t)output / 2U);
	7	12		}
	8	13

    XBAR_forceOutputLatch

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	//
		3	+	// Check the arguments.
		4	+	//
		5	+	ASSERT(XBAR_isBaseValid(base));
		6	+
	2	7		//
	3	8		// Set the bit that forces the corresponding OUTPUTLATCH bit.
	4	9		//
n	5		-	HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHFRC) =
		10	+	HWREGH(base + XBAR_O_OUTPUTLATCHFRC) =
	6	11		(uint16_t)0x1U << ((uint16_t)output / 2U);
	7	12		}
	8	13

    XBAR_invertOutputSignal

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	//
		3	+	// Check the arguments.
		4	+	//
		5	+	ASSERT(XBAR_isBaseValid(base));
		6	+
	2	7		//
	3	8		// Set or clear the polarity setting bit based on the invert parameter.
	4	9		//
	5	10		EALLOW;
	6	11
	7	12		if(invert)
	8	13		{
n	9		-	HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) |=
		14	+	HWREGH(base + XBAR_O_OUTPUTINV) |=
	10	15		0x1U << ((uint16_t)output / 2U);
	11	16		}
	12	17		else
	13	18		{
n	14		-	HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) &=
		19	+	HWREGH(base + XBAR_O_OUTPUTINV) &=
	15	20		~(0x1U << ((uint16_t)output / 2U));
	16	21		}
	17	22
	18	23		EDIS;
	19	24		}
	20	25

    XBAR_setInputPin

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
	2	2		//
	3	3		// Check the argument.
	4	4		//
n	5		-	ASSERT(pin <= XBAR_GPIO_MAX_CNT);
		5	+	ASSERT((pin <= XBAR_GPIO_MAX_CNT) ||
		6	+	((pin >= XBAR_NON_GPIO_MIN_CNT) && (pin <= XBAR_NON_GPIO_MAX_CNT)) ||
		7	+	((pin >= XBAR_GPIO_AIO_MIN_CNT) && (pin <= XBAR_GPIO_AIO_MAX_CNT)));
		8	+	ASSERT(XBAR_isBaseValid(base));
	6	9
	7	10		//
	8	11		// Write the requested pin to the appropriate input select register.
	9	12		//
	10	13		EALLOW;
	11	14
		15	+	HWREGH(INPUTXBAR_BASE + XBAR_O_INPUT1SELECT + (uint16_t)input) = pin;
	12		-	HWREGH(XBAR_INPUT_BASE + (uint16_t)input) = pin;
		16	+	HWREGH(base + XBAR_O_INPUT1SELECT + (uint16_t)input) = pin;
	13	17
	14	18		EDIS;
	15	19		}
	16	20

    XBAR_lockInput

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	//
		3	+	// Check the arguments.
		4	+	//
		5	+	ASSERT(XBAR_isBaseValid(base));
		6	+
	2	7		//
	3	8		// lock the input in the INPUTSELECTLOCK register.
	4	9		//
	5	10		EALLOW;
n	6		-	HWREG(INPUTXBAR_BASE + XBAR_O_INPUTSELECTLOCK) =
		11	+	HWREG(base + XBAR_O_INPUTSELECTLOCK) =
	7	12		1UL << (uint16_t)input;
	8	13		EDIS;
	9	14		}
	10	15

    XBAR_lockOutput

C2000Ware 4.03.00.00\f2837xd --> C2000Ware 4.03.00.00\f280013x
f	1	1		{
		2	+	//
		3	+	// Check the arguments.
		4	+	//
		5	+	ASSERT(XBAR_isBaseValid(base));
		6	+
	2	7		//
	3	8		// Lock the Output X-BAR with the OUTPUTLOCK register.
	4	9		// Write key 0x5A5A to the KEY bits and 1 to LOCK bit.
	5	10		//
	6	11		EALLOW;
	7	12
n	8		-	HWREG(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLOCK) =
		13	+	HWREG(base + XBAR_O_OUTPUTLOCK) =
	9		-	((uint32_t)0x5A5A << XBAR_OUTPUTLOCK_KEY_S) |
		14	+	((uint32_t)0x5A5A << XBAR_OUTPUTLOCK_KEY_S) |
	10		-	(uint32_t)XBAR_OUTPUTLOCK_LOCK;
		15	+	(uint32_t)XBAR_OUTPUTLOCK_LOCK;
	11	16
	12	17		EDIS;
	13	18		}
	14	19

    XBAR_enableCLBMux

    XBAR_disableCLBMux

    XBAR_invertCLBSignal

    XBAR_isBaseValid

xint