AM64x/AM62x/AM243x/AM62Ax/AM62Px DDR Register Configuration (v0.10.01)

Introduction

This tool is intended to simplify the process of configuring the DDR Subsystem Controller and PHY to interface to DDR4/LPDDR4 memory devices. The tools consists of a number of parameters to be input by the user (based on the memory device datasheet, board design, and topology), and outputs a file to be used by software to properly initialize and train the selected memory.

Supported Features

• Supported devices: AM64x, AM243x, AM62x, AM62Ax, AM62Px
• DDR Memory Types: LPDDR4 and DDR4 (AM62Ax/AM62Px only support LPDDR4)
• DDR Bus Width: 32bit (AM62Ax/AM62Px only), 16bit
• Single rank or dual rank (AM64x/AM243x only supports single rank)
• Custom IO drive strength and termination
• Configurable timing parameters
• Power of 2 densities (eg, 4Gb, 8Gb, 16Gb, etc.)
• Enables the following training algorithms:
  • CA/CS leveling (LPDDR4 only)
  • Write leveling (DDR4 and LPDDR4)
  • Read Gate Training (DDR4 and LPDDR4)
  • Read Leveling (Read Data Eye Training) (DDR4 and LPDDR4)
  • VREF Training (DDR4 and LPDDR4)
  • Write DQ Leveling (Wrie Data Eye Training) (LPDDR4 only)
• Bit swizzling and byte lane swapping (not on AM64x)

Unsupported Features

• Configuring ECC (This is enabled in the DDRSS wrapper). Please refer to the online documentation for the MCU+ SDK or Linux SDK on your device's product page for more information on enabling DDR ECC
• LPDDR4 frequency set points (FSPs) (only one operating frequency is supported)
• Finite number of memory clock frequencies
• Finite number of memory densities
• Training flexibility (all trainings are enabled by default)

Procedure:

1. Modify parameters based on your DDR device. Hover mouse pointer over each parameter and choose the help icon (?) for more explanation
2. The 'Generated Files' section on the right has output files for your software (uboot, RTOS, or GEL) that can be saved. A SysConfig configuration script can also be saved and then reloaded at a later time using File->Open in Sysconfg.

LPDDR4 Configuration

System Configuration

• Only 1 frequency is supported at this time. FSP0 is the boot frequency and will always be 2x the system input clock frequency
• Ensure to select density per channel in Gbits. If you are using 2 ranks, ensure to include only one channel in one of the ranks. For example, if your device has 16Gb per channel, and you are using 2 ranks, select 16Gb.
• if changing Operating Temperature Range, the derating required for high temperatures will automatically be added to the appropriate parameters. Also, tREFIab, tREFIpb, and tRASmax will be automatically adjusted to based on 4x refresh rate
• Write DBI is enabled by default and cannot be changed. Enabled write DBI will reduce power supply noise and improve signal integrity.

DRAM Timing A)

• Latency parameters will automatically change based on each frequency selected. The user should not have to change these. Note that these will be the latencies associated with Write DBI enabled.

DRAM Timing B)

• Most of these parameters do not change even for a different device, as most timings come from JEDEC spec and are the same across similarly spec'ed devices. These parameters can be checked against your memory device datasheet.
• some parameters have two components (ns and tCK), both of which can be found in your memory device datasheet where appropriate
• Here are some parameters to double check:
  • tFAW, tCKE
  • tREFIab and tREFIpb, these will change depending on your operating temperature
  • tRFCab, tRFCpb, these will change with device density

IO Control A)

• These are parameters for the processor DDR controller and PHY DDR IO configuration and contain Reference Voltage (VREF), Drive Strength, and On-Die Termination settings. Default values are for the associated EVM. Typically ideal values would be derived from board simulations. Consult the DDR Design and Layout Guidelines app note on the ti.com product page for your specific device for information on board simulations.
• VREF control
  • VREF control parameters impact the reference voltage used for inputs on the processor data signals (DQ, DM, DQS) during read cycles.
  • VREF Range and Control values would typically be left at the default values. VREF values will eventually get trained to an optimial value during DDR initialization
• Drive Strength
  • Drive strength parameters impact voltage swing and signal integrity of the processor data signals (during writes) and Ctrl/Addr signals
  • Driver Pull-Up DQ/DM/DQS: this is drive strength (during writes) for the processor data signals. Only one value for all data signals (DQ, DM, and DQS)
  • Driver Pull-Up CA: this is drive strength for the processor's Ctrl/Addr bus
  • Driver Pull-Up CSn: this is drive strength for the processor's CSn signal(s)
  • Driver Pull-Down: this is drive strength for the processor, and should be equivalent to the Pull-Up setting for the corresponding signals
• On Die Termination
  • Termination parameters impact voltage swing and signal integrity of the processor data signals during reads.
  • ODT Pull-Up: ODT pull up for LPDDR4 is disabled with Hi-Z
  • ODT Pull Down DQ/DM/DQS: this is the processor's termination impedance (during reads) for data signals

IO Control B)

• These are parameters for the memory device IO configuration and contain Reference Voltage (VREF), Drive Strength, and On-Die Termination settings. Default values are for the associated EVM. Typically ideal values would be derived from board simulations. Consult the DDR Design and Layout Guidelines app note on the ti.com product page for your specific device for information on board simulations.
• VREF control
  • VREF control should mostly remain unchanged. These are initial values of VREF for data (MR14) and ctrl/addr (MR12) for each frequency set point, but will eventually be training during initialization.
• Drive Strength
  • Drive Strength Pull-Down: this is the drive strength setting (during reads) for Data signals (MR3) for each frequency set point
  • Drive Stength Pull Up: defines the target VOH during read cycles (MR3)and should remain at VDDQ/3
• On-Die Termination
  • CA ODT Disable: This parameter is defined in MR22 of the LPDDR4 memory. When this parameter is set to "Disable", the termination of the command / address pins are disabled regardless of how the termination is configured in MR11 or the state of the DT_CA pin. When this parameter is set to "ODT_CA Bond Pad", the termination of the command / address pins are configured based on the MR11 configuration along with the ODT_CA pin. It is recommended to leave this parameter set to the default, "ODT_CA Bond Pad".
  • CK ODT Override: This parameter is defined in MR22 of the LPDDR4 memory. When set to "Enable", the clock termination is determined by the MR11 configuration regardless of the ODT_CA pin. This parameter is used to enable termination on the clock when the CA bus is shared between two ranks, but the clock is not. Because Sitara processors share both the CA bus and clock between ranks, it is recommended to leave this parameter set to the default, "Disable".
  • CS ODT Override: This parameter is defined in MR22 of the LPDDR4 memory. When set to "Enable", the chip select termination is determined by the MR11 configuration regardless of the ODT_CA pin. This parameter is used to enable termination on the chip select pin when the CA bus is shared between two ranks, but the chip select is not. Because Sitara processors share the CA bus between ranks but have unique chip select signals, it is recommended to leave this parameter set to the default, "Enable".
  • CA ODT: This parameter is defined in MR11 of the LPDDR4 memory and defines the termination of the command / address pins of the LPDDR4 memory. The appropriate value is typically a result of board simulations.
  • DQ ODT: This parameter is defined in MR11 of the LPDDR4 memory and defines the termination of the data (DQ), data mask (DM), and strobe (DQS) pins of the LPDDR4 memory during write cycles. The appropriate value is typically a result of board simulations
  • SOC ODT: This parameter is defined in MR22 of the LPDDR4 memory and defines the termination of the processor / DDR controller. This parameter must be configured to match the termination as defined in ODT Pull-Down in IO Control A)

GEL

The resulting .gel file should be placed in the CCS installation for your device, for example ccs\ccs_base\emulation\gel\AM64x\AM64_DDRSS, and loaded using a GEL_LoadGEL instruction (see example in ccs\ccs_base\emulation\gel\AM64x\AM64_DDRSS\AM64x_GP_EVM.gel)

CMM

The resulting .cmm file should be placed in the Lautherbach installation for your device.

Linux u-boot

The resulting .dtsi file should be placed in arch/arm/dts, and the include statement in k3-\<device\>-r5-\<board\>.dts (eg., k3-am642-r5-evm.dts for the AM64x GP EVM, or k3-am642-r5-sk.dts for the AM64x SK EVM) should reference the new .dtsi file. The DDR driver will properly set the DDR frequency and initialize the DDR controller using the information in this .dtsi file

MCU+ SDK (RTOS)

The resulting .h file should be placed in mcu_plus_sdk_\<device\>\_\<version\>\source\drivers\ddr\v0\soc\<device> and included by using the SysConfig for SDK tool when building your code. Please refer to the SDK API Guide mcu_plus_sdk_\<device\>_\<version\>\docs\api_guide_am64x\DRIVERS_DDR_PAGE.html for more information

Desktop Version

For computers without internet access, the DDR Register Configuration tool can be downloaded and installed on your local workstation by following these instructions:

• Install SysConfig

  • Download the latest Sysconfig from https://www.ti.com/tool/SYSCONFIG
  • Run the installer and install to c:\ti for windows or ~/ti for linux

• Install the DDR RegConfig Tool:

  • Open Resource Explorer at https://dev.ti.com/tirex/explore
  • Select the menu (icon with 3 horizontal lines) in the upper right and choose Package Manager
  • Scroll until you see DDR Subsystem Register Configuration
  • Select More and choose the latest version to download
  • You should now have a zip file Processor_DDR_Config_\<version\>_all.zip Extract the zip to c:\ti for windows or ~/ti for linux.

• Run the tool with the following command after substituting for:

  • The SysConfig version,
  • The Processor_DDR_Config version, and
  • The device name if needed (either AM64x, AM62x, AM62Ax, AM62Px)

Windows command example:

c:\ti\sysconfig_<version>\sysconfig_gui.bat --product c:\ti\Processor_DDR_Config_<version>\.metadata\product.json --device AM62x

Linux command example:

~/ti/sysconfig_<version>/sysconfig_gui.sh --product ~/ti/Processor_DDR_Config_<version>/.metadata/product.json --device AM62x

Revision History

v0.8.10: initial stable version.
Changes from previous versions include:

• added read/write DBI selection for LPDDR4/DDR4. Default to enable write DBI for LPDDR4, read DBI for DDR4 to improve power supply noise and improve overall signal integrity
• changed default value of CA ODT to 60ohm for both LPDDR4 and DDR4
• updated RTOS output to fix #ifdef
• periodic write DQ leveling disabled to improve realtime performance
• disabled "always-on" mode of the input enables for data bytes for power optimization
• disabled VREF controller for addr/cmd signals for power optimization

v0.8.40: provides improved operation at 1600MTs for both LPDDR4 and DDR4.
Changes from previous version include:

• changed default value CTRLUPD_AREF_HP_ENABLE=0
• changed default value LPI_WAKEUP_EN=0
• changed cal_clk divider and PVT calibration interval. This change provides significant stability improvements for LPDDR4 and DDR4 operation at 1600MTs
• fixed TOSCO_F0 calculation for LPDDR4

v0.8.80: added support for AM62x release. Added support for high temp operation.
Other misc fixes to align with documentation:

• CTL_165[11]=1 (LPI_WAKEUP_EN) only applicable for AM62x
• CTL_321[23:8] = 0xFFFF (CS_MSK_1) corrected value when rank 1 disabled

v0.9.04:

• changed wrlvl_delay_early_threshold=0x100 to allow write leveling to complete successfully for wider array of layouts
• add cmm output
• LPDDR4: `phyrddqslatency_adjust changed to 0 default recommendation (this value gets optimized during training)
• LPDDR4: optimized training loops to support 1 operating frequency
• LPDDR4/DDR4: optimized IO calibration configuration based on operating frequency
• LPDDR4/DDR4: optimized internal calibration clock based on operating frequency
• LPDDR4: changed default MR22 ODTE-CS=1
• LPDDR4: changed rx_ctle_cs default to No Boost
• AM62x dual rank support
• updated to use sysconfig v1.15
• public release for AM62A LPDDR4 support

v0.9.05:

• cleaned up supported frequencies

v0.9.08

• added automatic change of RL, WL and nWR when frequency is changed
• added DQ swizzle and byte swap configuration flexibilty for AM62x/AM62A LPDDR4
• PHY_CAL_CLK updated divider values for higher frequencies
• CS ODT fix bug introduced in previous release

v0.9.09

• added LPDDR4 description in README
• added instructions for offline support in README
• added 1200MHz use case for AM62A
• added auto adjustments of tRAS and tREFI with change in temp selection
• updated changes to latency parameters when frequency changes
• changed CS_MAP parameters to support 16-bit in AM62A
• rx_pclk_clk_sel update
• added WDQ leveling configuration selection

v0.9.10

• added AM62Px LPDDR4 support
• added support for swizzle of DMIx along with DQx (AM62x/AM62A/AM62P)
• allow for direct input of operating frequency in LPDDR4
• adjusted RST_DRIVE during initialization

v0.10.01

• new cosmetic changes: including being able to choose reference design as starting point
• added support for "Set B" write latencies in LPDDR4
• updated ODTon/off values per freq
• added support for enabling periodic ZQ Calibration in LPDDR4 memories (only 256ms period)
• added support for separate CK drive setting in LPDDR4
• allow for direct input of operating frequency in DDR4. Added warning and error checking
• updated DFI timings for AM62Ax and AM62Px
• added SDRAM_IDX parameter to properly set Subsystem register
• changed tool version in README from xx.xx to x.xx.xx (was missing leading revision)