AM64x/AM625/AM623/AM243x/AM62Ax/AM62Px DDR Register Configuration (v0.10.02)

Introduction

This tool is intended to simplify the process of configuring the DDR Subsystem Controller and PHY to interface to DDR4/LPDDR4 memory devices. The tools consists of a number of parameters to be input by the user (based on the memory device datasheet, board design, and topology), and outputs a file to be used by software to properly initialize and train the selected memory.

Supported Features

• Supported devices: AM64x, AM243x, AM625/AM623, AM62Ax, AM62Px
• DDR Memory Types: LPDDR4 and DDR4 (AM62Ax/AM62Px only support LPDDR4)
• DDR Bus Width: 32bit (AM62Ax/AM62Px only), 16bit
• Single rank or dual rank (AM64x/AM243x only supports single rank)
• Custom IO drive strength and termination
• Configurable timing parameters
• Power of 2 densities (eg, 4Gb, 8Gb, 16Gb, etc.)
• Enables the following training algorithms:
  • CA/CS leveling (LPDDR4 only)
  • Write leveling (DDR4 and LPDDR4)
  • Read Gate Training (DDR4 and LPDDR4)
  • Read Leveling (Read Data Eye Training) (DDR4 and LPDDR4)
  • VREF Training (DDR4 and LPDDR4)
  • Write DQ Leveling (Wrie Data Eye Training) (LPDDR4 only)
• Bit swizzling and byte lane swapping (not on AM64x)

Unsupported Features

• Configuring ECC (This is enabled in the DDRSS wrapper). Please refer to the online documentation for the MCU+ SDK or Linux SDK on your device's product page for more information on enabling DDR ECC
• LPDDR4 frequency set points (FSPs) (only one operating frequency is supported)
• Finite number of memory densities (only memory densities listed in the drop down menu are supported)
• Training flexibility (all trainings are enabled by default)

Procedure:

1. Modify parameters based on your DDR device. Hover mouse pointer over each parameter and choose the help icon (?) for more explanation
2. The 'Generated Files' section on the right has output files for your software (uboot, RTOS, or GEL) that can be saved. A SysConfig configuration script can also be saved and then reloaded at a later time using File->Open in Sysconfg.

The configurations for the various EVMs can be chosen using the Reference Design selection.

LPDDR4 Configuration

System Configuration

• Only 1 operating frequency is supported at this time. FSP0 is the boot frequency and will always be 2x the system input clock frequency. Inputs will be limited based on device, and a warning/error will be displayed when frequency is out of range. Check Sitara device datasheet for maximum frequency supported. Some flexibility is given to set a frequency higher than what is supported, this is only for test purposed (a warning will be displayed).
• Ensure to select density per channel in Gbits. If you are using 2 ranks, ensure to include only one channel in one of the ranks. For example, if your device has 16Gb per channel, and you are using 2 ranks, select 16Gb.
• if changing Operating Temperature Range, the derating required for high temperatures will automatically be added to the appropriate parameters (tDQSCK, tRCD, tRC, tRAS, tRP). Also, tREFI, tREFIpb, and tRASmax will be automatically adjusted to based on 4x refresh rate
• Write DBI is enabled by default and cannot be changed. Enabled write DBI will reduce power supply noise and improve signal integrity.
• Enable Periodic ZQ calibration in the memory if your system requires it. Some memory vendors may require this to be enabled for certain applications.
• Enable WDQS Extension to enable Mode 1 Read Based Control (see LPDDR4 JEDEC spec or DDR datasheet for more information). For Nanya and ISSI memories, this must be enabled.

DRAM Timing A)

• Latency parameters will automatically change based on each frequency selected. The user should not have to change these. Note that these will be the latencies associated with Write DBI enabled.
• Double check ODTLon and ODTLoff values in your datasheet. These values may need to change based on operating frequency.

DRAM Timing B)

• Most of these parameters do not change even for a different device, as most timings come from JEDEC spec and are the same across similarly spec'ed devices. These parameters should be checked against your memory device datasheet.
• some parameters have two components (ns and tCK), both of which can be found in your memory device datasheet where appropriate. Just enter these as shown in the datasheet, the tool will make the appropriate calculations to meet the min/max timing specifications.
• Here are some parameters to double check:
  • tFAW, tCKE
  • tREFIab and tREFIpb, these will change depending on your operating temperature
  • tRFCab, tRFCpb, these will change with device density
• Hover over the '?' next to each parameter for futher information

IO Control A)

• These are parameters for the processor DDR controller and PHY DDR IO configuration and contain Reference Voltage (VREF), Drive Strength, and On-Die Termination settings. Default values are for the associated EVM. Typically ideal values would be derived from board simulations. Consult the DDR Design and Layout Guidelines app note on the ti.com product page for your specific device for information on board simulations.
• VREF control
  • VREF control parameters impact the reference voltage used for inputs on the processor data signals (DQ, DM, DQS) during read cycles.
  • VREF Range and Control values would typically be left at the default values. VREF values will eventually get trained to an optimial value during DDR initialization
• Drive Strength
  • Drive strength parameters impact voltage swing and signal integrity of the processor data signals (during writes) and Ctrl/Addr signals
  • Driver Pull-Up DQ/DM/DQS: this is drive strength (during writes) for the processor data signals. Only one value for all data signals (DQ, DM, and DQS)
  • Driver Pull-Up CA: this is drive strength for the processor's Ctrl/Addr bus
  • Driver Pull-Up CSn: this is drive strength for the processor's CSn signal(s)
  • Driver Pull-Up CK: this is drive strength for the processor's CK signal(s)
  • Driver Pull-Down: this is drive strength for the processor, and should be equivalent to the Pull-Up setting for the corresponding signals
• On Die Termination
  • Termination parameters impact voltage swing and signal integrity of the processor data signals during reads.
  • ODT Pull-Up: ODT pull up for LPDDR4 is disabled with Hi-Z
  • ODT Pull Down DQ/DM/DQS: this is the processor's termination impedance (during reads) for data signals

IO Control B)

• These are parameters for the memory device IO configuration and contain Reference Voltage (VREF), Drive Strength, and On-Die Termination settings. Default values are for the associated EVM. Typically ideal values would be derived from board simulations. Consult the DDR Design and Layout Guidelines app note on the ti.com product page for your specific device for information on board simulations.
• VREF control
  • VREF control should mostly remain unchanged. These are initial values of VREF for data (MR14) and ctrl/addr (MR12) for each frequency set point, but will eventually be training during initialization.
• Drive Strength
  • Drive Strength Pull-Down: this is the drive strength setting (during reads) for Data signals (MR3) for each frequency set point
  • Drive Stength Pull Up: defines the target VOH during read cycles (MR3)and should remain at VDDQ/3
• On-Die Termination
  • CA ODT Disable: This parameter is defined in MR22 of the LPDDR4 memory. When this parameter is set to "Disable", the termination of the command / address pins are disabled regardless of how the termination is configured in MR11 or the state of the ODT_CA pin. When this parameter is set to "ODT_CA Bond Pad", the termination of the command / address pins are configured based on the MR11 configuration along with the ODT_CA pin. It is recommended to leave this parameter set to the default, "ODT_CA Bond Pad".
  • CK ODT Override: This parameter is defined in MR22 of the LPDDR4 memory. When set to "Enable", the clock termination is determined by the MR11 configuration regardless of the ODT_CA pin. This parameter is used to enable termination on the clock when the CA bus is shared between two ranks, but the clock is not. Because Sitara processors share both the CA bus and clock between ranks, it is recommended to leave this parameter set to the default, "Disable".
  • CS ODT Override: This parameter is defined in MR22 of the LPDDR4 memory. When set to "Enable", the chip select termination is determined by the MR11 configuration regardless of the ODT_CA pin. This parameter is used to enable termination on the chip select pin when the CA bus is shared between two ranks, but the chip select is not. Because Sitara processors share the CA bus between ranks but have unique chip select signals, it is recommended to leave this parameter set to the default, "Enable".
  • CA ODT: This parameter is defined in MR11 of the LPDDR4 memory and defines the termination of the command / address pins of the LPDDR4 memory. The appropriate value is typically a result of board simulations.
  • DQ ODT: This parameter is defined in MR11 of the LPDDR4 memory and defines the termination of the data (DQ), data mask (DM), and strobe (DQS) pins of the LPDDR4 memory during write cycles. The appropriate value is typically a result of board simulations
  • SOC ODT: This parameter is defined in MR22 of the LPDDR4 memory and defines the termination of the processor / DDR controller. This parameter must be configured to match the termination as defined in ODT Pull-Down in IO Control A)

DDR4 Configuration

System Configuration

• Input operating frequency in Memory Frequency. Inputs will be limited based on device, and a warning/error will be displayed when frequency is out of range. Check Sitara device datasheet for maximum frequency supported. Some flexibility is given to set a frequency higher than what is supported, this is only for test purposed (a warning will be displayed)
• Ensure to enter the Data Bus Width per device. In this case, a device may be a die if you have a multi-die package. For example, if you have a dual-die package with two x8 dies, then enter 8, since each "device" is 8-bit wide.
• Ensure to select density per device in Gbits. In this case, a device may be a die if you have a multi-die package. For example, if you are using a dual-die package which contains two x8 dies, then choose the density for one of the die.
• if changing Operating Temperature Range, the derating required for high temperatures will automatically be added to the appropriate parameters. Also, tREFIab, tREFIpb, and tRASmax will be automatically adjusted to based on 4x refresh rate
• Read DBI is enabled by default and cannot be changed. Enabled read DBI will reduce power supply noise and improve signal integrity.
• LPASR mode enables Low Power Auto Self Refresh mode in MR2 requiring self-refresh over different temperature ranges. Please see your DDR datasheet for more information. Note, this changes when the Operating Temperature Range parameter changes, but can be separately adjusted using the drop down menu.
• TCR mode enabled Temperature Controlled Refresh mode in MR4. Please see your DDR datasheet for more information.
• TCR range controls the temp range for TCR mode. Please see your DDR datasheet for more information. Note, this changes when the Operating Temperature Range parameter change, but can be separately adjusted using the drop down menu.

DRAM Timing A)

• Set the Latency parameters based on the speed bin tables in the datasheet. Ensure you choose the correct table based on the speed grade of your device. Then, select the CL and CWL according to your operating frequency. Choose the CL for a valid operating frequency (some device variants may have certain operating frequencies reserved). Some operating frequencies support multiple CWL, and you should be able to choose either value.

DRAM Timing B)

• Most of these parameters do not change even for a different device, as most timings come from JEDEC spec and are the same across similarly spec'ed devices. These parameters should be checked against your memory device datasheet.
• Some parameters have two components (ns and tCK), both of which can be found in your memory device datasheet where appropriate. Just enter these as shown in the datasheet, the tool will make the appropriate calculations to meet the min/max timing specifications.
• Here are some parameters to double check:
  • tFAW, tCKE
  • tREFI will change depending on your operating temperature
  • tRFC will change with device density
• Hover over the '?' next to each parameter for futher information

IO Control A)

• These are parameters for the processor DDR controller and PHY DDR IO configuration and contain Reference Voltage (VREF), Drive Strength, and On-Die Termination settings. Default values for the EVMs can be chosen using Reference Design setting at the top of the page. Typically ideal values would be derived from board simulations. Consult the DDR Design and Layout Guidelines app note on the ti.com product page for your specific device for information on board simulations.
• VREF control
  • VREF control parameters impact the reference voltage used for inputs on the processor data signals (DQ, DM, DQS) during read cycles.
  • VREF Range and Control values would typically be left at the default values. VREF values will eventually get trained to an optimial value during DDR initialization
• Drive Strength
  • Drive Impedance parameters impact voltage swing and signal integrity of the processor data signals (during writes) and Ctrl/Addr signals
  • Driver Impedance for DQ/DQS/DM: this is drive strength (during writes) for the processor data signals. Only one value for all data signals (DQ, DM, and DQS)
  • Driver Impedance for Addr/Ctrl/Clk: this is drive strength for the processor's Addr/Ctrl/Clk signals
• On Die Termination
  • Termination parameters impact voltage swing and signal integrity of the processor data signals during reads.
  • ODT for DQ/DQS/DM: this is the processor's termination impedance (during read) for data signals

IO Control B)

• These are parameters for the memory device IO configuration and contain Reference Voltage (VREF), Drive Strength, and On-Die Termination settings. Default values for the EVMs can be chosen using Reference Design setting at the top of the page. Typically ideal values would be derived from board simulations. Consult the DDR Design and Layout Guidelines app note on the ti.com product page for your specific device for information on board simulations.
• VREF control
  • VREF control should mostly remain unchanged. These are initial range and value of VREF for data (MR6), but will eventually be training during initialization.
• Drive Strength
  • Output Driver Impedance (ODI): this is the drive strength setting (during reads) for Data signals (MR1)
• On-Die Termination
  • Nominal ODT (RttNOM): Data bus ODT setting (during writes) in the memory. This gets set in MR1.
  • Dynamic ODT: Sets the dynamic ODT setting in the memory. This gets set in MR2.

GEL

The resulting .gel file should be placed in the CCS installation for your device, for example ccs\ccs_base\emulation\gel\AM64x\AM64_DDRSS, and loaded using a GEL_LoadGEL instruction (see example in ccs\ccs_base\emulation\gel\AM64x\AM64_DDRSS\AM64x_GP_EVM.gel)

CMM

The resulting .cmm file should be placed in the Lauterbach installation for your device.

Linux u-boot

The resulting .dtsi file should be placed in arch\arm\dts, and the include statement in k3-\<device\>-r5-\<board\>.dts (eg., k3-am642-r5-evm.dts for the AM64x GP EVM, or k3-am642-r5-sk.dts for the AM64x SK EVM) should reference the new .dtsi file. The DDR driver will properly set the DDR frequency and initialize the DDR controller using the information in this .dtsi file

MCU+ SDK (RTOS)

The resulting .h file should be placed in mcu_plus_sdk_\<device\>\_\<version\>\source\drivers\ddr\v0\soc\<device> and included by using the SysConfig for SDK tool when building your code. Please refer to the SDK API Guide mcu_plus_sdk_\<device\>_\<version\>\docs\api_guide_am64x\DRIVERS_DDR_PAGE.html for more information

Desktop Version

For computers without internet access, the DDR Register Configuration tool can be downloaded and installed on your local workstation by following these instructions:

• Install SysConfig

  • Download the latest Sysconfig from https://www.ti.com/tool/SYSCONFIG
  • Run the installer and install to c:\ti for windows or ~/ti for linux

• Install the DDR RegConfig Tool:

  • Open Resource Explorer at https://dev.ti.com/tirex/explore
  • Select the menu (icon with 3 horizontal lines) in the upper right and choose Package Manager
  • Scroll until you see DDR Configuration for AM64x, AM625, AM623, AM62Ax, AM62Px
  • Select More and choose the latest version to download
  • You should now have a zip file Processor_DDR_Config_\<version\>_all.zip Extract the zip to c:\ti for windows or ~/ti for linux.

• Run the tool with the following command after substituting for:

  • The SysConfig version,
  • The Processor_DDR_Config version, and
  • The device name if needed (either AM64x, AM62x, AM62Ax, AM62Px)

Windows command example:

c:\ti\sysconfig_<version>\sysconfig_gui.bat --product c:\ti\Processor_DDR_Config_<version>\.metadata\product.json --device AM62x

Linux command example:

~/ti/sysconfig_<version>/sysconfig_gui.sh --product ~/ti/Processor_DDR_Config_<version>/.metadata/product.json --device AM62x