Revision History

v0.10.02

• fixed CA VREF range1 training search for LPDDR4
• updated README, added DDR4 instructions
• added flexibility in choosing operating frequencies
• added selections for DDR4: LPASR, TCR mode, TCR range, and CA Parity Latency
• alphabetized timing parameters in DDR4
• changed WDQS Extension to enabled by default for LPDDR4. This enables WDQS Read Based Control.
• added periodic ZQ calibration selection for LPDDR4
• added REGION_IDX parameter to properly set Subsystem register

v0.10.01

• new cosmetic changes: including being able to choose reference design as starting point
• added support for "Set B" write latencies in LPDDR4
• updated ODTon/off values per freq
• added support for enabling periodic ZQ Calibration in LPDDR4 memories (only 256ms period)
• added support for separate CK drive setting in LPDDR4
• allow for direct input of operating frequency in DDR4. Added warning and error checking
• updated DFI timings for AM62Ax and AM62Px
• added SDRAM_IDX parameter to properly set Subsystem register
• changed tool version in README from xx.xx to x.xx.xx (was missing leading revision)

v0.9.10

• added AM62Px LPDDR4 support
• added support for swizzle of DMIx along with DQx (AM62x/AM62A/AM62P)
• allow for direct input of operating frequency in LPDDR4
• adjusted RST_DRIVE during initialization

v0.9.09

• added LPDDR4 description in README
• added instructions for offline support in README
• added 1200MHz use case for AM62A
• added auto adjustments of tRAS and tREFI with change in temp selection
• updated changes to latency parameters when frequency changes
• changed CS_MAP parameters to support 16-bit in AM62A
• rx_pclk_clk_sel update
• added WDQ leveling configuration selection

v0.9.08

• added automatic change of RL, WL and nWR when frequency is changed
• added DQ swizzle and byte swap configuration flexibilty for AM62x/AM62A LPDDR4
• PHY_CAL_CLK updated divider values for higher frequencies
• CS ODT fix bug introduced in previous release

v0.9.05:

• cleaned up supported frequencies

v0.9.04:

• changed wrlvl_delay_early_threshold=0x100 to allow write leveling to complete successfully for wider array of layouts
• add cmm output
• LPDDR4: phy_rddqs_latency_adjust changed to 0 default recommendation (this value gets optimized during training)
• LPDDR4: optimized training loops to support 1 operating frequency
• LPDDR4/DDR4: optimized IO calibration configuration based on operating frequency
• LPDDR4/DDR4: optimized internal calibration clock based on operating frequency
• LPDDR4: changed default MR22 ODTE-CS=1
• LPDDR4: changed rx_ctle_cs default to No Boost
• AM62x dual rank support
• updated to use sysconfig v1.15
• public release for AM62A LPDDR4 support

v0.8.80:

• added support for AM62x release.
• Added support for high temp operation.
• CTL_165[11]=1 (LPI_WAKEUP_EN) only applicable for AM62x
• CTL_321[23:8] = 0xFFFF (CS_MSK_1) corrected value when rank 1 disabled

v0.8.40: provides improved operation at 1600MTs for both LPDDR4 and DDR4.
Changes from previous version include:

• changed default value CTRLUPD_AREF_HP_ENABLE=0
• changed default value LPI_\WAKEUP_EN=0
• changed cal_clk divider and PVT calibration interval. This change provides significant stability improvements for LPDDR4 and DDR4 operation at 1600MTs
• fixed TOSCO_F0 calculation for LPDDR4

v0.8.10: initial stable version.
Changes from previous versions include:

• added read/write DBI selection for LPDDR4/DDR4. Default to enable write DBI for LPDDR4, read DBI for DDR4 to improve power supply noise and improve overall signal integrity
• changed default value of CA ODT to 60ohm for both LPDDR4 and DDR4
• updated RTOS output to fix #ifdef
• periodic write DQ leveling disabled to improve realtime performance
• disabled "always-on" mode of the input enables for data bytes for power optimization
• disabled VREF controller for addr/cmd signals for power optimization