Date: June 27th, 2025          
  Revision: 0.12.0          
                   
  NOTE: The user interfaced moved from a spreadsheet workbook to SysConfig starting with version 0.11.0          
                   
  Revision Date Changes Comments          
  0.1.0 September 19th, 2019 NA Initial Release          
  0.2.0 October 9th, 2019 1) Modified DDRSS_CTL_274, COMMAND_AGE_COUNT from 255 to 15
2) Added "GEL" tab
3) General formatting of output ("u-boot" tab)		            
  0.3.0 October 13th, 2019 1) Added parameter "DDR Density" to "Config" tab.
2) Updated following parameters based on input of "DDR Density" from "Config" tab:
    - DDRSS_CTL_268, ROW_DIFF_1 & ROW_DIFF_0
    - DDRSS_CTL_270, CS_VAL_UPPER_0
    - DDRSS_CTL_271, CS_VAL_LOWER_1 & CS_VAL_UPPER_1
    - DDRSS_CTL_272, CS_MSK_0
    - DDRSS_CTL_273, CS_MSK_1
    - DDRSS_PI_73, PI_ROW_DIFF
3) Updated following parameters based on input of "Chip Select / Ranks" from "Config" tab:
    - DDRSS_CTL_273, CS_LOWER_ADDR_EN
    - DDRSS_PLL_FHS_CNT (Global)		            
  0.4.0 February 18th, 2020 1) Added "RTOS" tab
2) Added support to enable hardware polling of MR4 (temperature of DRAM) to support dynamic refresh rates
    - "Config" Tab:
        > Modified section A, detail 11
            ~ Parameter: from "Max DRAM Operating Temperature" to "Enable DRAM Temperature Polling"
            ~ Value: from "Not used" to configurable options "Yes" or "No"; "No" set as default
            ~ Units: from "Celsius" to "NA"
            ~ Notes: Modified associated notes
        > Added section A, detail 12 ("System Temperature Gradient")
    - "DRAMTiming" Tab:
        > Added new row for parameter 'tTSI'
        > Added new row for parameter 'Device temperature margin'
    - Register Updates (based on new parameters):
        > DDRSS_CTL_124, MRR_TEMPCHK_HIGH_THRESHOLD_F0
        > DDRSS_CTL_124, MRR_TEMPCHK_NORM_THRESHOLD_F0
        > DDRSS_CTL_125, MRR_TEMPCHK_NORM_THRESHOLD_F1
        > DDRSS_CTL_126, MRR_TEMPCHK_HIGH_THRESHOLD_F1
        > DDRSS_CTL_127, MRR_TEMPCHK_NORM_THRESHOLD_F2
        > DDRSS_CTL_127, MRR_TEMPCHK_HIGH_THRESHOLD_F2
    * NOTE: Use of feature requires software interrupt routine to adjust refresh rate accordingly		 1) Feature update (no impact to register settings)
2) Feature update (requires software ISR)		          
  0.5.0 August 4th, 2020 1) Updated write DQ training pattern to improve centering of trained value
    - Register Updates
        > DDRSS_PHY_33, PHY_WDQLVL_PATT_0
        > DDRSS_PHY_289, PHY_WDQLVL_PATT_1
        > DDRSS_PHY_545, PHY_WDQLVL_PATT_2
        > DDRSS_PHY_801, PHY_WDQLVL_PATT_3
2) Updated VREF training start value to prevent training failures
    - Register Updates
        > DDRSS_PHY_85, PHY_VREF_INITIAL_START_POINT_0
        > DDRSS_PHY_341, PHY_VREF_INITIAL_START_POINT_1
        > DDRSS_PHY_597, PHY_VREF_INITIAL_START_POINT_2
        > DDRSS_PHY_853, PHY_VREF_INITIAL_START_POINT_3
3) Corrected mis-match in read / write post-amble settings between DRAM and SOC
    - Register Updates
        > DDRSS_PHY_17, PHY_LP4_PST_AMBLE_0
        > DDRSS_PHY_273, PHY_LP4_PST_AMBLE_1
        > DDRSS_PHY_529, PHY_LP4_PST_AMBLE_2
        > DDRSS_PHY_785, PHY_LP4_PST_AMBLE_3		 Updates 1-7 correct and/or improve register calculations          
  4) Corrected delay value used in formula to calculate number of cycles from dfi_rddata_en to release from FIFO
    - Register Updates
        > DDRSS_PHY_104, PHY_RPTR_UPDATE_0
        > DDRSS_PHY_360, PHY_RPTR_UPDATE_1
        > DDRSS_PHY_616, PHY_RPTR_UPDATE_2
        > DDRSS_PHY_872, PHY_RPTR_UPDATE_3
    - Register Indirect Impact
        > DDRSS_PI_46, PI_TDFI_RDLVL_RR
        > DDRSS_PI_211, PI_TDFI_WDQLVL_RW_F0
        > DDRSS_PI_213, PI_TDFI_WDQLVL_RW_F1
        > DDRSS_PI_216, PI_TDFI_WDQLVL_RW_F2
5) Enable periodic write DQ training (delay only) to compensate for temperature variations. Disable parallel channel training.
    - Register Updates
        > DDRSS_PI_66, PI_WDQLVL_VREF_EN
        > DDRSS_PI_71, PI_WDQLVL_INTERVAL
        > DDRSS_PI_72, PI_PARALLEL_WDQLVL_EN
        > DDRSS_PI_212, PI_WDQLVL_EN_F0
        > DDRSS_PI_214, PI_WDQLVL_EN_F1
        > DDRSS_PI_217, PI_WDQLVL_EN_F2		          
  6) Update the PCLK to the IOs
    - Register Updates
        > DDRSS_PHY_92, PHY_PAD_DSLICE_IO_CFG_0
        > DDRSS_PHY_348, PHY_PAD_DSLICE_IO_CFG_1
        > DDRSS_PHY_604, PHY_PAD_DSLICE_IO_CFG_2
        > DDRSS_PHY_860, PHY_PAD_DSLICE_IO_CFG_3
        > DDRSS_PHY_1064, PHY_PAD_ADR_IO_CFG_0
        > DDRSS_PHY_1393, PHY_PAD_CAL_IO_CFG_0
        > DDRSS_PHY_1394, PHY_PAD_ACS_IO_CFG
7) Adjust the DQS duty cycle to balance low/high pulse width
    - Register Updates
        > DDRSS_PHY_136, PHY_DATA_DC_DQS_CLK_ADJUST_0
        > DDRSS_PHY_392, PHY_DATA_DC_DQS_CLK_ADJUST_1
        > DDRSS_PHY_648, PHY_DATA_DC_DQS_CLK_ADJUST_2
        > DDRSS_PHY_904, PHY_DATA_DC_DQS_CLK_ADJUST_3
8) Globally updated tool name from "AM752x_DRA829_TDA4xM_*" to "Jacinto7_*". Removed "AM752x" from supported TI part numbers on worksheet "Title-README".		          
  0.6.0 June 1st, 2021 1) Added support for DRA821U
    - Added all supported SOC part numbers to parameter A2 ("TI SOC Part Number") on the "Config" tab.
    - Added macros to allow user to load the default SDK configurations for DRA821U and DRA829x/TDA4VM. From the "Title-README" worksheet, select the desired SOC and then use the "Load User Config" button to pre-populate the tool.
    * NOTE: Some parameters may be dependent on the selected SOC. Always ensure proper SOC selected when configuring tool.		            
  2) Enable the DRAM VRCG (errata i2159)
    - Register Updates
        > DDRSS_PI_259, PI_MR13_DATA_0
        > DDRSS_PI_261, PI_MR13_DATA_1
        > DDRSS_PI_263, PI_MR13_DATA_2
        > DDRSS_PI_265, PI_MR13_DATA_3		            
  3) Update PHY PLL SPO calibration control setting to ensure calibration converges to optimal setting
    - Register Updates
        > DDRSS_PHY_1310, PHY_PLL_SPO_CAL_CTRL		            
  4) Reduce the maximum read eye training slave delay search window to reduce boot time
    - Register Updates
        > DDRSS_PHY_108, PHY_RDLVL_MAX_EDGE_0
        > DDRSS_PHY_364, PHY_RDLVL_MAX_EDGE_1
        > DDRSS_PHY_620, PHY_RDLVL_MAX_EDGE_2
        > DDRSS_PHY_876, PHY_RDLVL_MAX_EDGE_3		            
  5) Allow the boot frequency used by drivers to be controlled by tool output.
    - Added output parameter DDRSS_PLL_FREQUENCY_0 to worksheets "u-boot", "GEL", "RTOS", "CMM"
    * NOTE: Parameter not used by drivers prior to SDK8.0
6) Modify the default input of parameter A5 ("DDR Memory Boot Frequency") on the "Config" tab to 55 MHz to match max boot frequency supported by DRAM.
    - Register updates: No forumlas updated with respect to this update; however, input change will impact several parameter values
    * NOTE: This change does not impact the actual boot frequency prior to SDK8.0		            
  7) Add 16-bit bus width support
    - Added "16" bit option of paramter A8 ("DDR Data Bus Width") on the "Config" tab
    - Register Updates
        > DDRSS_CTL_270, CS_VAL_UPPER_0
        > DDRSS_CTL_271, CS_VAL_UPPER_1
        > DDRSS_CTL_271, CS_VAL_LOWER_1
        > DDRSS_CTL_272, CS_MSK_0
        > DDRSS_CTL_273, CS_MSK_1
        > DDRSS_CTL_278, REDUC
        > DDRSS_CTL_286, DEVICE1_BYTE0_CS0
        > DDRSS_CTL_286, MEMDATA_RATIO_0
        > DDRSS_CTL_287, DEVICE1_BYTE0_CS1
        > DDRSS_CTL_287, DEVICE0_BYTE0_CS1
        > DDRSS_CTL_287, MEMDATA_RATIO_1
        > DDRSS_PI_14, PI_CS_MAP
        > DDRSS_PI_29, PI_WRLVL_CS_MAP
        > DDRSS_PI_45, PI_RDLVL_GATE_CS_MAP
        > DDRSS_PI_45, PI_RDLVL_CS_MAP
        > DDRSS_PI_55, PI_CALVL_CS_MAP
        > DDRSS_PI_67, PI_WDQLVL_CS_MAP		            
  8) Update controller MR22 parameters to match PI MR22 parameters
    - Register Updates
        > DDRSS_CTL_181, MR22_DATA_F0_0
        > DDRSS_CTL_182, MR22_DATA_F1_0
        > DDRSS_CTL_182, MR22_DATA_F2_0
        > DDRSS_CTL_189, MR22_DATA_F0_1
        > DDRSS_CTL_189, MR22_DATA_F1_1
        > DDRSS_CTL_189, MR22_DATA_F2_1		            
  9) Update feedback IO settings to use CA input parameters
    - Register Updates
        > DDRSS_PHY_1406, PHY_PAD_FDBK_DRIVE
        > DDRSS_PHY_1407, PHY_PAD_FDBK_DRIVE2		            
  10) Add "CMM" output tab            
  0.6.1 July 19th, 2021 1) Updated write DQ training pattern (from 0x7 to 0x6) to prevent invalid training results observed in some systems
    - Register Updates
        > DDRSS_PHY_33, PHY_WDQLVL_PATT_0
        > DDRSS_PHY_289, PHY_WDQLVL_PATT_1
        > DDRSS_PHY_545, PHY_WDQLVL_PATT_2
        > DDRSS_PHY_801, PHY_WDQLVL_PATT_3
2) Added a new SDK configuration macro to support the TDA4VM / DRA829x Edge AI board		            
  0.7.0 October 14th, 2021 1) Add support for non-power-of-2 density memories
    - Added new user options (1Gb, 3Gb, 6Gb, 12Gb) to detail 9 (DDR Density) of section A (System Configuration) on the
    Config worksheet
    - Register Updates
        > DDRSS_CTL_268, ROW_DIFF_0
        > DDRSS_CTL_268, ROW_DIFF_1
        > DDRSS_CTL_270, CS_VAL_UPPER_0
        > DDRSS_CTL_271, CS_VAL_UPPER_1
        > DDRSS_CTL_271, CS_VAL_LOWER_1
        > DDRSS_CTL_272, CS_MAP_NON_POW2
        > DDRSS_CTL_272, ROW_START_VAL_1
        > DDRSS_PI_73, PI_ROW_DIFF		            
  2) Update register calculation of cs_lower_addr_en for non-power-of-2 density memories (errata i2182)
    - Use cs-row-bank-col address mapping with dual-rank non-power-of-2 density LPDDR4 devices
    - Register Updates: DDRSS_CTL_273, CS_LOWER_ADDR_EN		          
  3) Correct register calculation bug of the tool which impacts the DRAM temperature polling feature
    - Description of bug: When temperature polling is enabled and the system temperature gradient is set substantially high relative
    to what the processor and DRAM can account for, then the tool calculates a negative time required to read the MR4 register
    of the LPDDR4 memory. As a negative value is invalid, this bug results in an incorrect register value and large delay between
    reads due to underflow.
    - Fix: Updated calculations to program registers to minimum value when system temperature gradient is too large.
    - Added a warning to detail 12 (System Temperature Gradient) of section A (System Configuration) on the Config worksheet
    when the user inputs a value that results in an invalid value.
    - Register Updates
        > DDRSS_CTL_124, MRR_TEMPCHK_HIGH_THRESHOLD_F0
        > DDRSS_CTL_124, MRR_TEMPCHK_NORM_THRESHOLD_F0
        > DDRSS_CTL_125, MRR_TEMPCHK_NORM_THRESHOLD_F1
        > DDRSS_CTL_126, MRR_TEMPCHK_HIGH_THRESHOLD_F1
        > DDRSS_CTL_127, MRR_TEMPCHK_HIGH_THRESHOLD_F2
        > DDRSS_CTL_127, MRR_TEMPCHK_NORM_THRESHOLD_F2		          
  4) Add support for TDA4AL, TDA4VE, TDA4VL
    a) Add support for second DDRSS
        - Duplicate all input parameters with the exception of details 1-4 and 13-15 of section A (System Configuration) on
        the Config worksheet
    b) Add support for interleaving between two DDR sub-systems
        - Changed the name of detail 3 of section A (System Configuration) on the Config worksheet from "OSC1 Input Frequency"
        to "DDR Controllers Utilized in System", and added a drop-down selections for parameter.
        - Added new inputs, details 13-15 of section A (System Configuration) on the Config worksheet
        - Added table section System DDR Size to section A (System Configuration) on the Config worksheet to illustrate memory
        usage based on selected parameters
    c) Update all output tabs to include items (a) and (b); output for previously supported devices is unchanged when saved using
        the push buttons
    d) Add macro option to pre-populate tool with inputs for TI EVM / SOM. Update existing device macros for new user inputs.		          
  5) Minor update to save push-buttons to fix file filter for some file types          
  0.7.1 December 2nd, 2021 1) Fix tool bug that incorrectly used some DDRSS0 inputs to calculate some DDRSS1 register values.
    - Register Updates (impacted parameters)
        > DDRSS1_CTL_55, BSTLEN
        > DDRSS1_CTL_270, CS_VAL_UPPER_0
        > DDRSS1_CTL_271, CS_VAL_UPPER_1
        > DDRSS1_CTL_271, CS_VAL_LOWER_1
        > DDRSS1_CTL_272, CS_MSK_0
        > DDRSS1_CTL_273, CS_MSK_1
        > DDRSS1_PI_46, PI_TDFI_RDLVL_RR
        > DDRSS1_PHY_102, PHY_RDDATA_EN_OE_DLY_0
        > DDRSS1_PHY_131, PHY_RDDQS_LATENCY_ADJUST_0
        > DDRSS1_PHY_358, PHY_RDDATA_EN_OE_DLY_1
        > DDRSS1_PHY_387, PHY_RDDQS_LATENCY_ADJUST_1
        > DDRSS1_PHY_614, PHY_RDDATA_EN_OE_DLY_2
        > DDRSS1_PHY_643, PHY_RDDQS_LATENCY_ADJUST_2
        > DDRSS1_PHY_870, PHY_RDDATA_EN_OE_DLY_3
        > DDRSS1_PHY_899, PHY_RDDQS_LATENCY_ADJUST_3		 This bug would only impact settings where inputs to DDRSS1 differed compared to DDRSS0.          
  0.8.0 May 4th, 2022 1) Improve write DQ training by increasing the minimum valid window to prevent false edge detection.
    - NOTE: This change is intended to address the same issue addressed by v0.6.1 (change 1) release.
                It is recommended to implement both changes.
    - Register Updates (impacted parameters)
        > DDRSSn_PHY_32, PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
        > DDRSSn_PHY_288, PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
        > DDRSSn_PHY_544, PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
        > DDRSSn_PHY_800, PHY_WDQLVL_CLK_JITTER_TOLERANCE_3		            
  2) Disable the PHY PLL calibration to prevent corner cases where circuit may not lock.
    - Register Updates (impacted parameters)
        > DDRSSn_PHY_1310, PHY_PLL_SPO_CAL_CTRL		            
  3) Enable periodic ZQ calibration of the DRAM.
    - Register Updates (impacted parameters)
        > DDRSSn_CTL_229, ZQ_CALSTART_HIGH_THRESHOLD_F0
        > DDRSSn_CTL_229, ZQ_CALSTART_NORM_THRESHOLD_F0
        > DDRSSn_CTL_230, ZQ_CALLATCH_HIGH_THRESHOLD_F0
        > DDRSSn_CTL_233, ZQ_CALSTART_NORM_THRESHOLD_F1
        > DDRSSn_CTL_234, ZQ_CALLATCH_HIGH_THRESHOLD_F1
        > DDRSSn_CTL_234, ZQ_CALSTART_HIGH_THRESHOLD_F1
        > DDRSSn_CTL_238, ZQ_CALSTART_HIGH_THRESHOLD_F2
        > DDRSSn_CTL_238, ZQ_CALSTART_NORM_THRESHOLD_F2
        > DDRSSn_CTL_239, ZQ_CALLATCH_HIGH_THRESHOLD_F2
        > DDRSSn_CTL_267, ZQ_CAL_LATCH_MAP_1
        > DDRSSn_CTL_267, ZQ_CAL_START_MAP_1
        > DDRSSn_CTL_267, ZQ_CAL_LATCH_MAP_0
        > DDRSSn_CTL_267, ZQ_CAL_START_MAP_0		            
  4) Fix tool bug impacting Read DBI functionality.
    - Register Updates (impacted parameters)
        > DDRSSn_PHY_102, PHY_DBI_MODE_0
        > DDRSSn_PHY_358, PHY_DBI_MODE_1
        > DDRSSn_PHY_614, PHY_DBI_MODE_2
        > DDRSSn_PHY_870, PHY_DBI_MODE_3		            
  5) Enable SOC VREF training
    - NOTE: These changes only apply to DRA821. SOC VREF training is already enabled for other parts supported by the tool.
    - Register Updates (impacted parameters)
        > DDRSS_PI_182, PI_RDLVL_PAT0_EN_F0
        > DDRSS_PI_183, PI_RDLVL_PAT0_EN_F1
        > DDRSS_PI_184, PI_RDLVL_PAT0_EN_F2		            
  6) Updated CA training parameters to improve CA VREF variability
    - NOTE: These changes only apply to DRA821
    - Register Updates (impacted parameters)
        > DDRSSn_PHY_1039, PHY_ADR_CALVL_NUM_PATTERNS_0
        > DDRSSn_PHY_1074, PHY_ADR_MEAS_DLY_STEP_ENABLE_0		            
  7) Optimized certain training parameters to improve (reduce) the DRAM initialization and training time.
    - NOTE: These changes only apply to DRA821, with the exception of PHY_RDLVL_DLY_STEP_* which was updated to match
                other supported parts supported by the tool.
    - Register Updates (impacted parameters)
        > DDRSSn_PI_61, PI_CALVL_VREF_INITIAL_STEPSIZE
        > DDRSSn_PI_67, PI_WDQLVL_VREF_INITIAL_STEPSIZE
        > DDRSSn_PI_67, PI_WDQLVL_VREF_NORMAL_STEPSIZE
        > DDRSSn_PI_72, PI_PARALLEL_WDQLVL_EN
        > DDRSSn_PHY_12, PHY_VREF_INITIAL_STEPSIZE_0
        > DDRSSn_PHY_268, PHY_VREF_INITIAL_STEPSIZE_1
        > DDRSSn_PHY_524, PHY_VREF_INITIAL_STEPSIZE_2
        > DDRSSn_PHY_780, PHY_VREF_INITIAL_STEPSIZE_3
        > DDRSSn_PHY_31, PHY_RDLVL_CAPTURE_CNT_0
        > DDRSSn_PHY_287, PHY_RDLVL_CAPTURE_CNT_1
        > DDRSSn_PHY_543, PHY_RDLVL_CAPTURE_CNT_2
        > DDRSSn_PHY_799, PHY_RDLVL_CAPTURE_CNT_3
        > DDRSSn_PHY_100, PHY_VREF_SETTING_TIME_0
        > DDRSSn_PHY_356, PHY_VREF_SETTING_TIME_1
        > DDRSSn_PHY_612, PHY_VREF_SETTING_TIME_2
        > DDRSSn_PHY_868, PHY_VREF_SETTING_TIME_3
        > DDRSSn_PHY_107, PHY_RDLVL_DLY_STEP_0
        > DDRSSn_PHY_363, PHY_RDLVL_DLY_STEP_1
        > DDRSSn_PHY_619, PHY_RDLVL_DLY_STEP_2
        > DDRSSn_PHY_875, PHY_RDLVL_DLY_STEP_3
        > DDRSSn_PHY_1073, PHY_ADR_CALVL_DLY_STEP_0
        > DDRSSn_PHY_1303, PHY_PLL_WAIT
        > DDRSSn_PHY_1397, PHY_CSLVL_DLY_STEP		            
  8) Enable single frequency set point to improve (reduce) DRAM initialization and training time.
    - NOTE: These changes only apply to DRA821
    - Global Updates
        > Updated calculation of macro DDRSS_PLL_FHS_CNT
    - Register Updates (impacted parameters)
        > DDRSSn_PI_12, PI_FREQ_MAP
        > DDRSSn_PI_13, PI_INIT_WORK_FREQ
        > DDRSSn_PI_176, PI_WRLVL_EN_F2
        > DDRSSn_PI_182, PI_RDLVL_GATE_EN_F2
        > DDRSSn_PI_182, PI_RDLVL_EN_F2
        > DDRSSn_PI_191, PI_CALVL_EN_F2
        > DDRSSn_PI_217, PI_WDQLVL_EN_F2		            
  9) Update the DRA821 default configuration (macro) to address errata and enable LP4-3200 for SR2.0 material
    - "Config" Input Updates
        > Enable Write DBI (Cells E65, F65, G65)
        > Set DDR memory frequency (F2) to 1600 MHz (Cells E33)
    - "DRAMTiming" Input Updates
        > Update read latency to 28 (Cells G25, H25)
        > Update write latency to 14 (Cells G27, H27)
        > Update write recovery to 30 (Cells G28, H28)
        > Update ODTLon to 6 (Cells G29, H29)
        > Update ODTLoff to 24 (Cells G30, H30)
    - "IOControl" Input Updates
        > Update CA drive strength to 40 ohms (Cells L27, L28)
        > Update CS drive strength to 80 ohms (Cells P27, P28)
    - "RTOS" Output Updates
        > All arrays and macros appended with "_v1" and "_V1" respectively
        > Header file default name appended with "_v1".		            
  10) General Updates
    - De-scoped support for DRA821 SR1.0; added support for DRA821 SR2.0
    - "Config" Worksheet (Section A)
        > Removed old table notes 1, 2, 6 (shifting remaining table notes, ex: '3' --> '1')
        > Edited table note 1
        > Updated detail 9 to state from "per channel" to "per channel for single rank"
    - "Config" Worksheet (Section B)
        > Removed old table notes 2 (shifting remaining table notes, ex: '3' --> '2')		            
  0.9.0 May 27th, 2022 1) Fixed tool bug in which the PHY_DBI_MODE parameter of DDRSS1 was previously determined by DDRSS0 tool inputs.
    - Register Updates (impacted parameters)
        > DDRSS1_PHY_102, PHY_DBI_MODE_0
        > DDRSS1_PHY_358, PHY_DBI_MODE_1
        > DDRSS1_PHY_614, PHY_DBI_MODE_2
        > DDRSS1_PHY_870, PHY_DBI_MODE_3		            
  2) Fixed tool bug in which the drop down selections for the interleave granularity (Config tab, Section A, Detail 15) were incorrect for non-power-of-2 densities.            
  3) Add support for TDA4AH, TDA4AP,TDA4VH, TDA4VP
    a) Add support for third and fourth DDRSS
        - Duplicate all input parameters with the exception of details 1-4 and 13-15 of section A (System Configuration) on
        the Config worksheet
    b) Update all output tabs to include items (a); output for previously supported devices is unchanged when saved using
        the push buttons
    d) Add macro option to pre-populate tool with inputs for TI EVM / SOM.		            
  0.9.1 June 28th, 2022 1) Fixed tool bug introduced in v0.9.0 in which the MULTI_DDR_CFG_HYBRID_SELECT and MULTI_DDR_CFG_EMIFS_ACTIVE
    parameters were assigned the wrong value for the GEL, RTOS, and CMM output tabs.		            
  2) Re-enable PHY PLL calibration. (Undo change #2 from revision 0.8.0)
    - NOTE: This change ONLY applies to J721E devices. PHY PLL calibration disabled for all other devices.
    - Register Updates (impacted parameters)
        > DDRSSn_PHY_1310, PHY_PLL_SPO_CAL_CTRL		            
  0.9.2 October 21st, 2022 1) Reduce the delay caused by write DQ periodic training during normal operation.
    - NOTE: These changes only apply to DRA821.
    - Register Updates (impacted parameters)
        > DDRSSn_PI_66, PI_WDQLVL_ROTATE
        > DDRSSn_PI_67, PI_WDQLVL_PERIODIC		            
  2) Modify the built in macros to set the refresh rate input to 1.95 us (applied to all macros)            
  0.10.0 January 23rd, 2023 1) Update tRASmax to 17.55 us for all default configurations to match the faster refresh rate (1.95 us) applied in v0.9.2 of the tool.            
  2) Update the TDA4VE default configuration (macro)
    - "Config" Input Updates
        > Enable Write DBI on both DDRSS (Cells E65, F65, G65, H65, I65, J65)
        > Enable Read DBI on DDRSS1 (Cells H64, I64, J64), *which requires modifying the read latency*
    - "DRAMTiming" Input Updates
        > Update DDRSS1 read latency to 40 (Cells I25, J25)
    - "IOControl" Input Updates
        > Update CA ODT to 80 ohms (Cells E79, F79, H79, I79)		            
  3) Enable single frequency set point to improve (reduce) DRAM initialization and training time.
    - NOTE: This update applies the changes from item number 8 from v0.8.0 of the tool to J721S2 devices.
    - Global and Register Updates
        > See description of item number 8 from v0.8.0 of the tool.		            
  4) Optimized certain training parameters to improve (reduce) the DRAM initialization and training time.
    - NOTE: This update applies the changes from item number 7 from v0.8.0 of the tool to J721S2 devices, with the exception of
                changes to PHY_ADR_CALVL_DLY_STEP_0.
    - Register Updates (impacted parameters)
        > See description of item number 7 from v0.8.0 of the tool.		            
  5) Reduce the delay caused by write DQ periodic training during normal operation.
    - NOTE: These changes only apply to J721S2 devices and only apply to DDRSS0.
    - Register Updates (impacted parameters)
        > DDRSS0_PI_66, PI_WDQLVL_ROTATE
        > DDRSS0_PI_67, PI_WDQLVL_PERIODIC
        > DDRSS0_PHY_33, PHY_WDQLVL_PATT_0
        > DDRSS0_PHY_289, PHY_WDQLVL_PATT_1
        > DDRSS0_PHY_545, PHY_WDQLVL_PATT_2
        > DDRSS0_PHY_801, PHY_WDQLVL_PATT_3		            
  6) Adjust the DQS duty cycle
    - NOTE: These changes only apply to J721S2 devices.
    - Register Updates (impacted parameters)
        > DDRSSn_PHY_136, PHY_DATA_DC_DQS_CLK_ADJUST_0
        > DDRSSn_PHY_392, PHY_DATA_DC_DQS_CLK_ADJUST_1
        > DDRSSn_PHY_648, PHY_DATA_DC_DQS_CLK_ADJUST_2
        > DDRSSn_PHY_904, PHY_DATA_DC_DQS_CLK_ADJUST_3		            
  v0.11.0 April 8th, 2024 1) Add support for AM68x (J721S2 family), AM69x (J784S4 family), and the J722S family of devices.            
  2) Update the TDA4VM (J721E) default input configuration
    - "Config Input Updates"
        > Enable Write DBI		            
  3) Update the TDA4VH (J784S4) default input configuration
    - "Config" Input Updates
        > Enable Write DBI on DDRSS0, DDRSS1, DDRSS2, DDRSS3
        > Enable Read DBI on DDRSS3, *which requires modifying the read latency*
    - "DRAMTiming" Input Updates
        > Update DDRSS3 read latency to 40
    - "IOControl" Input Updates
        > Update DDRSS3 DRAM IO CA ODT and DQ ODT boot frequency to match operating frequency		            
  4) Enable single frequency set point to improve (reduce) DRAM initialization and training time.
    - NOTE: This update applies the changes from item number 8 from v0.8.0 of the tool to J784S4 devices.
    - Global and Register Updates
        > See description of item number 8 from v0.8.0 of the tool.		            
  5) Optimized certain training parameters to improve (reduce) the DRAM initialization and training time.
    - NOTE: This update applies the changes from item number 7 from v0.8.0 of the tool to J784S4 devices, with the exception of
                changes to PHY_ADR_CALVL_DLY_STEP_0.
    - Register Updates (impacted parameters)
        > See description of item number 7 from v0.8.0 of the tool.		            
  6) Removed or renamed several inputs.
    - System Configuration
        > Removed "Board / Project Name" (previously not configurable)
        > Removed "DDR Memory Type" (only LPDDR4 supported)
        > Re-named F0 frequency to "LPDDR4 Boot Frequency"
        > Removed F1 (previously not configurable). All F1 values will be set to match F2.
        > Re-named F2 frequency to "LPDDR4 Operating Frequency".
    - Memory Burst Configuration
        > Remove "burst length" parameter (only 16 sequential supported)
        > All other parameters reduced to single input for all 3x frequencies.
    - DRAM Timing Latency
        > Remove all inputs for F0 and F1. F0 latency parameters configured to match a frequency of 55 MHz or less. F1 values will be
        configured to match F2.
    - IO Control (TI Processor)
        > Removed VREF control for address / command signals (signals are output only)
        > Drive strength control reduced to single selection for all configurable parameters. (driver pull-up = driver pull-down)
        > ODT control reduced to single selection (ODT pull-up selection set to Hi-Z)
    - IO Control (DRAM)
        > Removed F1 parameters for the "VREF control" group parameters.
        > Removed F1 parameters for "CA ODT" and "DQ ODT".
        > All other parameters reduced to single input for all 3x frequencies.		            
  7) Add new variables (when applicable) in output files to account for scenarios where system using multiple DDRSS configurations use
    LPDDR4 memories with different rank count. New variables include: "DDRSS1_PLL_FHS_CNT", "DDRSS2_PLL_FHS_CNT",
    "DDRSS3_PLL_FHS_CNT".		            
  v0.12.0 June 27th, 2025 1) Added support for errata i2160 (Valid VRef Range Must be Defined During LPDDR4 Command Bus Training).
    - Register Updates (impacted parameters)
        > J721E, J7200, J21S2, J742S2, J784S4:
            * DDRSSx_PI_199, PI_CALVL_VREF_INITIAL_START_POINT_F1
            * DDRSSx_PI_199, PI_CALVL_VREF_INITIAL_STOP_POINT_F1
            * DDRSSx_PI_200, PI_CALVL_VREF_INITIAL_START_POINT_F2
            * DDRSSx_PI_200, PI_CALVL_VREF_INITIAL_STOP_POINT_F2
        > J722S:
            * DDRSS_PI_219, PI_CALVL_VREF_INITIAL_START_POINT_F1
            * DDRSS_PI_219, PI_CALVL_VREF_INITIAL_STOP_POINT_F1
            * DDRSS_PI_220, PI_CALVL_VREF_INITIAL_START_POINT_F2
            * DDRSS_PI_220, PI_CALVL_VREF_INITIAL_STOP_POINT_F2		            
  2) Assign rank 0 as terminating rank during command bus training (CBT).
    - NOTE: Terminating rank was previously determined by reading the LPDDR4 MR0 register during CBT.
    - Register Updates (impacted parameters)
        > J721E, J7200, J721S2, J742S2, J784S4:
            * DDRSSx_PI_161, PI_CATR
            * DDRSSx_PI_162, PI_NO_CATR_READ
        > J722S:
            * DDRSSx_PI_174, PI_CATR
            * DDRSSx_PI_175, PI_NO_CATR_READ		            
  3) Use all CA signals during CS training.
    - Register Updates (impacted parameters)
        > DDRSSx_PHY_1055, PHY_ADR_CSLVL_TRAIN_MASK_0		            
  4) Extend write DQS pre-amble.
    - NOTE: Change only applies to J722S
    - J722S Register Updates (impacted parameters)
        > DDRSS_PHY_67, PHY_LP4_WDQS_OE_EXTEND_0
        > DDRSS_PHY_323, PHY_LP4_WDQS_OE_EXTEND_1
        > DDRSS_PHY_579, PHY_LP4_WDQS_OE_EXTEND_2
        > DDRSS_PHY_835, PHY_LP4_WDQS_OE_EXTEND_3		            
  5) Changes to improve self-refresh power-down entry/exit when using the fastest refresh rate.
    a) Prevent the controller from over-writing the VREF (MR12 / MR14) values during a frequency change
        - Register Updates (impacted parameters)
            > J721E, J7200, J721S2, J742S2, J784S4: DDRSSx_CTL_191, FSP_PHY_UPDATE_MRW
            > J722S: DDRSS_CTL_281, FSP_PHY_UPDATE_MRW
    b) Disable periodic write DQ training for F0 (boot frequency)
        - Register Updates (impacted parameters)
            > J721E, J7200, J721S2, J742S2, J784S4: DDRSSx_PI_212, PI_WDQLVL_EN_F0
            > J722S: DDRSS_PI_235, PI_WDQLVL_EN_F0
    c) Update tREF register calculation to subtract 2 instead of 8 for frequencies less than or equal to 55 MHz. Additionally, maintain an even value for the F0 copy.
        - Register Updates (impacted parameters)
            > J721E, J7200, J721S2, J784S4:
                * DDRSSx_CTL_61, TREF_F0
                * DDRSSx_CTL_63, TREF_F1
                * DDRSSx_CTL_65, TREF_F2
                * DDRSSx_PI_170, TREF_F0
                * DDRSSx_PI_172, TREF_F1
                * DDRSSx_PI_174, TREF_F2
            > J722S: DDRSSx_PI_235:
                * DDRSSx_CTL_75, TREF_F0
                * DDRSSx_CTL_77, TREF_F1
                * DDRSSx_CTL_79, TREF_F2
                * DDRSSx_PI_188, TREF_F0
                * DDRSSx_PI_190, TREF_F1
                * DDRSSx_PI_192, TREF_F2
    d) Allow PHY to snoop controller writes to MR13.
        - NOTE: Does not apply to J722S devices
        - Register Updates (impacted parameters)
            > DDRSSx_PI_163, PI_TRACE_MC_MR13		            
  6) Mask all controller interrupts. Software to unmask on need-basis when configuring intterupts.
    - NOTE: Change does not apply to J722S devices
    - Register Updates (impacted parameters)
        > DDRSSx_CTL_297, INT_MASK_31_0
        > DDRSSx_CTL_298, INT_MASK_44_32		            
  7) Update MR4 polling frequency calculation to use new input parameter 'System Response Delay'.
    - NOTE: Change does not apply to J722S devices
    - Register Updates (impacted parameters)
        > DDRSSx_CTL_124, MRR_TEMPCHK_HIGH_THRESHOLD_F0
        > DDRSSx_CTL_124, MRR_TEMPCHK_NORM_THRESHOLD_F0
        > DDRSSx_CTL_125, MRR_TEMPCHK_NORM_THRESHOLD_F1
        > DDRSSx_CTL_126, MRR_TEMPCHK_HIGH_THRESHOLD_F1
        > DDRSSx_CTL_127, MRR_TEMPCHK_HIGH_THRESHOLD_F2
        > DDRSSx_CTL_127, MRR_TEMPCHK_NORM_THRESHOLD_F2		            
  8) Fix tool bug to ensure both controller and PHY are working off of the same operating frequency set
    - Register Updates (impacted parameters)
        > J721E, J7200, J721S2, J742S2, J784S4: DDRSSx_CTL_20, DFIBUS_FREQ_INIT
        > J722S: DDRSS_CTL_180, INIT_FREQ		 Change #8: No functional impact as both operating frequency sets are configured to the same frequency.          
  9) Fix tool bug. Set PHY_TOGGLE_PRE_SUPPORT according to MR1 read pre-amble configuration.
    - Register Updates (impacted parameters)
        > J721E, J7200, J721S2, J742S2, J784S4:
            * DDRSSx_PHY_107, PHY_TOGGLE_PRE_SUPPORT_0
            * DDRSSx_PHY_363, PHY_TOGGLE_PRE_SUPPORT_1
            * DDRSSx_PHY_619, PHY_TOGGLE_PRE_SUPPORT_2
            * DDRSSx_PHY_875, PHY_TOGGLE_PRE_SUPPORT_3
        > J722S:
            * DDRSS_PHY_105, PHY_TOGGLE_PRE_SUPPORT_0
            * DDRSS_PHY_361, PHY_TOGGLE_PRE_SUPPORT_1
            * DDRSS_PHY_617, PHY_TOGGLE_PRE_SUPPORT_2
            * DDRSS_PHY_873, PHY_TOGGLE_PRE_SUPPORT_3		 Change #9: No impact to default configuration or systems using "static" read pre-amble.          
  10) Fixed tool bug (introduced in v0.11.0) which prevented MR4 polling feature from being enabled when tool input 'Enable DRAM Temperature Polling' was set to 'Yes'.
    - NOTE: Does not apply to J722S devices, where the feature / tool input is not supported.		            
  11) Modified default inputs
    - NOTE: All changes listed do not apply to J722S tool inputs.
    - Update all timing inputs to match JEDEC defined values instead of memory specific values
    - Enable Read DBI where not enabled (and update read latency accordingly)
    - Reduced 'System Temperature Gradient Maximum' to 20C/s		            
  12) Modified tool inputs
    - NOTE: All changes listed do not apply to J722S tool inputs.
    - Modified input selection for 'Multi DDRSS Interleave Memory Size' to be based on allowed values
    - Modified input selection for 'Multi DDRSS Interleave Granularity' to be based on allowed values
    - Added new input for max DRAM temp range, 'DRAM Max Operating Temperature'
    - Added new input 'System Response Delay'
    - Reduced & organized inputs from section "DRAM Timing B"
    - Added buttons (8x total, 2x per DDRSS) to auto populate timings based on JEDEC values		            
  13) Improved DTSI output file integration to SDK by adding new output #DEFINE definitions
    a) Enabling a subset of the SOC DDRSS (applies to J721S2, J742S2, and J784S4 devices only)
        - Added 'DDRx_CTL_NODE_STAT' definitions to output file, where 'x' is 0, 1, 2, or 3
        - NOTE: Requires device *-ddr.dtsi file add memory controller node property "status = DDRx_CTL_NODE_STAT"
    b) Defining total DDR memory available to system (applies to all devices except J722S devices)
        - Added 'DDR_REG0_SIZE_MSB', 'DDR_REG0_SIZE_LSB', 'DDR_REG1_SIZE_MSB', and 'DDR_REG1_SIZE_LSB' definitions
        - NOTE: Requires board DTSI file to replace the hard coded values in the memory 'reg' property with new definitions
    c) Added register definitions for unused DDRSS (applies to J784S4 only)		            
  14) Added new error checking for the following inputs:
    - NOTE: All changes listed do not apply to J722S tool inputs.
    - Multi DDRSS Interleave Memory Size (J721S2, J742S2, and J784S4 only)
    - Multi DDRSS Interleave Granularity (J721S2, J742S2, and J784S4 only)
    - LPDDR4 Boot Frequency
    - LPDDR4 Operating Frequency
    - Enable DRAM Temperature Polling
    - Data Bus Inversion (Read)
    - Data Bus Inversion (Write)
    - All inputs under sections "DRAM Timing A" and "DRAM Timing B"		            
  15) Added support for J742S2 family of devices.