UDMACC26XX.h
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103 #ifndef ti_drivers_UDMACC26XX__include
104 #define ti_drivers_UDMACC26XX__include
105 
106 #include <stdint.h>
107 #include <stdbool.h>
108 
109 #include <ti/drivers/Power.h>
111 
112 #include <ti/devices/DeviceFamily.h>
113 #include DeviceFamily_constructPath(inc/hw_types.h)
114 #include DeviceFamily_constructPath(driverlib/udma.h)
115 
116 #ifdef __cplusplus
117 extern "C" {
118 #endif
119 
130 /* Add DMACC26XX_STATUS_* macros here */
131 
144 /* Add DMACC26XX_CMD_* macros here */
145 
149 #if !defined(UDMACC26XX_CONFIG_BASE) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2)
150  /* On CC13X2, CC13X2X7, CC26X2, and CC26X2X7 devices, the uDMA table needs
151  * to be offset a few kB since the ROM area of SRAM is placed at the start
152  * of SRAM on those devices.
153  */
154  #define UDMACC26XX_CONFIG_BASE 0x20001800
155 #elif !defined(UDMACC26XX_CONFIG_BASE) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \
156  DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4)
157  /* Since there is no ROM area of SRAM on the CC13X1, CC26X1, CC13X4, and
158  * CC26X4 devices, we can move the uDMA table closer to the start of SRAM.
159  * This improves the linker efficiency when using dynamically sized heaps.
160  */
161  #define UDMACC26XX_CONFIG_BASE 0x20000400
162 #elif !defined(UDMACC26XX_CONFIG_BASE)
163  #define UDMACC26XX_CONFIG_BASE 0x20000400
164 #endif
165 
167 #if (UDMACC26XX_CONFIG_BASE & 0x3FF)
168  #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned."
169 #endif
170 
172 #if defined(__IAR_SYSTEMS_ICC__)
173  #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
174  __no_init static volatile tDMAControlTable ENTRY_NAME @UDMACC26XX_CONFIG_BASE + \
175  CHANNEL_INDEX * sizeof(tDMAControlTable)
176 #elif defined(__TI_COMPILER_VERSION__) || defined(__clang__)
177  #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
178  static volatile tDMAControlTable ENTRY_NAME \
179  __attribute__((retain, location(UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable))))
180 #elif defined(__GNUC__)
181  #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
182  extern int UDMACC26XX_##ENTRY_NAME##_is_placed; \
183  __attribute__((section("." #ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = { \
184  &UDMACC26XX_##ENTRY_NAME##_is_placed}
185 #else
186  #error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain"
187 #endif
188 
190 #define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M)
191 
192 #define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1)
193 
197 typedef struct
198 {
199  bool isOpen;
200  HwiP_Struct hwi;
202 
206 typedef struct
207 {
208  uint32_t baseAddr;
209  PowerCC26XX_Resource powerMngrId;
210  uint8_t intNum;
233  uint8_t intPriority;
235 
239 typedef struct
240 {
241  void *object;
242  void const *hwAttrs;
244 
249 
250 /* Extern'd hwiIntFxn */
251 extern void UDMACC26XX_hwiIntFxn(uintptr_t callbacks);
252 
265 __STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
266 {
267  UDMACC26XX_Object *object;
268 
269  /* Get the pointer to the object */
270  object = (UDMACC26XX_Object *)(handle->object);
271 
272  /* mark the module as available */
273  object->isOpen = false;
274 }
275 
291 extern UDMACC26XX_Handle UDMACC26XX_open(void);
292 
306 __STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
307 {
308  UDMACC26XX_HWAttrs const *hwAttrs;
309 
310  /* Get the pointer to the hwAttrs */
311  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
312 
313  /* Enable DMA channel */
314  HWREG(hwAttrs->baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask;
315 }
316 
335 __STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
336 {
337  UDMACC26XX_HWAttrs const *hwAttrs;
338 
339  /* Get the pointer to the hwAttrs */
340  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
341 
342  /* Check if REQDONE is set for a specific channel */
343  return (uDMAIntStatus(hwAttrs->baseAddr) & channelBitMask) ? true : false;
344 }
345 
363 __STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
364 {
365  UDMACC26XX_HWAttrs const *hwAttrs;
366 
367  /* Get the pointer to the hwAttrs and object */
368  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
369 
370  /* Clear UDMA done interrupt */
371  uDMAIntClear(hwAttrs->baseAddr, channelBitMask);
372 }
373 
391 __STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
392 {
393  UDMACC26XX_HWAttrs const *hwAttrs;
394 
395  /* Get the pointer to the hwAttrs */
396  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
397 
398  HWREG(hwAttrs->baseAddr + UDMA_O_CLEARCHANNELEN) = channelBitMask;
399 }
400 
421 __STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle, uint32_t channelNum, uint32_t attr)
422 {
423  UDMACC26XX_HWAttrs const *hwAttrs;
424 
425  /* Get the pointer to the hwAttrs */
426  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
427 
428  uDMAChannelAttributeDisable(hwAttrs->baseAddr, channelNum, attr);
429 }
430 
446 extern void UDMACC26XX_close(UDMACC26XX_Handle handle);
447 
448 #ifdef __cplusplus
449 }
450 #endif
451 
452 #endif /* ti_drivers_UDMACC26XX__include */
bool isOpen
Definition: UDMACC26XX.h:199
HwiP_Struct hwi
Definition: UDMACC26XX.h:200
void UDMACC26XX_hwiIntFxn(uintptr_t callbacks)
PowerCC26XX_Resource powerMngrId
Definition: UDMACC26XX.h:209
void UDMACC26XX_close(UDMACC26XX_Handle handle)
Function to close the DMA driver.
UDMACC26XX_Handle UDMACC26XX_open(void)
Function to initialize the CC26XX DMA peripheral.
__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:363
Power Manager.
__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:306
uint8_t intNum
Definition: UDMACC26XX.h:210
__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
Function to initialize the CC26XX DMA driver.
Definition: UDMACC26XX.h:265
__STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle, uint32_t channelNum, uint32_t attr)
Definition: UDMACC26XX.h:421
UDMACC26XX Global configuration.
Definition: UDMACC26XX.h:239
Power manager interface for CC26XX/CC13XX.
UDMACC26XX hardware attributes.
Definition: UDMACC26XX.h:206
void * object
Definition: UDMACC26XX.h:241
uint8_t intPriority
UDMACC26XX error interrupt priority. intPriority is the DMA peripheral&#39;s interrupt priority...
Definition: UDMACC26XX.h:233
__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:391
__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:335
uint32_t baseAddr
Definition: UDMACC26XX.h:208
UDMACC26XX object.
Definition: UDMACC26XX.h:197
UDMACC26XX_Config * UDMACC26XX_Handle
A handle that is returned from a UDMACC26XX_open() call.
Definition: UDMACC26XX.h:248
void const * hwAttrs
Definition: UDMACC26XX.h:242
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