UDMACC26XX.h

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/*
 * Copyright (c) 2015-2022, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef ti_drivers_UDMACC26XX__include
#define ti_drivers_UDMACC26XX__include

#include <stdint.h>
#include <stdbool.h>

#include <ti/drivers/Power.h>
#include <ti/drivers/power/PowerCC26XX.h>

#include <ti/devices/DeviceFamily.h>
#include DeviceFamily_constructPath(inc/hw_types.h)
#include DeviceFamily_constructPath(driverlib/udma.h)

#ifdef __cplusplus
extern "C" {
#endif

/* Add DMACC26XX_STATUS_* macros here */

/* Add DMACC26XX_CMD_* macros here */

#if !defined(UDMACC26XX_CONFIG_BASE)
    #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2)
        /* On CC13X2, CC13X2X7, CC26X2, and CC26X2X7 devices, the uDMA table needs
         * to be offset a few kB since the ROM area of SRAM is placed at the start
         * of SRAM on those devices.
         */
        #define UDMACC26XX_CONFIG_BASE 0x20001800
    #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1)
        /*
         * Since there is no ROM area of SRAM on the CC13X1 and CC26X1 devices, we
         * can move the uDMA table closer to the start of SRAM. This improves the
         * linker efficiency when using dynamically sized heaps.
         */
        #define UDMACC26XX_CONFIG_BASE 0x20000400
    #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4)
        /*
         * Since there is no ROM area of SRAM on the CC13X4 and CC26X4 devices, we
         * can move the uDMA table closer to the start of SRAM. This improves the
         * linker efficiency when using dynamically sized heaps.
         */
        #if (SPE_ENABLED == 0)
            #define UDMACC26XX_CONFIG_BASE 0x20000400
        #else
            #define UDMACC26XX_CONFIG_BASE 0x2000C400
        #endif
    #else
        #define UDMACC26XX_CONFIG_BASE 0x20000400
    #endif
#endif

#if (UDMACC26XX_CONFIG_BASE & 0x3FF)
    #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned."
#endif

#if defined(__IAR_SYSTEMS_ICC__)
    #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX)                     \
        __no_init static volatile tDMAControlTable ENTRY_NAME @UDMACC26XX_CONFIG_BASE + \
            CHANNEL_INDEX * sizeof(tDMAControlTable)
#elif defined(__TI_COMPILER_VERSION__) || defined(__clang__)
    #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
        static volatile tDMAControlTable ENTRY_NAME                 \
            __attribute__((retain, location(UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable))))
#elif defined(__GNUC__)
    #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX)                               \
        extern int UDMACC26XX_##ENTRY_NAME##_is_placed;                                           \
        __attribute__((section("." #ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = { \
            &UDMACC26XX_##ENTRY_NAME##_is_placed}
#else
    #error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain"
#endif

#define UDMACC26XX_SET_TRANSFER_SIZE(SIZE)    (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M)

#define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1)

typedef struct
{
    bool isOpen;     
    HwiP_Struct hwi; 
} UDMACC26XX_Object;

typedef struct
{
    uint32_t baseAddr;                
    PowerCC26XX_Resource powerMngrId; 
    uint8_t intNum;                   
    uint8_t intPriority;
} UDMACC26XX_HWAttrs;

typedef struct
{
    void *object;        
    void const *hwAttrs; 
} UDMACC26XX_Config;

typedef UDMACC26XX_Config *UDMACC26XX_Handle;

/* Extern'd hwiIntFxn */
extern void UDMACC26XX_hwiIntFxn(uintptr_t callbacks);

__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
{
    UDMACC26XX_Object *object;

    /* Get the pointer to the object */
    object = (UDMACC26XX_Object *)(handle->object);

    /* mark the module as available */
    object->isOpen = false;
}

extern UDMACC26XX_Handle UDMACC26XX_open(void);

__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs */
    hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);

    /* Enable DMA channel */
    HWREG(hwAttrs->baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask;
}

__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs */
    hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);

    /* Check if REQDONE is set for a specific channel */
    return (uDMAIntStatus(hwAttrs->baseAddr) & channelBitMask) ? true : false;
}

__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs and object */
    hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);

    /* Clear UDMA done interrupt */
    uDMAIntClear(hwAttrs->baseAddr, channelBitMask);
}

__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs */
    hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);

    HWREG(hwAttrs->baseAddr + UDMA_O_CLEARCHANNELEN) = channelBitMask;
}

__STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle, uint32_t channelNum, uint32_t attr)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs */
    hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);

    uDMAChannelAttributeDisable(hwAttrs->baseAddr, channelNum, attr);
}

extern void UDMACC26XX_close(UDMACC26XX_Handle handle);

#ifdef __cplusplus
}
#endif

#endif /* ti_drivers_UDMACC26XX__include */