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Go to the documentation of this file. 33 #ifndef __HW_CPU_ITM_H__ 34 #define __HW_CPU_ITM_H__ 43 #define CPU_ITM_O_STIM0 0x00000000 46 #define CPU_ITM_O_STIM1 0x00000004 49 #define CPU_ITM_O_STIM2 0x00000008 52 #define CPU_ITM_O_STIM3 0x0000000C 55 #define CPU_ITM_O_STIM4 0x00000010 58 #define CPU_ITM_O_STIM5 0x00000014 61 #define CPU_ITM_O_STIM6 0x00000018 64 #define CPU_ITM_O_STIM7 0x0000001C 67 #define CPU_ITM_O_STIM8 0x00000020 70 #define CPU_ITM_O_STIM9 0x00000024 73 #define CPU_ITM_O_STIM10 0x00000028 76 #define CPU_ITM_O_STIM11 0x0000002C 79 #define CPU_ITM_O_STIM12 0x00000030 82 #define CPU_ITM_O_STIM13 0x00000034 85 #define CPU_ITM_O_STIM14 0x00000038 88 #define CPU_ITM_O_STIM15 0x0000003C 91 #define CPU_ITM_O_STIM16 0x00000040 94 #define CPU_ITM_O_STIM17 0x00000044 97 #define CPU_ITM_O_STIM18 0x00000048 100 #define CPU_ITM_O_STIM19 0x0000004C 103 #define CPU_ITM_O_STIM20 0x00000050 106 #define CPU_ITM_O_STIM21 0x00000054 109 #define CPU_ITM_O_STIM22 0x00000058 112 #define CPU_ITM_O_STIM23 0x0000005C 115 #define CPU_ITM_O_STIM24 0x00000060 118 #define CPU_ITM_O_STIM25 0x00000064 121 #define CPU_ITM_O_STIM26 0x00000068 124 #define CPU_ITM_O_STIM27 0x0000006C 127 #define CPU_ITM_O_STIM28 0x00000070 130 #define CPU_ITM_O_STIM29 0x00000074 133 #define CPU_ITM_O_STIM30 0x00000078 136 #define CPU_ITM_O_STIM31 0x0000007C 139 #define CPU_ITM_O_TER 0x00000E00 142 #define CPU_ITM_O_TPR 0x00000E40 145 #define CPU_ITM_O_TCR 0x00000E80 148 #define CPU_ITM_O_LAR 0x00000FB0 151 #define CPU_ITM_O_LSR 0x00000FB4 166 #define CPU_ITM_STIM0_STIM0_W 32 167 #define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF 168 #define CPU_ITM_STIM0_STIM0_S 0 183 #define CPU_ITM_STIM1_STIM1_W 32 184 #define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF 185 #define CPU_ITM_STIM1_STIM1_S 0 200 #define CPU_ITM_STIM2_STIM2_W 32 201 #define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF 202 #define CPU_ITM_STIM2_STIM2_S 0 217 #define CPU_ITM_STIM3_STIM3_W 32 218 #define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF 219 #define CPU_ITM_STIM3_STIM3_S 0 234 #define CPU_ITM_STIM4_STIM4_W 32 235 #define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF 236 #define CPU_ITM_STIM4_STIM4_S 0 251 #define CPU_ITM_STIM5_STIM5_W 32 252 #define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF 253 #define CPU_ITM_STIM5_STIM5_S 0 268 #define CPU_ITM_STIM6_STIM6_W 32 269 #define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF 270 #define CPU_ITM_STIM6_STIM6_S 0 285 #define CPU_ITM_STIM7_STIM7_W 32 286 #define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF 287 #define CPU_ITM_STIM7_STIM7_S 0 302 #define CPU_ITM_STIM8_STIM8_W 32 303 #define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF 304 #define CPU_ITM_STIM8_STIM8_S 0 319 #define CPU_ITM_STIM9_STIM9_W 32 320 #define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF 321 #define CPU_ITM_STIM9_STIM9_S 0 336 #define CPU_ITM_STIM10_STIM10_W 32 337 #define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF 338 #define CPU_ITM_STIM10_STIM10_S 0 353 #define CPU_ITM_STIM11_STIM11_W 32 354 #define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF 355 #define CPU_ITM_STIM11_STIM11_S 0 370 #define CPU_ITM_STIM12_STIM12_W 32 371 #define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF 372 #define CPU_ITM_STIM12_STIM12_S 0 387 #define CPU_ITM_STIM13_STIM13_W 32 388 #define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF 389 #define CPU_ITM_STIM13_STIM13_S 0 404 #define CPU_ITM_STIM14_STIM14_W 32 405 #define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF 406 #define CPU_ITM_STIM14_STIM14_S 0 421 #define CPU_ITM_STIM15_STIM15_W 32 422 #define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF 423 #define CPU_ITM_STIM15_STIM15_S 0 438 #define CPU_ITM_STIM16_STIM16_W 32 439 #define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF 440 #define CPU_ITM_STIM16_STIM16_S 0 455 #define CPU_ITM_STIM17_STIM17_W 32 456 #define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF 457 #define CPU_ITM_STIM17_STIM17_S 0 472 #define CPU_ITM_STIM18_STIM18_W 32 473 #define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF 474 #define CPU_ITM_STIM18_STIM18_S 0 489 #define CPU_ITM_STIM19_STIM19_W 32 490 #define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF 491 #define CPU_ITM_STIM19_STIM19_S 0 506 #define CPU_ITM_STIM20_STIM20_W 32 507 #define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF 508 #define CPU_ITM_STIM20_STIM20_S 0 523 #define CPU_ITM_STIM21_STIM21_W 32 524 #define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF 525 #define CPU_ITM_STIM21_STIM21_S 0 540 #define CPU_ITM_STIM22_STIM22_W 32 541 #define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF 542 #define CPU_ITM_STIM22_STIM22_S 0 557 #define CPU_ITM_STIM23_STIM23_W 32 558 #define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF 559 #define CPU_ITM_STIM23_STIM23_S 0 574 #define CPU_ITM_STIM24_STIM24_W 32 575 #define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF 576 #define CPU_ITM_STIM24_STIM24_S 0 591 #define CPU_ITM_STIM25_STIM25_W 32 592 #define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF 593 #define CPU_ITM_STIM25_STIM25_S 0 608 #define CPU_ITM_STIM26_STIM26_W 32 609 #define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF 610 #define CPU_ITM_STIM26_STIM26_S 0 625 #define CPU_ITM_STIM27_STIM27_W 32 626 #define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF 627 #define CPU_ITM_STIM27_STIM27_S 0 642 #define CPU_ITM_STIM28_STIM28_W 32 643 #define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF 644 #define CPU_ITM_STIM28_STIM28_S 0 659 #define CPU_ITM_STIM29_STIM29_W 32 660 #define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF 661 #define CPU_ITM_STIM29_STIM29_S 0 676 #define CPU_ITM_STIM30_STIM30_W 32 677 #define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF 678 #define CPU_ITM_STIM30_STIM30_S 0 693 #define CPU_ITM_STIM31_STIM31_W 32 694 #define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF 695 #define CPU_ITM_STIM31_STIM31_S 0 705 #define CPU_ITM_TER_STIMENA31 0x80000000 706 #define CPU_ITM_TER_STIMENA31_BITN 31 707 #define CPU_ITM_TER_STIMENA31_M 0x80000000 708 #define CPU_ITM_TER_STIMENA31_S 31 713 #define CPU_ITM_TER_STIMENA30 0x40000000 714 #define CPU_ITM_TER_STIMENA30_BITN 30 715 #define CPU_ITM_TER_STIMENA30_M 0x40000000 716 #define CPU_ITM_TER_STIMENA30_S 30 721 #define CPU_ITM_TER_STIMENA29 0x20000000 722 #define CPU_ITM_TER_STIMENA29_BITN 29 723 #define CPU_ITM_TER_STIMENA29_M 0x20000000 724 #define CPU_ITM_TER_STIMENA29_S 29 729 #define CPU_ITM_TER_STIMENA28 0x10000000 730 #define CPU_ITM_TER_STIMENA28_BITN 28 731 #define CPU_ITM_TER_STIMENA28_M 0x10000000 732 #define CPU_ITM_TER_STIMENA28_S 28 737 #define CPU_ITM_TER_STIMENA27 0x08000000 738 #define CPU_ITM_TER_STIMENA27_BITN 27 739 #define CPU_ITM_TER_STIMENA27_M 0x08000000 740 #define CPU_ITM_TER_STIMENA27_S 27 745 #define CPU_ITM_TER_STIMENA26 0x04000000 746 #define CPU_ITM_TER_STIMENA26_BITN 26 747 #define CPU_ITM_TER_STIMENA26_M 0x04000000 748 #define CPU_ITM_TER_STIMENA26_S 26 753 #define CPU_ITM_TER_STIMENA25 0x02000000 754 #define CPU_ITM_TER_STIMENA25_BITN 25 755 #define CPU_ITM_TER_STIMENA25_M 0x02000000 756 #define CPU_ITM_TER_STIMENA25_S 25 761 #define CPU_ITM_TER_STIMENA24 0x01000000 762 #define CPU_ITM_TER_STIMENA24_BITN 24 763 #define CPU_ITM_TER_STIMENA24_M 0x01000000 764 #define CPU_ITM_TER_STIMENA24_S 24 769 #define CPU_ITM_TER_STIMENA23 0x00800000 770 #define CPU_ITM_TER_STIMENA23_BITN 23 771 #define CPU_ITM_TER_STIMENA23_M 0x00800000 772 #define CPU_ITM_TER_STIMENA23_S 23 777 #define CPU_ITM_TER_STIMENA22 0x00400000 778 #define CPU_ITM_TER_STIMENA22_BITN 22 779 #define CPU_ITM_TER_STIMENA22_M 0x00400000 780 #define CPU_ITM_TER_STIMENA22_S 22 785 #define CPU_ITM_TER_STIMENA21 0x00200000 786 #define CPU_ITM_TER_STIMENA21_BITN 21 787 #define CPU_ITM_TER_STIMENA21_M 0x00200000 788 #define CPU_ITM_TER_STIMENA21_S 21 793 #define CPU_ITM_TER_STIMENA20 0x00100000 794 #define CPU_ITM_TER_STIMENA20_BITN 20 795 #define CPU_ITM_TER_STIMENA20_M 0x00100000 796 #define CPU_ITM_TER_STIMENA20_S 20 801 #define CPU_ITM_TER_STIMENA19 0x00080000 802 #define CPU_ITM_TER_STIMENA19_BITN 19 803 #define CPU_ITM_TER_STIMENA19_M 0x00080000 804 #define CPU_ITM_TER_STIMENA19_S 19 809 #define CPU_ITM_TER_STIMENA18 0x00040000 810 #define CPU_ITM_TER_STIMENA18_BITN 18 811 #define CPU_ITM_TER_STIMENA18_M 0x00040000 812 #define CPU_ITM_TER_STIMENA18_S 18 817 #define CPU_ITM_TER_STIMENA17 0x00020000 818 #define CPU_ITM_TER_STIMENA17_BITN 17 819 #define CPU_ITM_TER_STIMENA17_M 0x00020000 820 #define CPU_ITM_TER_STIMENA17_S 17 825 #define CPU_ITM_TER_STIMENA16 0x00010000 826 #define CPU_ITM_TER_STIMENA16_BITN 16 827 #define CPU_ITM_TER_STIMENA16_M 0x00010000 828 #define CPU_ITM_TER_STIMENA16_S 16 833 #define CPU_ITM_TER_STIMENA15 0x00008000 834 #define CPU_ITM_TER_STIMENA15_BITN 15 835 #define CPU_ITM_TER_STIMENA15_M 0x00008000 836 #define CPU_ITM_TER_STIMENA15_S 15 841 #define CPU_ITM_TER_STIMENA14 0x00004000 842 #define CPU_ITM_TER_STIMENA14_BITN 14 843 #define CPU_ITM_TER_STIMENA14_M 0x00004000 844 #define CPU_ITM_TER_STIMENA14_S 14 849 #define CPU_ITM_TER_STIMENA13 0x00002000 850 #define CPU_ITM_TER_STIMENA13_BITN 13 851 #define CPU_ITM_TER_STIMENA13_M 0x00002000 852 #define CPU_ITM_TER_STIMENA13_S 13 857 #define CPU_ITM_TER_STIMENA12 0x00001000 858 #define CPU_ITM_TER_STIMENA12_BITN 12 859 #define CPU_ITM_TER_STIMENA12_M 0x00001000 860 #define CPU_ITM_TER_STIMENA12_S 12 865 #define CPU_ITM_TER_STIMENA11 0x00000800 866 #define CPU_ITM_TER_STIMENA11_BITN 11 867 #define CPU_ITM_TER_STIMENA11_M 0x00000800 868 #define CPU_ITM_TER_STIMENA11_S 11 873 #define CPU_ITM_TER_STIMENA10 0x00000400 874 #define CPU_ITM_TER_STIMENA10_BITN 10 875 #define CPU_ITM_TER_STIMENA10_M 0x00000400 876 #define CPU_ITM_TER_STIMENA10_S 10 881 #define CPU_ITM_TER_STIMENA9 0x00000200 882 #define CPU_ITM_TER_STIMENA9_BITN 9 883 #define CPU_ITM_TER_STIMENA9_M 0x00000200 884 #define CPU_ITM_TER_STIMENA9_S 9 889 #define CPU_ITM_TER_STIMENA8 0x00000100 890 #define CPU_ITM_TER_STIMENA8_BITN 8 891 #define CPU_ITM_TER_STIMENA8_M 0x00000100 892 #define CPU_ITM_TER_STIMENA8_S 8 897 #define CPU_ITM_TER_STIMENA7 0x00000080 898 #define CPU_ITM_TER_STIMENA7_BITN 7 899 #define CPU_ITM_TER_STIMENA7_M 0x00000080 900 #define CPU_ITM_TER_STIMENA7_S 7 905 #define CPU_ITM_TER_STIMENA6 0x00000040 906 #define CPU_ITM_TER_STIMENA6_BITN 6 907 #define CPU_ITM_TER_STIMENA6_M 0x00000040 908 #define CPU_ITM_TER_STIMENA6_S 6 913 #define CPU_ITM_TER_STIMENA5 0x00000020 914 #define CPU_ITM_TER_STIMENA5_BITN 5 915 #define CPU_ITM_TER_STIMENA5_M 0x00000020 916 #define CPU_ITM_TER_STIMENA5_S 5 921 #define CPU_ITM_TER_STIMENA4 0x00000010 922 #define CPU_ITM_TER_STIMENA4_BITN 4 923 #define CPU_ITM_TER_STIMENA4_M 0x00000010 924 #define CPU_ITM_TER_STIMENA4_S 4 929 #define CPU_ITM_TER_STIMENA3 0x00000008 930 #define CPU_ITM_TER_STIMENA3_BITN 3 931 #define CPU_ITM_TER_STIMENA3_M 0x00000008 932 #define CPU_ITM_TER_STIMENA3_S 3 937 #define CPU_ITM_TER_STIMENA2 0x00000004 938 #define CPU_ITM_TER_STIMENA2_BITN 2 939 #define CPU_ITM_TER_STIMENA2_M 0x00000004 940 #define CPU_ITM_TER_STIMENA2_S 2 945 #define CPU_ITM_TER_STIMENA1 0x00000002 946 #define CPU_ITM_TER_STIMENA1_BITN 1 947 #define CPU_ITM_TER_STIMENA1_M 0x00000002 948 #define CPU_ITM_TER_STIMENA1_S 1 953 #define CPU_ITM_TER_STIMENA0 0x00000001 954 #define CPU_ITM_TER_STIMENA0_BITN 0 955 #define CPU_ITM_TER_STIMENA0_M 0x00000001 956 #define CPU_ITM_TER_STIMENA0_S 0 974 #define CPU_ITM_TPR_PRIVMASK_W 4 975 #define CPU_ITM_TPR_PRIVMASK_M 0x0000000F 976 #define CPU_ITM_TPR_PRIVMASK_S 0 986 #define CPU_ITM_TCR_BUSY 0x00800000 987 #define CPU_ITM_TCR_BUSY_BITN 23 988 #define CPU_ITM_TCR_BUSY_M 0x00800000 989 #define CPU_ITM_TCR_BUSY_S 23 996 #define CPU_ITM_TCR_ATBID_W 7 997 #define CPU_ITM_TCR_ATBID_M 0x007F0000 998 #define CPU_ITM_TCR_ATBID_S 16 1008 #define CPU_ITM_TCR_TSPRESCALE_W 2 1009 #define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 1010 #define CPU_ITM_TCR_TSPRESCALE_S 8 1011 #define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 1012 #define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 1013 #define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 1014 #define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 1027 #define CPU_ITM_TCR_SWOENA 0x00000010 1028 #define CPU_ITM_TCR_SWOENA_BITN 4 1029 #define CPU_ITM_TCR_SWOENA_M 0x00000010 1030 #define CPU_ITM_TCR_SWOENA_S 4 1036 #define CPU_ITM_TCR_DWTENA 0x00000008 1037 #define CPU_ITM_TCR_DWTENA_BITN 3 1038 #define CPU_ITM_TCR_DWTENA_M 0x00000008 1039 #define CPU_ITM_TCR_DWTENA_S 3 1046 #define CPU_ITM_TCR_SYNCENA 0x00000004 1047 #define CPU_ITM_TCR_SYNCENA_BITN 2 1048 #define CPU_ITM_TCR_SYNCENA_M 0x00000004 1049 #define CPU_ITM_TCR_SYNCENA_S 2 1060 #define CPU_ITM_TCR_TSENA 0x00000002 1061 #define CPU_ITM_TCR_TSENA_BITN 1 1062 #define CPU_ITM_TCR_TSENA_M 0x00000002 1063 #define CPU_ITM_TCR_TSENA_S 1 1069 #define CPU_ITM_TCR_ITMENA 0x00000001 1070 #define CPU_ITM_TCR_ITMENA_BITN 0 1071 #define CPU_ITM_TCR_ITMENA_M 0x00000001 1072 #define CPU_ITM_TCR_ITMENA_S 0 1083 #define CPU_ITM_LAR_LOCK_ACCESS_W 32 1084 #define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF 1085 #define CPU_ITM_LAR_LOCK_ACCESS_S 0 1095 #define CPU_ITM_LSR_BYTEACC 0x00000004 1096 #define CPU_ITM_LSR_BYTEACC_BITN 2 1097 #define CPU_ITM_LSR_BYTEACC_M 0x00000004 1098 #define CPU_ITM_LSR_BYTEACC_S 2 1104 #define CPU_ITM_LSR_ACCESS 0x00000002 1105 #define CPU_ITM_LSR_ACCESS_BITN 1 1106 #define CPU_ITM_LSR_ACCESS_M 0x00000002 1107 #define CPU_ITM_LSR_ACCESS_S 1 1112 #define CPU_ITM_LSR_PRESENT 0x00000001 1113 #define CPU_ITM_LSR_PRESENT_BITN 0 1114 #define CPU_ITM_LSR_PRESENT_M 0x00000001 1115 #define CPU_ITM_LSR_PRESENT_S 0 1117 #endif // __CPU_ITM__
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