Instance: AUX_ANAIF
Component: AUX_ANAIF
Base address: 0x400C9000
AUX Analog Peripheral Control Module
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 9010 |
|
RO |
32 |
0x0000 0001 |
0x0000 0014 |
0x400C 9014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 9018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x400C 901C |
|
RW |
32 |
0x0000 0001 |
0x0000 0020 |
0x400C 9020 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x400C 9010 | Instance | 0x400C 9010 |
Description | ADC Control Configuration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | ||||||||||||||
13 | START_POL | Select active polarity for START_SRC event.
|
RW | 0 | ||||||||||||||
12:8 | START_SRC | Select ADC trigger event source from the asynchronous AUX event bus. Set START_SRC to NO_EVENT<n> if you want to trigger the ADC manually through ADCTRIG.START. |
RW | 0b0 0000 | ||||||||||||||
7:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||||||||||||||
1:0 | CMD | ADC interface command. Non-enumerated values are not supported. The written value is returned when read.
|
RW | 0b00 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x400C 9014 | Instance | 0x400C 9014 |
Description | ADC FIFO Status FIFO can hold up to four ADC samples. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
4 | OVERFLOW | FIFO overflow flag. 0: FIFO has not overflowed. 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO write pointer is static. It is not possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. |
RO | 0 | ||
3 | UNDERFLOW | FIFO underflow flag. 0: FIFO has not underflowed. 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO read pointer is static. Read returns the previous sample that was read. Flush FIFO to clear the flag. |
RO | 0 | ||
2 | FULL | FIFO full flag. 0: FIFO is not full, there is less than 4 samples in the FIFO. 1: FIFO is full, there are 4 samples in the FIFO. When the flag is set, it is not possible to add more samples to the ADC FIFO. An attempt to add samples sets the OVERFLOW flag. |
RO | 0 | ||
1 | ALMOST_FULL | FIFO almost full flag. 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL flag is also asserted in the latter case. 1: There are 3 samples in the FIFO, there is room for one more sample. |
RO | 0 | ||
0 | EMPTY | FIFO empty flag. 0: FIFO contains one or more samples. 1: FIFO is empty. When the flag is set, read returns the previous sample that was read and sets the UNDERFLOW flag. |
RO | 1 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C 9018 | Instance | 0x400C 9018 |
Description | ADC FIFO | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | ||
11:0 | DATA | FIFO data. Read: Get oldest ADC sample from FIFO. Write: Write dummy sample to FIFO. This is useful for code development when you do not have real ADC samples. |
RW | 0x000 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x400C 901C | Instance | 0x400C 901C |
Description | ADC Trigger | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | START | Manual ADC trigger. 0: No effect. 1: Single ADC trigger. To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT<n> to avoid conflict with event-driven ADC trigger. |
WO | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x400C 9020 | Instance | 0x400C 9020 |
Description | Current Source Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | RESET_N | ISRC reset control. 0: ISRC drives 0 uA. 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. |
RW | 1 |
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