Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / outut |
0x7 |
OPENSRC_INV |
Open Source
Inverted input/output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO0
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO1
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO2
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO3
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO4
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO5
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO6
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO7
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO8
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO9
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO10
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO11
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO12
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO13
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO14
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO15
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0001 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO16
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0010 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO17
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO18
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO19
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO20
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO21
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO22
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO23
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO24
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO25
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO26
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO27
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO28
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO29
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO30
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
HYST_EN |
0: Input hysteresis disable
1: Input hysteresis enable |
RW |
0 |
29
|
IE |
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. |
RW |
0 |
28:27
|
WU_CFG |
If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
RW |
0b00 |
26:24
|
IOMODE |
IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value |
ENUM Name |
Description |
0x0 |
NORMAL |
Normal input / output |
0x1 |
INV |
Inverted input / ouput |
0x4 |
OPENDR |
Open Drain,
Normal input / output |
0x5 |
OPENDR_INV |
Open Drain
Inverted input / output |
0x6 |
OPENSRC |
Open Source
Normal input / output |
0x7 |
OPENSRC_INV |
Open Source
Inverted input / output |
|
RW |
0b000 |
23:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0b0 0000 |
18
|
EDGE_IRQ_EN |
0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
RW |
0 |
17:16
|
EDGE_DET |
Enable generation of edge detection events on this IO
Value |
ENUM Name |
Description |
0x0 |
NONE |
No edge detection |
0x1 |
NEG |
Negative edge detection |
0x2 |
POS |
Positive edge detection |
0x3 |
BOTH |
Positive and negative edge detection |
|
RW |
0b00 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14:13
|
PULL_CTL |
Pull control
Value |
ENUM Name |
Description |
0x1 |
DWN |
Pull down |
0x2 |
UP |
Pull up |
0x3 |
DIS |
No pull |
|
RW |
0b11 |
12
|
SLEW_RED |
0: Normal slew rate
1: Enables reduced slew rate in output driver. |
RW |
0 |
11:10
|
IOCURR |
Selects IO current mode of this IO.
Value |
ENUM Name |
Description |
0x0 |
2MA |
Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO |
0x1 |
4MA |
High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO |
0x2 |
4_8MA |
Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
|
RW |
0b00 |
9:8
|
IOSTR |
Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value |
ENUM Name |
Description |
0x0 |
AUTO |
Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) |
0x1 |
MIN |
Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) |
0x2 |
MED |
Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) |
0x3 |
MAX |
Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
|
RW |
0b00 |
7:6
|
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
5:0
|
PORT_ID |
Selects usage for DIO31
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
Value |
ENUM Name |
Description |
0x0 |
GPIO |
General Purpose IO |
0x7 |
AON_CLK32K |
AON 32 KHz clock (SCLK_LF) |
0x8 |
AUX_IO |
AUX IO |
0x9 |
SSI0_RX |
SSI0 RX |
0xA |
SSI0_TX |
SSI0 TX |
0xB |
SSI0_FSS |
SSI0 FSS |
0xC |
SSI0_CLK |
SSI0 CLK |
0xD |
I2C_MSSDA |
I2C Data |
0xE |
I2C_MSSCL |
I2C Clock |
0xF |
UART0_RX |
UART0 RX |
0x10 |
UART0_TX |
UART0 TX |
0x11 |
UART0_CTS |
UART0 CTS |
0x12 |
UART0_RTS |
UART0 RTS |
0x17 |
PORT_EVENT0 |
PORT EVENT 0
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x18 |
PORT_EVENT1 |
PORT EVENT 1
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x19 |
PORT_EVENT2 |
PORT EVENT 2
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1A |
PORT_EVENT3 |
PORT EVENT 3
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1B |
PORT_EVENT4 |
PORT EVENT 4
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1C |
PORT_EVENT5 |
PORT EVENT 5
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1D |
PORT_EVENT6 |
PORT EVENT 6
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x1E |
PORT_EVENT7 |
PORT EVENT 7
Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc |
0x20 |
CPU_SWV |
CPU SWV |
0x21 |
SSI1_RX |
SSI1 RX |
0x22 |
SSI1_TX |
SSI1 TX |
0x23 |
SSI1_FSS |
SSI1 FSS |
0x24 |
SSI1_CLK |
SSI1 CLK |
0x25 |
I2S_AD0 |
I2S Data 0 |
0x26 |
I2S_AD1 |
I2S Data 1 |
0x27 |
I2S_WCLK |
I2S WCLK |
0x28 |
I2S_BCLK |
I2S BCLK |
0x29 |
I2S_MCLK |
I2S MCLK |
0x2E |
RFC_TRC |
RF Core Trace |
0x2F |
RFC_GPO0 |
RF Core Data Out 0 |
0x30 |
RFC_GPO1 |
RF Core Data Out 1 |
0x31 |
RFC_GPO2 |
RF Core Data Out 2 |
0x32 |
RFC_GPO3 |
RF Core Data Out 3 |
0x33 |
RFC_GPI0 |
RF Core Data In 0 |
0x34 |
RFC_GPI1 |
RF Core Data In 1 |
0x35 |
RFC_SMI_DL_OUT |
RF Core SMI Data Link Out |
0x36 |
RFC_SMI_DL_IN |
RF Core SMI Data Link In |
0x37 |
RFC_SMI_CL_OUT |
RF Core SMI Command Link Out |
0x38 |
RFC_SMI_CL_IN |
RF Core SMI Command Link In |
|
RW |
0b00 0000 |