C2000Ware Digital Power SDK  5.06.00.00
PMP23126 - 3kW Phase-shifted Full Bridge With Active Clamp

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Target Applications

  • Server & Telecom power supplies
  • Industrial supplies

Features & Specification

  • > 270-W/in³ power density in an x-y dimension of less than 68 mm x 102 mm and max height of 32 mm
  • Peak efficiency of 97.74%
  • 100kHz switching frequency
  • Active clamp for minimizing voltage stress on SR MOSFETs enabling use of better FoM devices
PMP23126 Design Specification
Vin (Min) (V) 350
Vin (Max) (V) 410
Vout (Nom) (V) 12
Iout (Max) (A) 250
Output Power (W) 3000
Isolated/Non-Isolated Isolated
Input Type DC
Topology Full Bridge - Phase Shifted

Description

This reference design is a GaN-based 3kW phase-shifted full bridge (PSFB) targeting maximum power density.

The design has an active clamp to minimize voltage stress on the secondary synchronous rectifier MOSFETs enabling use of lower voltage-rating MOSFETs with better figure-of-merit (FoM). PMP23126 uses our 30mΩ GaN on the primary side and silicon MOSFETs on the secondary side. The LMG3522 top-side cooled GaN with integrated driver and protection enables higher efficiency by maintaining ZVS over a wider range of operation compared to Si MOSFET. The PSFB operates at 100 kHz and achieves a peak efficiency of 97.74%.

This design can be run on a C2000™ TMS320F280039C or TMS320F280049C or TMS320F2800157 real-time MCU.

Additionally, PMP23126 supports MATLAB's model-based design for a GUI-based system design, simulation, and automatic code generation. Host communications are enabled using UART/SCI to tune and monitor control and voltage parameters in runtime. Refer here for a brief overview of the model design.

MATLAB® is a registered trademark of MathWorks®

Software Device Usage
Device F28003x F28003x
(Model-based design)
F28004x F280015x
Memory Consumption RAM: 4.3KB
Flash: 7.2KB
RAM: 8.3KB
Flash: 8.2KB
RAM: 4.7KB
Flash: 7.7KB
RAM: 4.8KB
Flash: 7.7KB
MIPS Consumption 70 MIPS 80 MIPS 70 MIPS

70 MIPS

C28x and/or CLA C28x C28x C28x C28x
# of PWM Channels
(EPWM or HRPWM)
5 EPWM Channel
# of ADC Channels 3 ADC Channel
(2 ADCA + 1 ADCB)
6 ADC Channel
(2 ADCA + 4 ADCB)
3 ADC Channel
(2 ADCA + 1 ADCC)
# of CMPSS 1
Control Methodology Inner peak current mode loop for current regulation with integrator saturated PI Control for voltage control.
ISR Frequency ISR1: 100kHz ISR1(Control): 100kHz [PCMC:200kHz]
ISR2(SCI): Baudrate = 5M
ISR1: 100kHz ISR1: 100kHz
PMP23126 EVM Board
C2000 MCU interface to PCMC PSFB DC/DC Power Stage Diagram

Relevant Links

Useful links regarding the reference design are provided below:

Note
To import and evaluate CCS project using the button above, please access the current page via Resource Explorer from CCS, or CCS Cloud. (go to View->Resource Explorer)

Steps to Run the Example

  • It's strongly recommended to first read through the User Guide/Software Guide for any specific setup instructions and hazard warnings before proceeding.
  • To import CCS projects, either import via the button above or mannually select the file directory where this solutions resides.
  • Build the project within the CCS project menu, then launch a CCS debug session and run the executable.

Release Notes

Shown below lists all the software revision history for this reference design:

Software Revision In SDK Release Changelog
v1.00.00 4.02.00.00 First release, on F28004x devices in C2000Ware Digital Power SDK
v1.01.00 4.03.00.00 Bug fixes & Enhancements:
  • Frequency reduction for zero load stability
  • Dynamic testing per mCPRS
  • Updates compiler version
v2.00.00 4.04.00.00 New device support:
  • Added F280015x as a supported device
v3.00.00 5.03.00.00 New device support & Enhancements:
  • Added F28003x as a supported device
  • Added Burst Mode
  • Removed Frequency Reduction Mode
v3.00.01 5.04.00.00 Changes & Enhancements:
  • Added reference links to release notes within the solution
v3.01.00 5.05.00.00 Changes & Enhancements:
  • Added F28003x model-based design support and related documentation
v3.01.01 5.05.01.00 Patch fixes:
  • Fixes an issue with the included Simulink file that is causing the source to be no longer interpretable

Hardware design files

For EVM design files such as schematics, BOM, PCB layouts & assembly files, please visit TI design webpage from the link above.

Help and Support

For additional help and support, please visit E2E™ design support forum