CLOCKS

Table of Contents

• Features Supported
• SysConfig Features
• Example Usage

Features Supported

The SOC driver offers an API called SOC_clocksEnable that sets up and activates both PLL_DIG and ADPLL and configures r5, DSP clocks along with their multiplexers (MUXes).

Note

DSP frequency configured in SysConfig only configures the MUX for DSP. However, powering on the DSP is handled by RBL. Setting DSP frequency doesnot mean DSP is powered on.

This API configures:

• PLLDIG is configured to run at 400MHz and post divider is configured as 2 to get 200MHz.
• ADPLL is configured as below:
  • 1600MHz - When DSP frequency is 400MHz or XTAL(40MHz).
  • 1800MHZ - When DSP frequency is 450MHz or 360MHz.
• HS Divider Clock Out 0 is configured as source to fast clock 1 and is configured to 200MHz.
• HS Divider Clock Out 1 is configured as source to fast clock 2 and is configured as below:
  • 400MHz - When DSP frequency is 400MHz.
  • 450MHZ - When DSP frequency is 450MHz.
  • 360MHZ - When DSP frequency is 360MHz.
• If DSP frequency is XTAL(40MHz), HS Divider Clock Out 1 and fast clock 1 are not configured.
• HS Divider Clock Out 2 to 50MHz.
  • NOTE: This clock cannot be configured more than 600MHz hence ADPLL is used as the source clock for LVDS. However, though ADPLL is the source of LVDS, this clock has to be enabled for LVDS by design.
• HS Divider Clock Out 3 is configured as source to DSS domain and is configured to 200MHz.
• Fast clock 1 with post div 1 is selected as a source clock for R5 core. Hence, R5 core runs at 200MHz.
• DSP core clock source is set to:
  • Fast Clock 2 with Div 1: When DSP frequency is 400MHz or 450MHz or 360MHz.
  • XTAL(40MHz) with Div 1: When DSP frequency is XTAL(40MHz)

SysConfig Features

The SysCfg offers the ability to modify the clock speed of the DSP, as depicted in the below figure.

Example Usage

Include the below file to access the APIs

#include <drivers/soc.h>

Configure Clocks

int32_t SOC_clocksEnable(uint32_t dspFreqHz)
{
    int32_t status = SystemP_SUCCESS;
 
    SOC_RcmADPllFoutFreqId adpllFreqId;
    SOC_RcmDspClockSource  dspClkSource;
    uint32_t hsdiv0FreqHz;
    uint32_t hsdiv1FreqHz;
    uint32_t hsdiv2FreqHz;
    uint32_t hsdiv3FreqHz;
 
    hsdiv0FreqHz = SOC_HsDivClkOut_200MHzFreq;
    hsdiv2FreqHz = SOC_HsDivClkOut_50MHzFreq;
    hsdiv3FreqHz = SOC_HsDivClkOut_200MHzFreq;
 
    if(dspFreqHz == SOC_C66CoreFreq400MHz)
    {
        adpllFreqId = SOC_RcmADPllFoutFreqId_CLK_1600MHZ;
        hsdiv1FreqHz = SOC_HsDivClkOut_400MHzFreq;
        dspClkSource = SOC_RcmDspClockSource_FAST_CLK2;
    }
    else if(dspFreqHz == SOC_C66CoreFreq450MHz)
    {
        adpllFreqId = SOC_RcmADPllFoutFreqId_CLK_1800MHZ;
        hsdiv1FreqHz = SOC_HsDivClkOut_450MHzFreq;
        dspClkSource = SOC_RcmDspClockSource_FAST_CLK2;
    }
    else if(dspFreqHz == SOC_C66CoreFreq360MHz)
    {
        adpllFreqId = SOC_RcmADPllFoutFreqId_CLK_1800MHZ;
        hsdiv1FreqHz = SOC_HsDivClkOut_360MHzFreq;
        dspClkSource = SOC_RcmDspClockSource_FAST_CLK2;
    }
    else /* When DSP frequency is set to OSC(40MHz) */
    {
        adpllFreqId = SOC_RcmADPllFoutFreqId_CLK_1600MHZ;
        dspClkSource = SOC_RcmDspClockSource_OSC_CLK;
    }
 
    /* Configure PLLDIG out with 400MHz and post divider as 2 to get 200MHz */
    SOC_rcmCoreDigPllConfig(SOC_RcmPllFoutFreqId_CLK_400MHZ, 2U);
 
    /* Configure the ADPLL out to:
     * 1600MHz - When DSP frequency is 400MHz or OSC(40MHz)
     * 1800MHZ - When DSP frequency is 450MHz or 360MHz 
     */
    SOC_rcmCoreADPLLConfig(adpllFreqId);
 
    /* Configuring HS Divider Clock Out 0 to 200MHz */
    SOC_rcmConfigureHsDividerClocks(SOC_RcmADPllHsDivClkOut0,SOC_RCM_FREQ_HZ2MHZ(hsdiv0FreqHz), gSocRcmADPLLFreqId2FOutMap[adpllFreqId]);
    
    /* Configuring HS Divider Clock Out 2 to 50MHz */
    SOC_rcmConfigureHsDividerClocks(SOC_RcmADPllHsDivClkOut2,SOC_RCM_FREQ_HZ2MHZ(hsdiv2FreqHz), gSocRcmADPLLFreqId2FOutMap[adpllFreqId]);
    
    /* Configuring HS Divider Clock Out 3 to 200MHz*/
    SOC_rcmConfigureHsDividerClocks(SOC_RcmADPllHsDivClkOut3,SOC_RCM_FREQ_HZ2MHZ(hsdiv3FreqHz), gSocRcmADPLLFreqId2FOutMap[adpllFreqId]);
 
    /* Select HS Divider Clock Out 0 as source for Fast Clock 1 which is 200MHz */
    SOC_TopssSelFclk1(SOC_TopssFclk1Source_ADPLL_HSDIV_CLK0);
 
    /* When the DSP frequency is not 40MHz (OSC), configure Fast Clock 2 and HS Divider Clock Out 1. However, if the DSP frequency is 40MHz (OSC), do not configure these clocks, as the OSC clock will be used directly as the source for the DSP instead of Fast Clock 2. */
    if(dspFreqHz != SOC_RCM_XTAL_CLK_40MHZ)
    {
        /* Configuring HS Divider Clock Out 1 to:
        * 400MHz - When DSP frequency is 400MHz 
        * 450MHZ - When DSP frequency is 450MHz
        * 360MHZ - When DSP frequency is 360MHz
        */
        SOC_rcmConfigureHsDividerClocks(SOC_RcmADPllHsDivClkOut1,SOC_RCM_FREQ_HZ2MHZ(hsdiv1FreqHz), gSocRcmADPLLFreqId2FOutMap[adpllFreqId]);
 
        /* Select ADPLL HDIV CLK 1 as Source for Fast Clock 2 */
        SOC_TopssSelFclk2(SOC_TopssFclk2Source_ADPLL_HSDIV_CLK1);
    }
    
    /* Configure R5 Clock source to Fast Clock 1 with Div 1. This configures core at 200MHz */
    SOC_rcmSetR5Clock(SOC_R5FCoreFreq200MHz, SOC_FastClk1Freq200MHz, SOC_RcmR5ClockSource_FAST_CLK1);
 
    /* Configure DSP Clock source to:
     * Fast Clock 2 with Div 1: When DSP frequency is 400MHz or 450MHz or 360MHz
     * OSC with Div 1: When DSP frequency is OSC(40MHz) */
    SOC_rcmSetDSPClock(dspFreqHz, dspFreqHz, dspClkSource);
 
    /* Configure DSS Clock source to HS DIV CLOCK3 with Div 1. This configures core at 200Mhz */
    SOC_rcmSetDSSClock(SOC_DSSFreq200MHz,hsdiv3FreqHz, SOC_RcmDssClockSource_HSDIVCLKOUT3_CLK);
 
    return status;
}