soc_rcm.h

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#ifndef SOC_RCM_XWRL684X_H_
#define SOC_RCM_XWRL684X_H_
#endif
 
#include <stdint.h>
#include <kernel/dpl/SystemP.h>
 
#include <stdint.h>
 
typedef struct SOC_RcmDeviceFreqConfig_s
{
    uint32_t           dspFreqHz;
    uint32_t           r5FreqHz;
    uint32_t           sysClkFreqHz;
} SOC_RcmDeviceFreqConfig;
 
typedef enum SOC_RcmEfusePkgType_e
{
    SOC_RCM_EFUSE_DEVICE_PKG_TYPE_ETS
} SOC_RcmEfusePkgType;
 
typedef enum SOC_RcmAppCtrlClock_e {
    SOC_RcmAppCtrlClockEnable,
    SOC_RcmAppCtrlClockDisable
 
}SOC_RcmAppCtrlClock;
 
typedef enum SOC_TopssFclk1Source_e
{
    SOC_TopssFclk1Source_PLLDIG,
    SOC_TopssFclk1Source_ADPLL_HSDIV_CLK0,
    SOC_TopssFclk1Source_APLL_CLK_DIV4,
    SOC_TopssFclk1Source_APLL_CLK_DIV5,
    SOC_TopssFclk1Source_SLOW_CLK,
    SOC_TopssFclk1Source_MAX_VALUE = 0xFFFFFFFFu,
} SOC_TopssFclk1Source;
 
typedef enum SOC_TopssFclk2Source_e
{
    SOC_TopssFclk2Source_PLLDIG,
    SOC_TopssFclk2Source_ADPLL_HSDIV_CLK1,
    SOC_TopssFclk2Source_APLL_CLK_DIV2,
    SOC_TopssFclk2Source_SLOW_CLK,
    SOC_TopssFclk2Source_MAX_VALUE = 0xFFFFFFFFu,
} SOC_TopssFclk2Source;
 
typedef enum SOC_RcmR5ClockSource_e
{
    SOC_RcmR5ClockSource_OSC_CLK,
    SOC_RcmR5ClockSource_SLOW_CLK,
    SOC_RcmR5ClockSource_FAST_CLK1,
    SOC_RcmR5ClockSource_MAX_VALUE = 0xFFFFFFFFu,
} SOC_RcmR5ClockSource;
 
typedef enum SOC_RcmDspClockSource_e
{
    SOC_RcmDspClockSource_OSC_CLK,
    SOC_RcmDspClockSource_FAST_CLK2,
    SOC_RcmDspClockSource_SLOW_CLK,
    SOC_RcmDspClockSource_MAX_VALUE = 0xFFFFFFFFu,
} SOC_RcmDspClockSource;
 
typedef enum SOC_RcmDssClockSource_e
{
    SOC_RcmDssClockSource_OSC_CLK,
    SOC_RcmDssClockSource_FAST_CLK1,
    SOC_RcmDssClockSource_HSDIVCLKOUT3_CLK,
    SOC_RcmDssClockSource_SLOW_CLK,
    SOC_RcmDssClockSource_MAX_VALUE = 0xFFFFFFFFu,
} SOC_RcmDssClockSource;
 
typedef enum SOC_RcmTopssClockSource_e
{
    SOC_RcmTopssClockSource_OSC_CLK = 0x000U,
    SOC_RcmTopssClockSource_SLOW_CLK = 0x111U,
    SOC_RcmTopssClockSource_FAST_CLK1 = 0x333U,
    SOC_RcmTopssClockSource_MAX_VALUE = 0xFFFFFFFFu,
} SOC_RcmTopssClockSource;
 
typedef enum SOC_RcmPeripheralClockGate_e {
    SOC_RcmPeripheralClockGateEnable,
    SOC_RcmPeripheralClockGateDisable
 
}SOC_RcmPeripheralClockGate;
 
typedef enum SOC_RcmPeripheralClockSource_e
{
    SOC_RcmPeripheralClockSource_OSC_CLK,
    SOC_RcmPeripheralClockSource_OSC_CLKX2,
    SOC_RcmPeripheralClockSource_SLOW_CLK,
    SOC_RcmPeripheralClockSource_FAST_CLK1,
    SOC_RcmPeripheralClockSource_FAST_CLK2,
    SOC_RcmPeripheralClockSource_CAN_CLK,
    SOC_RcmPeripheralClockSource_PLL_DIG_CLK,
} SOC_RcmPeripheralClockSource;
 
 
typedef enum SOC_RcmPeripheralId_e
{
    SOC_RcmPeripheralId_APPSS_RTI,
    SOC_RcmPeripheralId_APPSS_WDT,
    SOC_RcmPeripheralId_APPSS_QSPI,
    SOC_RcmPeripheralId_APPSS_MCSPIA,
    SOC_RcmPeripheralId_APPSS_MCSPIB,
    SOC_RcmPeripheralId_APPSS_I2C,
    SOC_RcmPeripheralId_APPSS_LIN,
    SOC_RcmPeripheralId_APPSS_UARTA,
    SOC_RcmPeripheralId_APPSS_UARTB,
    SOC_RcmPeripheralId_APPSS_MCANA,
    SOC_RcmPeripheralId_APPSS_MCANB,
    SOC_RcmPeripheralId_APPSS_ESM,
    SOC_RcmPeripheralId_APPSS_EDMA,
    SOC_RcmPeripheralId_APPSS_CRC,
    SOC_RcmPeripheralId_APPSS_PWM,
    SOC_RcmPeripheralId_APPSS_GIO,
    SOC_RcmPeripheralId_DSS_HWA,
    SOC_RcmPeripheralId_DSS_RTIA,
    SOC_RcmPeripheralId_DSS_WDT,
    SOC_RcmPeripheralId_DSS_EDMA,
    SOC_RcmPeripheralId_DSS_SCIA,
    SOC_RcmPeripheralId_DSS_ADCBUF,
} SOC_RcmPeripheralId;
 
typedef enum SOC_RcmPllFoutFreqId_e
{
    SOC_RcmPllFoutFreqId_CLK_400MHZ,
    SOC_RcmPllFoutFreqId_MAX_VALUE = 0xFFFFFFFFu,
} SOC_RcmPllFoutFreqId;
 
typedef enum SOC_RcmADPllFoutFreqId_e
{
    SOC_RcmADPllFoutFreqId_CLK_1600MHZ,
    SOC_RcmADPllFoutFreqId_CLK_1800MHZ,
    SOC_RcmADPllFoutFreqId_MAX_VALUE = 0xFFFFFFFFu,
}SOC_RcmADPllFoutFreqId;
 
typedef enum SOC_RcmADPllHsDivClkOut_e
{
    SOC_RcmADPllHsDivClkOut0,
    SOC_RcmADPllHsDivClkOut1,
    SOC_RcmADPllHsDivClkOut2,
    SOC_RcmADPllHsDivClkOut3,
}SOC_RcmADPllHsDivClkOut;
 
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
static void SOC_rcmGetClkSrcAndDivReg(SOC_RcmPeripheralId PeriphID,
                               SOC_RcmPeripheralClockSource clkSource, uint16_t *clkSrcVal,
                               volatile uint32_t **clkSrcReg,
                               volatile uint32_t **clkdDivReg);
 
static int32_t SOC_rcmGetClkSrcAndDivValue(SOC_RcmPeripheralId PeriphID,
                                        SOC_RcmPeripheralClockSource *clkSource,
                                        volatile uint32_t *clkDiv);
 
static void SOC_rcmProgDigPllCoreDivider(uint8_t inputClockDiv,uint16_t multiplier);
 
int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphID,
                                  SOC_RcmPeripheralClockSource clkSource,
                                  uint32_t freqHz);
 
void SOC_rcmCoreDigPllConfig(SOC_RcmPllFoutFreqId, uint8_t);
void SOC_rcmCoreADPLLConfig(SOC_RcmADPllFoutFreqId outFreqId);
static void SOC_rcmConfigurePllDsp(uint16_t trimVal);
// void SOC_rcmDspPllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
// static SOC_RcmXtalFreqId SOC_rcmGetXTALFrequency(void);
static uint32_t SOC_rcmGetR5InFrequency(void);
// static uint32_t SOC_rcmGetFreq(SOC_RcmClockSrcId clkSrcId);
// static uint32_t SOC_rcmGetFreqLeafNode(SOC_RcmClockSrcId clkSrcId);
static uint32_t SOC_rcmGetModuleClkDivVal(uint32_t inFreq, uint32_t outFreq);
static uint32_t SOC_rcmGetModuleClkDivRegVal(uint32_t moduleClkDivVal);
static uint32_t SOC_rcmGetModuleClkDivFromRegVal(uint32_t moduleClkDivRegVal);
// static uint16_t SOC_rcmGetDspTrimVal(void)
int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t inpFreqHz, SOC_RcmR5ClockSource clkSrc);
int32_t SOC_rcmSetDSPClock(uint32_t dspFreqHz, uint32_t inpFreqHz, SOC_RcmDspClockSource clkSrc);
int32_t SOC_rcmSetDSSClock(uint32_t dssFreqHz, uint32_t inpFreqHz, SOC_RcmDssClockSource clkSrc);
uint32_t SOC_rcmGetR5Clock(void);
uint32_t SOC_rcmGetPeripheralClock(SOC_RcmPeripheralId periphID);
static uint32_t SOC_rcmGetPeripheralClockFrequency(SOC_RcmPeripheralClockSource clkSource);
static uint32_t SOC_rcmGetCoreFout(uint32_t Finp, uint32_t div2flag);
static uint32_t SOC_rcmDigPllGetFOut(uint32_t Finp, uint32_t N, uint32_t M,uint32_t div2flag);
void SOC_rcmGetDeviceFrequency(SOC_RcmDeviceFreqConfig *deviceFreqEfuseCfg);
void SOC_rcmGetPackageType(SOC_RcmEfusePkgType *deviceTypeEfuse);
void SOC_rcmCoreDigPllDisable(void);
void SOC_rcmR5ConfigLockStep(void);
void SOC_rcmSwitchR5Clock(SOC_RcmR5ClockSource clkSrc, uint32_t divVal);
uint32_t SOC_rcmGetDspClock(void);
void SOC_TopssSelFclk1(SOC_TopssFclk1Source clkSrc);
void SOC_TopssSelFclk2(SOC_TopssFclk2Source clkSrc);
int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockGate enable);
void SOC_rcmConfigureHsDividerClocks (SOC_RcmADPllHsDivClkOut HsDividerClkOutSel, uint32_t foutMHz, uint32_t finMHz );
void SOC_rcmDisableADPLL();
void SOC_rcmEnableOscx2Clk();
int32_t SOC_rcmSetAPPCtrlClock(SOC_RcmAppCtrlClock enable);
int32_t SOC_rcmSetTopssClock(uint32_t topssFreqHz, uint32_t inpFreqHz, SOC_RcmTopssClockSource clkSrc);