Hardware Crypto Accelerators#

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This module explains how Hardware Crypto Accelerators helps in offloading the CPU and effectively utilizing the hardware.

Introduction#

DTHE stands for Data Transform and Hashing Engine. This module is a wrapper on top of the Crypto IP with some additional capability, including CRC and Checksum

Features supported in AM26x devices#

DTHE provides the following features:

  • Symmetric encryption and decryption

    • AES: 128, 192, and 256 bit keys

    • Cipher modes ECB, CTR, CBC, GCM, CCM, F9, F8, XTS, CFB, ICM, CTR, CBC-MAC, CMAC based on AES

  • Asymmetric cryptography

    • High performance PKA (public key engine) for large vector math/modulus operation

    • RSA2048, RSA3092, RSA4096

    • ECC (accelerated using PKA module)

  • Hashing

    • MD5, SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512

    • HMAC-SHA256, HMAC-SHA512 keyed hashing

  • Random number generator

    • 128 bit True random number generator

    • 128 bit Deterministic random bit generator

  • Supports these CRC functions:

    • Bisync, Modbus, USB, ANSI X3.28, many others; also known as CRC-16 and CRC-16-ANSI : (x^16+x^15+x^2+1)

    • CRC16-/X.25 with Polynomial 0x1021 : (x^16+x^12+x^5+1)

    • CRC32-IEEE/MPEG2/Hamming with Polynomial 0x4C11DB7 : (x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2 + x+1)

    • CRC32-G.Hn/CRC32C with Polynomial 0x1EDC6F41 : (x^32+x^28+x^27+x^26+x^25+x^23+x^22+x^20+x^19+x^18+x^14+x^13+ x^11+x^10+x^9+x^8+x^6+1)

  • Supports TCP/UDP CheckSum (CSUM)

Link to SW Driver Support documentation

Additional Support#

DMA support#

The AES and SHA engine also have DMA IF as an optional feature. The AM263x and AM263Px has an EDMA on the SoC which can be used with the engines so the CPU can offload the copy from memory to engine as well as the copy from engine to memory. Not only it will save the CPU cycles for redundant copy operations but will also improve the performance of the Cryptographic operations. TBD : Link to More details on DMA support

Accessing the Hardware Cryptographic Accelerators#

The cryptographic accelerators can be accessed by both HSM(M4) cores as well as Application (R5F) cores. In HS-FS devices, for development ease-of-use, TIFS-MCU firmware opens the firewalls for DTHE so the R5F Applications can access the same. Link to Examples of DTHE for Application Cores.

TIFS-MCU firmware opens the firewalls for AES and SHA engine only. TRNG and PKA are single context engines so by default the access remains with HSM(M4) only.

## I intend to use AES-CTR-128 and key for this operation is a session key which I can store in non-secure memory like Application MSRAM/On Chip SRAM ? The IPC latency should be avoided/minimized. How should this use case be taken into consideration ? > DTHE hardware can be accessed by Application R5 CPUs via Public Context. - [x] R5F CPUs to directly access the the AES engine, this will eliminate the IPC latency. Also the key is temporary which is okay for this use case. - [ ] IPC latency cannot be avoided as R5F CPUs need to use IPC to interact with HSM and access the DTHE. - [ ] HSM and R5F CPUs cannot access the DTHE, hence this use case is not valid.

Accessing TRNG hardware / Get Random Number Service#

As mentioned above TIFS-MCU firewalls the TRNG and PKA hardware accelerators for public cores to directly access the same. However in order to avail the features of the hardware accelerators, TIFS-MCU provides an HSM service called Get Random Number Service.

Service Information

HSM Communication

Link

HSM Service for GetRandomNum

HSM Client

LINK

HSM Services for TRNG Services

HSM Server

LINK

Note

Services related to PKA are not yet available.