Analog-to-Digital Converter (ADC)#
C2000 devices support multiple analog-to-digital converters (ADCs) in 12-bit mode and/or 16-bit mode. Each ADC module has a single sample-and-hold (S/H) circuit and using multiple ADC modules enables simultaneous sampling or independent operation (sequential sampling). The ADC module is implemented using a successive approximation (SAR) type ADC.
ADC Module
Not all C2000 devices have the same ADC type or capabilities. Refer to the C2000 Real-Time Microcontrollers Peripheral Reference Guide to find your specific device’s ADC type and feature set.
Differential Signal Mode#
In this mode, a pair of pins (positive input ADCINxP and negative input ADCINxN) are sampled and the input applied to the converter is the difference between the two pins (ADCINxP – ADCINxN). A benefit of differential signaling mode is the ability to cancel noise that may be introduced common to both inputs.
Single-Ended Signal Mode#
In single-ended mode, a single pin (ADCINx) is sampled and applied to the input of the converter.
Start of Conversion (SOC)#
The ADC triggering and conversion sequencing is managed by a series of start-of-conversion (SOCx) configuration registers.
Each SOCx register configures a single channel conversion, where the SOCx register specifies the trigger source that starts the conversion, the channel to convert, and the acquisition sample window duration.
Multiple SOCx registers can be configured for the same trigger, channel, and/or acquisition window. Configuring multiple SOCx registers to use the same trigger will cause that trigger to perform a sequence of conversions, and configuring multiple SOCx registers for the same trigger and channel can oversample the signal.
The various trigger sources that can be used to start an ADC conversion include the General Purpose Timers, the ePWM modules, an external pin, and by software. Also, the flag setting of either ADCINT1 or ADCINT2 can be configured as a trigger source which can be used for continuous conversion operation.
The ADC interrupt logic can generate up to four interrupts. The results for SOC 0 through 15 appear in result registers 0 through 15, respectively.
Note:
The diagram above is for the F28004x, other devices might have different trigger sources. Please refer to the ‘ADC Triggering’ section of this module for more information.
The figure above is a conceptual view highlighting a single ADC start-of-conversion functional flow from triggering to interrupt generation. This figure is replicated 16 times and the Driverlib functions highlight the sections that they modify.
ADC Triggering#
Trigger Sources:
As discussed previously, each ADC module has multiple trigger sources that can be used to initiate an ADC conversion. For a complete list of trigger sources please reference the ‘ADC Triggering’ section of the TRM.
Point about triggering:
There is fine granularity and coupling for when the ADC conversion can be sampled vs the control loop (especially with an EPWM-trigger + EPWM-actuation scheme), which is convenient for avoiding noise and optimizing response times (phase margin).
Parallel ADCs allow for true simultaneous sampling, which is good for correlated signals (like Voltage + Current for a power supply)
The sampling rate is software configurable, so the ADC sampling can be adjusted on-the-fly to match the input signal
Triggering Examples#
The top example shows channels A1, A3, and A5 being converted with a trigger from EPWM1. After A5 is converted, ADCINT1 is generated.
The bottom example shows channels A2, A4, and A6 being converted initially by a software trigger. Then, after A6 is converted, ADCINT2 is generated and also fed back as a trigger to start the process again.
The ADC ping-pong triggering example shows channels B0 through B5 being converted, triggered initially by software. After channel B2 is converted, ADCINT1 is generated, which also triggers channel B3. After channel B5 is converted, ADCINT2 is generated and is also fed back to start the process again from the beginning. Additionally, ADCINT1 and ADCINT2 are being used to manage the ping-pong interrupts for the interrupt service routines.
ADC Conversion Priority#
When multiple triggers are received at the same time, the ADC conversion priority determines the order in which they are converted.
Three different priority modes are supported. Lets take a look at each:
Round Robin Priority (default)#
No SOC has an inherent higher priority than another
Priority depends on the round robin pointer which operates in a circular buffer
High Priority#
High priority SOC will interrupt the round robin wheel after current conversion completes and insert itself as the next conversion
One or more than one SOC can be assigned as ‘high priority’
High priority mode is assigned first to the lower number start-of-conversion and then in increasing numerical order.
If two high priority start-of-conversion triggers occur at the same time, the lower number will take precedence.
After its conversion completes, the round robin wheel will continue where it was interrupted
Round Robin Burst Mode#
Allows a single trigger to convert one or more SOCs in the round robin wheel
Uses BURSTTRIG instead of TRIGSEL for all round robin SOCs (not high priority) to select the burst size and trigger source
In the ADC Conversion Priority Functional Diagram, the Start-of-Conversion Priority Control Register contains two bit fields. The Start-of-Conversion Priority bit fields determine the cutoff point between high priority and round robin mode, whereas the Round-Robin Pointer bit fields contains the last converted round robin start-of-conversion which determines the order of conversions.
The Round-Robin Burst mode utilizes an ADC Burst Control Register to enable the burst mode, determine the burst size, and select the burst trigger source.
Post Processing Block#
To further enhance the capabilities of the ADC, each ADC module incorporates post processing blocks (PPBs), and each PPB can be linked to any of the ADC result registers (ADCRESULTx). The PPBs can be used for offset correction, calculating an error from a set-point, detecting a limit and zero-crossing, and capturing a trigger-to-sample delay.
1.Offset Correction
Simultaneously remove an offset associated with an ADCIN channel possibly caused by external sensors and signal sources (zero-overhead; saving cycles)
2.Error from Set-point Calculation
Subtract out a reference value which can be used to automatically calculate an error from a set-point or expected value (reduces the sample to output latency and software overhead)
3.Limit and Zero-Crossing Detection
Automatically perform a check against a high/low limit or zero- crossing and can generate a trip to the ePWM and/or an interrupt (decreases the sample to ePWM latency and reduces software overhead; trip the ePWM based on an out of range ADC conversion without CPU intervention) which is useful for safety cautious applications.
4.Trigger-to-Sample Delay Capture
Capable of recording the delay between when the SOC is triggered and when it begins to be sampled (allows software techniques to reduce the delay error)
5.Post Processing Block Interrupt Event
Each ADC module contains Post Processing Blocks
Each Post Processing Block can be associated with any of the 16 ADCRESULTx registers
ADC Clocking Flow#
In order to configure the clock for the ADC module, first the SYSCLK needs to be
generated. This clock is the CPU frequency and is configured through the
SysCtl_setClock() function. This function lets you choose the input clock
source and configure the PLL settings. Once the SYSCLK is setup, the clock to
each ADC module used must be enabled using the SysCtl_enablePeripheral()
function. Upon enabling the clock, a prescalar value can be selected
through the ADC_setPrescaler() function that will scale down the SYSCLK
frequency to go to the ADC core. Make sure to check the datasheet for the MAX
ADC frequency, this is lower than SYSCLK.
Example of configuring the clock settings for a device
Note:
The values in this example may not apply to all devices but the flow will be the same.
ADC Timing#
Below is an example of how to calculate the maximum sampling rate. For this
example, SYSCLK is 100MHz (10ns period) and ADCCLK is 50MHz (20ns period)
Sample + Hold (sampling window) time: 8 * 10 ns = 80 ns
Conversion time: 21 * 10 ns = 210 ns
Sampling Rate: 80 ns + 210 ns = 290 ns ->3.45 MSPS (Mega samples per second)
ADC Conversion Result Registers#
The ADC conversion results are stored within the ADCRESULTx register. The
ADC_readResult() function can be utilized to read the result given an ADC
module and SOC number.
Selectable internal reference of 2.5 V or 3.3 V (Not available on multi-core devices)
Ratiometric external reference set by VREFHI/VREFLO
Note:
The table above is based on internal reference of 3.3 V; for external reference VREFHI is VDDA maximum, however VREFHI is typically selected as 2.5 V or 3.0 V
ADC Calibration and Reference#
Built-In Calibration#
TI reserved OTP contains device specific calibration data for the ADC, internal oscillators and buffered DAC
The Boot ROM contains a Device_cal() routine that copies the calibration data to their respective registers
Device_cal() must be run to meet the specifications in the datasheet
The Bootloader automatically calls Device_cal() such that no action is normally required by the user
If the Bootloader is bypassed (e.g. during development) Device_cal () should be called by the application:
The Device_cal() function is called by the SysCtl_deviceCal() function
within the sysctl.h file which is called by the Device_init() function. The
Device_init() function is found within device.c. This is what C2000Ware
examples utilize to initialize the device.
Manual ADC Calibration#
If the offset and gain errors in the datasheet are unacceptable for your application, or you want to also compensate for board level errors (e.g. sensor or amplifier offset), you can manually calibrate
Offset error (12-bit mode)
Compensated in analog with the ADCOFFTRIM register
No reduction in full-scale range
Configure input to VREFLO, set ADCOFFTRIM to maximum offset error, and take a reading
Re-adjust ADCOFFTRIM to make result zero
Gain error
Compensated in software
Some loss in full-scale range
Requires use of a second ADC input pin and an upper-range reference voltage on that pin
Analog Subsystem External Reference#
Setting up an External Reference
For an example of how to setup an external reference refer to the ‘Designing an External Reference Circuit’ section within the device’s Technical Reference Manual (TRM).
The following image shows an example of the reference generation scheme for the F28004x device:
ADC Type-4#
The figure below shows the simplified diagram of ADC module, which consists of input channel MUX, SOC arbitration, SOC block, REPEAT block, Post-Processing Block (PBB), ADC core, and reference voltage generator.
The ADC Type-4 module contains two repeat blocks, in which the trigger can be selected from any of the regular triggers. Once selected, the repeater can pass a modified version of the input trigger to its output based on the other configurations in the block. From the SOC perspective, the repeater trigger functions the same as any other trigger. REPEAT block is illustrated below.
The possible trigger modifications are discussed below
Over-sampling#
The initial trigger is passed through to the module output. As soon as all SOCs configured to receive the trigger are no longer pending (the last sample is in-progress) the trigger is issued again. This process repeats until a fixed and preselected number of trigger pulses have been issued (NSEL + 1 pulses). This allows the application to easily perform multiple back-to-back samples from a single trigger pulse. When used in conjunction with the aggregation options in the PPB this allows oversampling, averaging, or peak detection.
The figure below shows an example of an over-sampled ADC triggering scheme. (TRIGGER = ePWM SOCA, NSEL = 3, PHASE = 0, MODE = Over-sampling, SPREAD = 0)
Under-sampling#
The initial trigger is passed through to the module output. Subsequent triggers are blocked until a fixed and preselected number of trigger pulses have been received by the repeat module (NSEL + 1 total triggers). The result is only 1-in-N trigger pulses passing to the output. This allows the application to scale down the trigger frequency for one or more SOCs. This is useful for charge-sharing input drivers which have increased error based on how frequently the channel is sampled.
The figure below shows an example of an under-sampled ADC triggering scheme. (TRIGGER = ePWM PRD, NSEL = 7, PHASE = 0, MODE = Under-sampling, SPREAD = (don’t care))
Phase delay#
The initial trigger is delayed by a specified number of SYSCLK cycles. This can be combined with either over-sampled or under-sampled triggers. This allows the application to tie the trigger starting point to an event (e.g. CMPAU) in the ePWM without the trigger occurring exactly at the event time. This is useful, for example, if the event causes a pin state change and the application wants to sample a little later after noise from the pin edge has settled. Without the phase delay, an additional compare would be needed.
The figure below shows an example of an ADC trigger with phase delay. (TRIGGER = ePWM SOCA, NSEL= 0, PHASE = 100, MODE = (either), SPREAD = (don’t care))
Re-trigger spread#
If additional time between samples is desired, the SPREAD can be set to a number of SYSCLK cycles equal to the desired time between samples.
The figure below shows an example of an ADC trigger using sample spread. (TRIGGER = ePWM SOCA, NSEL = 3, MODE = Over-sampling, PHASE = 0, SPREAD = 500)
Safety Checker#
In ADC module, to facilitate automatic HW safety checking of redundant ADC results, the safety checker subsystem snoops on the various ADC results from multiple ADC modules, compares the results, and then checks if the results are in range. In case the aggregate result is out of range then a HW trip via the X-BAR and/or an ISR can be triggered. At a high level, the ADC safety checker consists of a series of checker tiles that share a common ADC results bus. As the ADCs produce results, the results are placed on the checker bus so that each checker tile can capture its associated results. Once a checker tile captures both configured ADC results, the absolute value of the difference between the results is taken and it is compared to a pre-set tolerance. If the difference is out of tolerance, an event is generated for the X-BAR or an interrupt can be generated.
Below is an image of the ADC Safety Checker Tile Diagram
MUX Connections#
In order to control an external mux, four channel selection pins are assigned to handle more channel connected via digital output pins. This allows the customer the flexibility to increase the ADC channel count in each SOC via an external mux with minimal SW overhead. The channel selection pins are made available by mapping them to GPIO mux positions just like any other peripheral.
On the ADC Type-4 module, oversampling is enabled by adding additional HW to the post-processing block (PPB). This hardware supports accumulation for averaging and also min/max of a sequence of samples for peak detection and outlier removal.
ADC Type-5 & Type-6#
Note
Not all C2000 devices have a Type-5 or Type-6 ADC. Refer to the Peripheral Reference Guide for a list of supported modules and module types on your device.
Type-5 Key Features#
ADC-Sample & Hold (S/H) Capacitor Reset
PPB Result Delta Calculation
Type-6 Key Features#
High-speed sampling - see device data sheet
ADC-Sample & Hold (S/H) Capacitor Reset
Additional PWM triggers: SOCC and SOCD
Sample & Hold (S/H) Capacitor Reset#
The signal conditioning circuits for the feedback signals should be carefully designed and evaluated to ensure that adequate settling is achieved in the time allocated for the ADC’s sample-and-hold (S+H). In cases where adequate settling is not achieved in the hardware design of the signal conditioning circuits, memory cross-talk issues can arise in the system. Indeed, in systems where the ADC is scanning through multiple multiplexed inputs to be sampled (a common use case in real-time control applications), the ADC result error will show up as memory cross-talk. Memory crosstalk is the tendency of the ADC conversion to be pulled towards the value of the previous conversion due to inadequate sample and hold time.
The ADC Type-5/Type-6 sample capacitor reset feature helps mitigate memory crosstalk. When the sample capacitor reset is enabled, after every conversion, the sampling capacitor voltage is reset to the VREFLO voltage. While this is achievable on other devices, current methods require extra sampling (VREFLO) in between samples, strategic ADC sampling strategies, or driving circuit enhancements for good settling performance. Also, this new feature takes only 1 ADCCLK cycle while other devices would require a full sample and conversion (about 20 ADCCLK Cycles) to reset the capacitor.
Post-Processing Block (PPB) Result Delta Calculation (Type-5 only)#
The ADC Type-5 post-processing block has the capability to calculate the delta from the previous conversion sample. When enabled, register contains the difference between the current conversion result and the previous conversion. This delta is computed on the actual conversion result, not the result of a prior delta calculation. Obtaining the result delta can help provide insight into certain signal characteristics in your system. For example, a high delta might tell us that there is something wrong with the signal conditioning.
SOCC & SOCD triggers (Type-6 only)#
The PWM has four different available SOC events (SOCA, SOCB, SOCC, and SOCD - connected to CMPA, CMPB, CMPC and CMPD respectively) that can be used to trigger SOCs on the Type-6 ADC module. This increases flexibility in the timing of when conversions on the Type-6 ADC can take place while allowing of these events to be sycnhronized to the same PWM time-base counter signal.
Resources#
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