PRCM

Instance: PRCM
Component: PRCM
Base address: 0x40082000


Power, Reset and Clock Management

TOP:PRCM Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

INFRCLKDIVR

RW

32

0x0000 0000

0x0000 0000

0x4008 2000

INFRCLKDIVS

RW

32

0x0000 0000

0x0000 0004

0x4008 2004

INFRCLKDIVDS

RW

32

0x0000 0000

0x0000 0008

0x4008 2008

VDCTL

RW

32

0x0000 0000

0x0000 000C

0x4008 200C

CLKLOADCTL

RW

32

0x0000 0002

0x0000 0028

0x4008 2028

RFCCLKG

RW

32

0x0000 0001

0x0000 002C

0x4008 202C

VIMSCLKG

RW

32

0x0000 0003

0x0000 0030

0x4008 2030

SECDMACLKGR

RW

32

0x0000 0000

0x0000 003C

0x4008 203C

SECDMACLKGS

RW

32

0x0000 0000

0x0000 0040

0x4008 2040

SECDMACLKGDS

RW

32

0x0000 0000

0x0000 0044

0x4008 2044

GPIOCLKGR

RW

32

0x0000 0000

0x0000 0048

0x4008 2048

GPIOCLKGS

RW

32

0x0000 0000

0x0000 004C

0x4008 204C

GPIOCLKGDS

RW

32

0x0000 0000

0x0000 0050

0x4008 2050

GPTCLKGR

RW

32

0x0000 0000

0x0000 0054

0x4008 2054

GPTCLKGS

RW

32

0x0000 0000

0x0000 0058

0x4008 2058

GPTCLKGDS

RW

32

0x0000 0000

0x0000 005C

0x4008 205C

I2CCLKGR

RW

32

0x0000 0000

0x0000 0060

0x4008 2060

I2CCLKGS

RW

32

0x0000 0000

0x0000 0064

0x4008 2064

I2CCLKGDS

RW

32

0x0000 0000

0x0000 0068

0x4008 2068

UARTCLKGR

RW

32

0x0000 0000

0x0000 006C

0x4008 206C

UARTCLKGS

RW

32

0x0000 0000

0x0000 0070

0x4008 2070

UARTCLKGDS

RW

32

0x0000 0000

0x0000 0074

0x4008 2074

SSICLKGR

RW

32

0x0000 0000

0x0000 0078

0x4008 2078

SSICLKGS

RW

32

0x0000 0000

0x0000 007C

0x4008 207C

SSICLKGDS

RW

32

0x0000 0000

0x0000 0080

0x4008 2080

I2SCLKGR

RW

32

0x0000 0000

0x0000 0084

0x4008 2084

I2SCLKGS

RW

32

0x0000 0000

0x0000 0088

0x4008 2088

I2SCLKGDS

RW

32

0x0000 0000

0x0000 008C

0x4008 208C

SYSBUSCLKDIV

RW

32

0x0000 0000

0x0000 00B4

0x4008 20B4

CPUCLKDIV

RW

32

0x0000 0000

0x0000 00B8

0x4008 20B8

PERBUSCPUCLKDIV

RW

32

0x0000 0000

0x0000 00BC

0x4008 20BC

PERDMACLKDIV

RW

32

0x0000 0000

0x0000 00C4

0x4008 20C4

I2SBCLKSEL

RW

32

0x0000 0000

0x0000 00C8

0x4008 20C8

GPTCLKDIV

RW

32

0x0000 0000

0x0000 00CC

0x4008 20CC

I2SCLKCTL

RW

32

0x0000 0000

0x0000 00D0

0x4008 20D0

I2SMCLKDIV

RW

32

0x0000 0000

0x0000 00D4

0x4008 20D4

I2SBCLKDIV

RW

32

0x0000 0000

0x0000 00D8

0x4008 20D8

I2SWCLKDIV

RW

32

0x0000 0000

0x0000 00DC

0x4008 20DC

RESETSECDMA

RW

32

0x0000 0000

0x0000 00F0

0x4008 20F0

RESETGPIO

RW

32

0x0000 0000

0x0000 00F4

0x4008 20F4

RESETGPT

RW

32

0x0000 0000

0x0000 00F8

0x4008 20F8

RESETI2C

RW

32

0x0000 0000

0x0000 00FC

0x4008 20FC

RESETUART

RW

32

0x0000 0000

0x0000 0100

0x4008 2100

RESETSSI

RW

32

0x0000 0000

0x0000 0104

0x4008 2104

RESETI2S

RW

32

0x0000 0000

0x0000 0108

0x4008 2108

PDCTL0

RW

32

0x0000 0000

0x0000 012C

0x4008 212C

PDCTL0RFC

RW

32

0x0000 0000

0x0000 0130

0x4008 2130

PDCTL0SERIAL

RW

32

0x0000 0000

0x0000 0134

0x4008 2134

PDCTL0PERIPH

RW

32

0x0000 0000

0x0000 0138

0x4008 2138

PDSTAT0

RO

32

0x0000 0000

0x0000 0140

0x4008 2140

PDSTAT0RFC

RO

32

0x0000 0000

0x0000 0144

0x4008 2144

PDSTAT0SERIAL

RO

32

0x0000 0000

0x0000 0148

0x4008 2148

PDSTAT0PERIPH

RO

32

0x0000 0000

0x0000 014C

0x4008 214C

PDCTL1

RW

32

0x0000 000A

0x0000 017C

0x4008 217C

PDCTL1CPU

RW

32

0x0000 0001

0x0000 0184

0x4008 2184

PDCTL1RFC

RW

32

0x0000 0000

0x0000 0188

0x4008 2188

PDCTL1VIMS

RW

32

0x0000 0001

0x0000 018C

0x4008 218C

PDSTAT1

RO

32

0x0000 001A

0x0000 0194

0x4008 2194

PDSTAT1BUS

RO

32

0x0000 0001

0x0000 0198

0x4008 2198

PDSTAT1RFC

RO

32

0x0000 0000

0x0000 019C

0x4008 219C

PDSTAT1CPU

RO

32

0x0000 0001

0x0000 01A0

0x4008 21A0

PDSTAT1VIMS

RO

32

0x0000 0001

0x0000 01A4

0x4008 21A4

RFCBITS

RW

32

0x0000 0000

0x0000 01CC

0x4008 21CC

RFCMODESEL

RW

32

0x0000 0000

0x0000 01D0

0x4008 21D0

RFCMODEHWOPT

RO

32

0x0000 0000

0x0000 01D4

0x4008 21D4

PWRPROFSTAT

RW

32

0x0000 0001

0x0000 01E0

0x4008 21E0

MCUSRAMCFG

RW

32

0x0000 0020

0x0000 021C

0x4008 221C

RAMRETEN

RW

32

0x0000 000B

0x0000 0224

0x4008 2224

OSCIMSC

RW

32

0x0000 0036

0x0000 0290

0x4008 2290

OSCRIS

RO

32

0x0000 0000

0x0000 0294

0x4008 2294

OSCICR

WO

32

0x0000 0000

0x0000 0298

0x4008 2298

TOP:PRCM Register Descriptions

TOP:PRCM:INFRCLKDIVR

Address Offset 0x0000 0000
Physical Address 0x4008 2000 Instance 0x4008 2000
Description Infrastructure Clock Division Factor For Run Mode
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 RATIO Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode. Division ratio affects both infrastructure clock and perbusull clock.
Value ENUM Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV8 Divide by 8
0x3 DIV32 Divide by 32
RW 0b00

TOP:PRCM:INFRCLKDIVS

Address Offset 0x0000 0004
Physical Address 0x4008 2004 Instance 0x4008 2004
Description Infrastructure Clock Division Factor For Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 RATIO Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode. Division ratio affects both infrastructure clock and perbusull clock.
Value ENUM Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV8 Divide by 8
0x3 DIV32 Divide by 32
RW 0b00

TOP:PRCM:INFRCLKDIVDS

Address Offset 0x0000 0008
Physical Address 0x4008 2008 Instance 0x4008 2008
Description Infrastructure Clock Division Factor For DeepSleep Mode
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 RATIO Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode. Division ratio affects both infrastructure clock and perbusull clock.
Value ENUM Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV8 Divide by 8
0x3 DIV32 Divide by 32
RW 0b00

TOP:PRCM:VDCTL

Address Offset 0x0000 000C
Physical Address 0x4008 200C Instance 0x4008 200C
Description MCU Voltage Domain Control
Type RW
Bits Field Name Description Type Reset
31:1 SPARE1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 ULDO Request PMCTL to switch to uLDO.

0: No request
1: Assert request when possible

The bit will have no effect before the following requirements are met:
1. PDCTL1.CPU_ON = 0
2. PDCTL1.VIMS_MODE = x0
3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD)
4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD)
5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD)
6. RFC do no request access to BUS
7. System CPU in deepsleep		 RW 0

TOP:PRCM:CLKLOADCTL

Address Offset 0x0000 0028
Physical Address 0x4008 2028 Instance 0x4008 2028
Description Load PRCM Settings To CLKCTRL Power Domain
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 LOAD_DONE Status of LOAD.
Will be cleared to 0 when any of the registers requiring a LOAD is written to, and be set to 1 when a LOAD is done.
Note that writing no change to a register will result in the LOAD_DONE being cleared.

0 : One or more registers have been write accessed after last LOAD
1 : No registers are write accessed after last LOAD		 RO 1
0 LOAD
0: No action
1: Load settings to CLKCTRL. Bit is HW cleared.

Multiple changes to settings may be done before LOAD is written once so all changes takes place at the same time. LOAD can also be done after single setting updates.

Registers that needs to be followed by LOAD before settings being applied are:
- SYSBUSCLKDIV
- CPUCLKDIV
- PERBUSCPUCLKDIV
- PERDMACLKDIV
- PERBUSCPUCLKG
- RFCCLKG
- VIMSCLKG
- SECDMACLKGR
- SECDMACLKGS
- SECDMACLKGDS
- GPIOCLKGR
- GPIOCLKGS
- GPIOCLKGDS
- GPTCLKGR
- GPTCLKGS
- GPTCLKGDS
- GPTCLKDIV
- I2CCLKGR
- I2CCLKGS
- I2CCLKGDS
- SSICLKGR
- SSICLKGS
- SSICLKGDS
- UARTCLKGR
- UARTCLKGS
- UARTCLKGDS
- I2SCLKGR
- I2SCLKGS
- I2SCLKGDS
- I2SBCLKSEL
- I2SCLKCTL
- I2SMCLKDIV
- I2SBCLKDIV
- I2SWCLKDIV		 WO 0

TOP:PRCM:RFCCLKG

Address Offset 0x0000 002C
Physical Address 0x4008 202C Instance 0x4008 202C
Description RFC Clock Gate
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 CLK_EN
0: Disable Clock
1: Enable clock if RFC power domain is on

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 1

TOP:PRCM:VIMSCLKG

Address Offset 0x0000 0030
Physical Address 0x4008 2030 Instance 0x4008 2030
Description VIMS Clock Gate
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 CLK_EN 00: Disable clock
01: Disable clock when SYSBUS clock is disabled
11: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0b11

TOP:PRCM:SECDMACLKGR

Address Offset 0x0000 003C
Physical Address 0x4008 203C Instance 0x4008 203C
Description SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes
Type RW
Bits Field Name Description Type Reset
31:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
24 DMA_AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN when enabled.

SYSBUS clock will always run when enabled

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
23:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
19 PKA_ZERIOZE_RESET_N Zeroization logic hardware reset.

0: pka_zeroize logic inactive.
1: pka_zeroize of memory is enabled.

This register must remain active until the memory are completely zeroized which requires 256 periods on systembus clock.		 RW 0
18 PKA_AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN when enabled.

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
17 TRNG_AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN when enabled.

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
16 CRYPTO_AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and SECDMACLKGDS.CRYPTO_CLK_EN when enabled.

SYSBUS clock will always run when enabled

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
15:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
8 DMA_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by DMA_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2 PKA_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by PKA_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
1 TRNG_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by TRNG_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
0 CRYPTO_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by CRYPTO_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:SECDMACLKGS

Address Offset 0x0000 0040
Physical Address 0x4008 2040 Instance 0x4008 2040
Description SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 DMA_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2 PKA_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
1 TRNG_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
0 CRYPTO_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:SECDMACLKGDS

Address Offset 0x0000 0044
Physical Address 0x4008 2044 Instance 0x4008 2044
Description SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 DMA_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2 PKA_CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
1 TRNG_CLK_EN
0: Disable clock
1: Enable clock

SYSBUS clock will always run when enabled

Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
0 CRYPTO_CLK_EN
0: Disable clock
1: Enable clock

SYSBUS clock will always run when enabled

Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:GPIOCLKGR

Address Offset 0x0000 0048
Physical Address 0x4008 2048 Instance 0x4008 2048
Description GPIO Clock Gate For Run And All Modes
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled.

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
7:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:GPIOCLKGS

Address Offset 0x0000 004C
Physical Address 0x4008 204C Instance 0x4008 204C
Description GPIO Clock Gate For Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by GPIOCLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:GPIOCLKGDS

Address Offset 0x0000 0050
Physical Address 0x4008 2050 Instance 0x4008 2050
Description GPIO Clock Gate For Deep Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by GPIOCLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:GPTCLKGR

Address Offset 0x0000 0054
Physical Address 0x4008 2054 Instance 0x4008 2054
Description GPT Clock Gate For Run And All Modes
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:8 AM_CLK_EN Each bit below has the following meaning:

0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled.

ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 AM_GPT0 Enable clock for GPT0 in all modes
0x2 AM_GPT1 Enable clock for GPT1 in all modes
0x4 AM_GPT2 Enable clock for GPT2 in all modes
0x8 AM_GPT3 Enable clock for GPT3 in all modes
RW 0x0
7:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
3:0 CLK_EN Each bit below has the following meaning:

0: Disable clock
1: Enable clock

Can be forced on by AM_CLK_EN

ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 GPT0 Enable clock for GPT0
0x2 GPT1 Enable clock for GPT1
0x4 GPT2 Enable clock for GPT2
0x8 GPT3 Enable clock for GPT3
RW 0x0

TOP:PRCM:GPTCLKGS

Address Offset 0x0000 0058
Physical Address 0x4008 2058 Instance 0x4008 2058
Description GPT Clock Gate For Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 CLK_EN Each bit below has the following meaning:

0: Disable clock
1: Enable clock

Can be forced on by GPTCLKGR.AM_CLK_EN

ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 GPT0 Enable clock for GPT0
0x2 GPT1 Enable clock for GPT1
0x4 GPT2 Enable clock for GPT2
0x8 GPT3 Enable clock for GPT3
RW 0x0

TOP:PRCM:GPTCLKGDS

Address Offset 0x0000 005C
Physical Address 0x4008 205C Instance 0x4008 205C
Description GPT Clock Gate For Deep Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 CLK_EN Each bit below has the following meaning:

0: Disable clock
1: Enable clock

Can be forced on by GPTCLKGR.AM_CLK_EN

ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 GPT0 Enable clock for GPT0
0x2 GPT1 Enable clock for GPT1
0x4 GPT2 Enable clock for GPT2
0x8 GPT3 Enable clock for GPT3
RW 0x0

TOP:PRCM:I2CCLKGR

Address Offset 0x0000 0060
Physical Address 0x4008 2060 Instance 0x4008 2060
Description I2C Clock Gate For Run And All Modes
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled.

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
7:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:I2CCLKGS

Address Offset 0x0000 0064
Physical Address 0x4008 2064 Instance 0x4008 2064
Description I2C Clock Gate For Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:1 SPARE1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by I2CCLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:I2CCLKGDS

Address Offset 0x0000 0068
Physical Address 0x4008 2068 Instance 0x4008 2068
Description I2C Clock Gate For Deep Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:1 SPARE1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by I2CCLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:UARTCLKGR

Address Offset 0x0000 006C
Physical Address 0x4008 206C Instance 0x4008 206C
Description UART Clock Gate For Run And All Modes
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:8 AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled.

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 AM_UART0 Enable clock for UART0
0x2 AM_UART1 Enable clock for UART1
RW 0b00
7:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
1:0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 UART0 Enable clock for UART0
0x2 UART1 Enable clock for UART1
RW 0b00

TOP:PRCM:UARTCLKGS

Address Offset 0x0000 0070
Physical Address 0x4008 2070 Instance 0x4008 2070
Description UART Clock Gate For Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by UARTCLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 AM_UART0 Enable clock for UART0
0x2 AM_UART1 Enable clock for UART1
RW 0b00

TOP:PRCM:UARTCLKGDS

Address Offset 0x0000 0074
Physical Address 0x4008 2074 Instance 0x4008 2074
Description UART Clock Gate For Deep Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by UARTCLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 AM_UART0 Enable clock for UART0
0x2 AM_UART1 Enable clock for UART1
RW 0b00

TOP:PRCM:SSICLKGR

Address Offset 0x0000 0078
Physical Address 0x4008 2078 Instance 0x4008 2078
Description SSI Clock Gate For Run And All Modes
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:8 AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled.

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 SSI0 Enable clock for SSI0
0x2 SSI1 Enable clock for SSI1
RW 0b00
7:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
1:0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 SSI0 Enable clock for SSI0
0x2 SSI1 Enable clock for SSI1
RW 0b00

TOP:PRCM:SSICLKGS

Address Offset 0x0000 007C
Physical Address 0x4008 207C Instance 0x4008 207C
Description SSI Clock Gate For Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by SSICLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 SSI0 Enable clock for SSI0
0x2 SSI1 Enable clock for SSI1
RW 0b00

TOP:PRCM:SSICLKGDS

Address Offset 0x0000 0080
Physical Address 0x4008 2080 Instance 0x4008 2080
Description SSI Clock Gate For Deep Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by SSICLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Value ENUM Name Description
0x1 SSI0 Enable clock for SSI0
0x2 SSI1 Enable clock for SSI1
RW 0b00

TOP:PRCM:I2SCLKGR

Address Offset 0x0000 0084
Physical Address 0x4008 2084 Instance 0x4008 2084
Description I2S Clock Gate For Run And All Modes
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 AM_CLK_EN
0: No force
1: Force clock on for all modes (Run, Sleep and Deep Sleep)

Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled.
SYSBUS clock will always run when enabled

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
7:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:I2SCLKGS

Address Offset 0x0000 0088
Physical Address 0x4008 2088 Instance 0x4008 2088
Description I2S Clock Gate For Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

Can be forced on by I2SCLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:I2SCLKGDS

Address Offset 0x0000 008C
Physical Address 0x4008 208C Instance 0x4008 208C
Description I2S Clock Gate For Deep Sleep Mode
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 CLK_EN
0: Disable clock
1: Enable clock

SYSBUS clock will always run when enabled

Can be forced on by I2SCLKGR.AM_CLK_EN

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:SYSBUSCLKDIV

Address Offset 0x0000 00B4
Physical Address 0x4008 20B4 Instance 0x4008 20B4
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 RATIO Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 DIV1 Internal. Only to be used through TI provided API.
0x1 DIV2 Internal. Only to be used through TI provided API.
RW 0b000

TOP:PRCM:CPUCLKDIV

Address Offset 0x0000 00B8
Physical Address 0x4008 20B8 Instance 0x4008 20B8
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Internal. Only to be used through TI provided API. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 RATIO Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 DIV1 Internal. Only to be used through TI provided API.
0x1 DIV2 Internal. Only to be used through TI provided API.
RW 0

TOP:PRCM:PERBUSCPUCLKDIV

Address Offset 0x0000 00BC
Physical Address 0x4008 20BC Instance 0x4008 20BC
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Internal. Only to be used through TI provided API. RO 0x000 0000
3:0 RATIO Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 DIV1 Internal. Only to be used through TI provided API.
0x1 DIV2 Internal. Only to be used through TI provided API.
0x2 DIV4 Internal. Only to be used through TI provided API.
0x3 DIV8 Internal. Only to be used through TI provided API.
0x4 DIV16 Internal. Only to be used through TI provided API.
0x5 DIV32 Internal. Only to be used through TI provided API.
0x6 DIV64 Internal. Only to be used through TI provided API.
0x7 DIV128 Internal. Only to be used through TI provided API.
0x8 DIV256 Internal. Only to be used through TI provided API.
RW 0x0

TOP:PRCM:PERDMACLKDIV

Address Offset 0x0000 00C4
Physical Address 0x4008 20C4 Instance 0x4008 20C4
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Internal. Only to be used through TI provided API. RO 0x000 0000
3:0 RATIO Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 DIV1 Internal. Only to be used through TI provided API.
0x1 DIV2 Internal. Only to be used through TI provided API.
0x2 DIV4 Internal. Only to be used through TI provided API.
0x3 DIV8 Internal. Only to be used through TI provided API.
0x4 DIV16 Internal. Only to be used through TI provided API.
0x5 DIV32 Internal. Only to be used through TI provided API.
0x6 DIV64 Internal. Only to be used through TI provided API.
0x7 DIV128 Internal. Only to be used through TI provided API.
0x8 DIV256 Internal. Only to be used through TI provided API.
RW 0x0

TOP:PRCM:I2SBCLKSEL

Address Offset 0x0000 00C8
Physical Address 0x4008 20C8 Instance 0x4008 20C8
Description I2S Clock Control
Type RW
Bits Field Name Description Type Reset
31:1 SPARE1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 SRC BCLK source selector

0: Use external BCLK
1: Use internally generated clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:GPTCLKDIV

Address Offset 0x0000 00CC
Physical Address 0x4008 20CC Instance 0x4008 20CC
Description GPT Scalar
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 RATIO Scalar used for GPTs. The division rate will be constant and ungated for Run / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD needs to be written Other values are not supported.
Value ENUM Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV32 Divide by 32
0x6 DIV64 Divide by 64
0x7 DIV128 Divide by 128
0x8 DIV256 Divide by 256
RW 0x0

TOP:PRCM:I2SCLKCTL

Address Offset 0x0000 00D0
Physical Address 0x4008 20D0 Instance 0x4008 20D0
Description I2S Clock Control
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3 SMPL_ON_POSEDGE On the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK.

0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge.
1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge.

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0
2:1 WCLK_PHASE Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV).

0: Single phase
1: Dual phase
2: User Defined
3: Reserved/Undefined

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0b00
0 EN
0: MCLK, BCLK and WCLK will be static low
1: Enables the generation of MCLK, BCLK and WCLK

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0

TOP:PRCM:I2SMCLKDIV

Address Offset 0x0000 00D4
Physical Address 0x4008 20D4 Instance 0x4008 20D4
Description MCLK Division Ratio
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 MDIV An unsigned factor of the division ratio used to generate MCLK [2-1024]:

MCLK = MCUCLK/MDIV[Hz]
MCUCLK is 48MHz.

A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase.

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0b00 0000 0000

TOP:PRCM:I2SBCLKDIV

Address Offset 0x0000 00D8
Physical Address 0x4008 20D8 Instance 0x4008 20D8
Description BCLK Division Ratio
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BDIV An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]:

BCLK = MCUCLK/BDIV[Hz]
MCUCLK is 48MHz.

A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase.
If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase.

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0b00 0000 0000

TOP:PRCM:I2SWCLKDIV

Address Offset 0x0000 00DC
Physical Address 0x4008 20DC Instance 0x4008 20DC
Description WCLK Division Ratio
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 WDIV If I2SCLKCTL.WCLK_PHASE = 0, Single phase.
WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods.

WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]
MCUCLK is 48MHz.

If I2SCLKCTL.WCLK_PHASE = 1, Dual phase.
Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods.

WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz]

If I2SCLKCTL.WCLK_PHASE = 2, User defined.
WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] (unsigned, [1-255]) BCLK periods.

WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]

For changes to take effect, CLKLOADCTL.LOAD needs to be written		 RW 0x0000

TOP:PRCM:RESETSECDMA

Address Offset 0x0000 00F0
Physical Address 0x4008 20F0 Instance 0x4008 20F0
Description RESET For SEC (PKA And TRNG And CRYPTO) And UDMA
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 DMA Write 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2 PKA Write 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0
1 TRNG Write 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0
0 CRYPTO Write 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0

TOP:PRCM:RESETGPIO

Address Offset 0x0000 00F4
Physical Address 0x4008 20F4 Instance 0x4008 20F4
Description RESET For GPIO IPs
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 GPIO
0: No action
1: Reset GPIO. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0

TOP:PRCM:RESETGPT

Address Offset 0x0000 00F8
Physical Address 0x4008 20F8 Instance 0x4008 20F8
Description RESET For GPT Ips
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 GPT
0: No action
1: Reset all GPTs. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0

TOP:PRCM:RESETI2C

Address Offset 0x0000 00FC
Physical Address 0x4008 20FC Instance 0x4008 20FC
Description RESET For I2C IPs
Type RW
Bits Field Name Description Type Reset
31:1 SPARE1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 I2C
0: No action
1: Reset I2C. HW cleared.

Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0

TOP:PRCM:RESETUART

Address Offset 0x0000 0100
Physical Address 0x4008 2100 Instance 0x4008 2100
Description RESET For UART IPs
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 UART1
0: No action
1: Reset UART1. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0
0 UART0
0: No action
1: Reset UART0. HW cleared.

Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0

TOP:PRCM:RESETSSI

Address Offset 0x0000 0104
Physical Address 0x4008 2104 Instance 0x4008 2104
Description RESET For SSI IPs
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 SSI SSI 0:

0: No action
1: Reset SSI. HW cleared.

Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

SSI 1:

0: No action
1: Reset SSI. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0b00

TOP:PRCM:RESETI2S

Address Offset 0x0000 0108
Physical Address 0x4008 2108 Instance 0x4008 2108
Description RESET For I2S IP
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 I2S
0: No action
1: Reset module. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.		 WO 0

TOP:PRCM:PDCTL0

Address Offset 0x0000 012C
Physical Address 0x4008 212C Instance 0x4008 212C
Description Power Domain Control
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 PERIPH_ON PERIPH Power domain.

0: PERIPH power domain is powered down
1: PERIPH power domain is powered up		 RW 0
1 SERIAL_ON SERIAL Power domain.

0: SERIAL power domain is powered down
1: SERIAL power domain is powered up		 RW 0
0 RFC_ON
0: RFC power domain powered off if also PDCTL1.RFC_ON = 0
1: RFC power domain powered on		 RW 0

TOP:PRCM:PDCTL0RFC

Address Offset 0x0000 0130
Physical Address 0x4008 2130 Instance 0x4008 2130
Description RFC Power Domain Control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON Alias for PDCTL0.RFC_ON RW 0

TOP:PRCM:PDCTL0SERIAL

Address Offset 0x0000 0134
Physical Address 0x4008 2134 Instance 0x4008 2134
Description SERIAL Power Domain Control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON Alias for PDCTL0.SERIAL_ON RW 0

TOP:PRCM:PDCTL0PERIPH

Address Offset 0x0000 0138
Physical Address 0x4008 2138 Instance 0x4008 2138
Description PERIPH Power Domain Control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON Alias for PDCTL0.PERIPH_ON RW 0

TOP:PRCM:PDSTAT0

Address Offset 0x0000 0140
Physical Address 0x4008 2140 Instance 0x4008 2140
Description Power Domain Status
Type RO
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 PERIPH_ON PERIPH Power domain.

0: Domain may be powered down
1: Domain powered up (guaranteed)		 RO 0
1 SERIAL_ON SERIAL Power domain.

0: Domain may be powered down
1: Domain powered up (guaranteed)		 RO 0
0 RFC_ON RFC Power domain

0: Domain may be powered down
1: Domain powered up (guaranteed)		 RO 0

TOP:PRCM:PDSTAT0RFC

Address Offset 0x0000 0144
Physical Address 0x4008 2144 Instance 0x4008 2144
Description RFC Power Domain Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON Alias for PDSTAT0.RFC_ON RO 0

TOP:PRCM:PDSTAT0SERIAL

Address Offset 0x0000 0148
Physical Address 0x4008 2148 Instance 0x4008 2148
Description SERIAL Power Domain Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON Alias for PDSTAT0.SERIAL_ON RO 0

TOP:PRCM:PDSTAT0PERIPH

Address Offset 0x0000 014C
Physical Address 0x4008 214C Instance 0x4008 214C
Description PERIPH Power Domain Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON Alias for PDSTAT0.PERIPH_ON RO 0

TOP:PRCM:PDCTL1

Address Offset 0x0000 017C
Physical Address 0x4008 217C Instance 0x4008 217C
Description Power Domain Control
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:3 VIMS_MODE
00: VIMS power domain is only powered when CPU power domain is powered.
01: VIMS power domain is powered whenever the BUS power domain is powered.
1X: Block power up of VIMS power domain at next wake up. This mode only has effect when VIMS power domain is not powered. Used for Autonomous RF Core.		 RW 0b01
2 RFC_ON 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power domain powered on Bit shall be used by RFC in autonomous mode but there is no HW restrictions fom system CPU to access the bit. RW 0
1 CPU_ON
0: Causes a power down of the CPU power domain when system CPU indicates it is idle.
1: Initiates power-on of the CPU power domain.

This bit is automatically set by a WIC power-on event.		 RW 1
0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0

TOP:PRCM:PDCTL1CPU

Address Offset 0x0000 0184
Physical Address 0x4008 2184 Instance 0x4008 2184
Description CPU Power Domain Direct Control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON This is an alias for PDCTL1.CPU_ON RW 1

TOP:PRCM:PDCTL1RFC

Address Offset 0x0000 0188
Physical Address 0x4008 2188 Instance 0x4008 2188
Description RFC Power Domain Direct Control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON This is an alias for PDCTL1.RFC_ON RW 0

TOP:PRCM:PDCTL1VIMS

Address Offset 0x0000 018C
Physical Address 0x4008 218C Instance 0x4008 218C
Description VIMS Mode Direct Control
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 MODE This is an alias for PDCTL1.VIMS_MODE RW 0b01

TOP:PRCM:PDSTAT1

Address Offset 0x0000 0194
Physical Address 0x4008 2194 Instance 0x4008 2194
Description Power Manager Status
Type RO
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4 BUS_ON
0: BUS domain not accessible
1: BUS domain is currently accessible		 RO 1
3 VIMS_ON
0: VIMS domain not accessible
1: VIMS domain is currently accessible		 RO 1
2 RFC_ON
0: RFC domain not accessible
1: RFC domain is currently accessible		 RO 0
1 CPU_ON
0: CPU and BUS domain not accessible
1: CPU and BUS domains are both currently accessible		 RO 1
0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0

TOP:PRCM:PDSTAT1BUS

Address Offset 0x0000 0198
Physical Address 0x4008 2198 Instance 0x4008 2198
Description BUS Power Domain Direct Read Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON This is an alias for PDSTAT1.BUS_ON RO 1

TOP:PRCM:PDSTAT1RFC

Address Offset 0x0000 019C
Physical Address 0x4008 219C Instance 0x4008 219C
Description RFC Power Domain Direct Read Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON This is an alias for PDSTAT1.RFC_ON RO 0

TOP:PRCM:PDSTAT1CPU

Address Offset 0x0000 01A0
Physical Address 0x4008 21A0 Instance 0x4008 21A0
Description CPU Power Domain Direct Read Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON This is an alias for PDSTAT1.CPU_ON RO 1

TOP:PRCM:PDSTAT1VIMS

Address Offset 0x0000 01A4
Physical Address 0x4008 21A4 Instance 0x4008 21A4
Description VIMS Mode Direct Read Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ON This is an alias for PDSTAT1.VIMS_ON RO 1

TOP:PRCM:RFCBITS

Address Offset 0x0000 01CC
Physical Address 0x4008 21CC Instance 0x4008 21CC
Description Control To RFC
Type RW
Bits Field Name Description Type Reset
31:0 READ Control bits for RFC. The RF core CPE processor will automatically check this register when it boots, and it can be used to immediately instruct CPE to perform some tasks at its start-up. The supported functionality is ROM-defined and may vary. See the technical reference manual for more details. RW 0x0000 0000

TOP:PRCM:RFCMODESEL

Address Offset 0x0000 01D0
Physical Address 0x4008 21D0 Instance 0x4008 21D0
Description Selected RFC Mode
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 CURR Selects the set of commands that the RFC will accept. Only modes permitted by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for details.
Value ENUM Name Description
0x0 MODE0 Select Mode 0
0x1 MODE1 Select Mode 1
0x2 MODE2 Select Mode 2
0x3 MODE3 Select Mode 3
0x4 MODE4 Select Mode 4
0x5 MODE5 Select Mode 5
0x6 MODE6 Select Mode 6
0x7 MODE7 Select Mode 7
RW 0b000

TOP:PRCM:RFCMODEHWOPT

Address Offset 0x0000 01D4
Physical Address 0x4008 21D4 Instance 0x4008 21D4
Description Allowed RFC Modes
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 AVAIL Permitted RFC modes. More than one mode can be permitted.
Value ENUM Name Description
0x1 MODE0 Mode 0 permitted
0x2 MODE1 Mode 1 permitted
0x4 MODE2 Mode 2 permitted
0x8 MODE3 Mode 3 permitted
0x10 MODE4 Mode 4 permitted
0x20 MODE5 Mode 5 permitted
0x40 MODE6 Mode 6 permitted
0x80 MODE7 Mode 7 permitted
RO 0x00

TOP:PRCM:PWRPROFSTAT

Address Offset 0x0000 01E0
Physical Address 0x4008 21E0 Instance 0x4008 21E0
Description Power Profiler Register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VALUE SW can use these bits to timestamp the application. These bits are also available through the testtap and can thus be used by the emulator to profile in real time. RW 0x01

TOP:PRCM:MCUSRAMCFG

Address Offset 0x0000 021C
Physical Address 0x4008 221C Instance 0x4008 221C
Description MCU SRAM configuration
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 BM_OFF Burst Mode disable

0: Burst Mode enabled.
1: Burst Mode off.		 RW 1
4 PAGE Page Mode select

0: Page Mode disabled. Memory works in standard mode
1: Page Mode enabled. Only one half of butterfly array selected. Page Mode will select either LSB half or MSB half of the word based on PGS setting.

This mode can be used for additional power saving		 RW 0
3 PGS 0: Select LSB half of word during Page Mode, PAGE = 1
1: Select MSB half of word during Page Mode, PAGE = 1		 RW 0
2 BM Burst Mode Enable

0: Burst Mode Disable. Memory works in standard mode.
1: Burst Mode Enable

When in Burst Mode bitline precharge and wordline firing depends on PCH_F and PCH_L.
Burst Mode results in reduction in active power.		 RW 0
1 PCH_F 0: No bitline precharge in second half of cycle
1: Bitline precharge in second half of cycle when in Burst Mode, BM = 1		 RW 0
0 PCH_L 0: No bitline precharge in first half of cycle
1: Bitline precharge in first half of cycle when in Burst Mode, BM = 1		 RW 0

TOP:PRCM:RAMRETEN

Address Offset 0x0000 0224
Physical Address 0x4008 2224 Instance 0x4008 2224
Description Memory Retention Control
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3 RFCULL 0: Retention for RFC ULL SRAM disabled
1: Retention for RFC ULL SRAM enabled

Memories controlled:
CPEULLRAM		 RW 1
2 RFC 0: Retention for RFC SRAM disabled
1: Retention for RFC SRAM enabled

Memories controlled: CPERAM MCERAM RFERAM DSBRAM		 RW 0
1:0 VIMS
0: Memory retention disabled
1: Memory retention enabled

Bit 0: VIMS_TRAM
Bit 1: VIMS_CRAM

Legal modes depend on settings in VIMS:CTL.MODE

00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to CACHE or SPLIT mode after waking up again
01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in GPRAM mode after wake up, alternatively select OFF mode first and then CACHE or SPILT mode.
10: Illegal mode
11: No restrictions		 RW 0b11

TOP:PRCM:OSCIMSC

Address Offset 0x0000 0290
Physical Address 0x4008 2290 Instance 0x4008 2290
Description Oscillator Interrupt Mask
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 HFSRCPENDIM 0: Disable interrupt generation when HFSRCPEND is qualified
1: Enable interrupt generation when HFSRCPEND is qualified		 RW 0
6 LFSRCDONEIM 0: Disable interrupt generation when LFSRCDONE is qualified
1: Enable interrupt generation when LFSRCDONE is qualified		 RW 0
5 XOSCDLFIM 0: Disable interrupt generation when XOSCDLF is qualified
1: Enable interrupt generation when XOSCDLF is qualified		 RW 1
4 XOSCLFIM 0: Disable interrupt generation when XOSCLF is qualified
1: Enable interrupt generation when XOSCLF is qualified		 RW 1
3 RCOSCDLFIM 0: Disable interrupt generation when RCOSCDLF is qualified
1: Enable interrupt generation when RCOSCDLF is qualified		 RW 0
2 RCOSCLFIM 0: Disable interrupt generation when RCOSCLF is qualified
1: Enable interrupt generation when RCOSCLF is qualified		 RW 1
1 XOSCHFIM 0: Disable interrupt generation when XOSCHF is qualified
1: Enable interrupt generation when XOSCHF is qualified		 RW 1
0 RCOSCHFIM 0: Disable interrupt generation when RCOSCHF is qualified
1: Enable interrupt generation when RCOSCHF is qualified		 RW 0

TOP:PRCM:OSCRIS

Address Offset 0x0000 0294
Physical Address 0x4008 2294 Instance 0x4008 2294
Description Oscillator Raw Interrupt Status
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 HFSRCPENDRIS 0: HFSRCPEND has not been qualified
1: HFSRCPEND has been qualified since last clear

Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.

Set by HW. Cleared by writing to OSCICR.HFSRCPENDC		 RO 0
6 LFSRCDONERIS 0: LFSRCDONE has not been qualified
1: LFSRCDONE has been qualified since last clear

Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.

Set by HW. Cleared by writing to OSCICR.LFSRCDONEC		 RO 0
5 XOSCDLFRIS 0: XOSCDLF has not been qualified
1: XOSCDLF has been qualified since last clear.

Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.

Set by HW. Cleared by writing to OSCICR.XOSCDLFC		 RO 0
4 XOSCLFRIS 0: XOSCLF has not been qualified
1: XOSCLF has been qualified since last clear.

Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.

Set by HW. Cleared by writing to OSCICR.XOSCLFC		 RO 0
3 RCOSCDLFRIS 0: RCOSCDLF has not been qualified
1: RCOSCDLF has been qualified since last clear.

Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.

Set by HW. Cleared by writing to OSCICR.RCOSCDLFC		 RO 0
2 RCOSCLFRIS 0: RCOSCLF has not been qualified
1: RCOSCLF has been qualified since last clear.

Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.

Set by HW. Cleared by writing to OSCICR.RCOSCLFC		 RO 0
1 XOSCHFRIS 0: XOSCHF has not been qualified
1: XOSCHF has been qualified since last clear.

Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.

Set by HW. Cleared by writing to OSCICR.XOSCHFC		 RO 0
0 RCOSCHFRIS 0: RCOSCHF has not been qualified
1: RCOSCHF has been qualified since last clear.

Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt.

Set by HW. Cleared by writing to OSCICR.RCOSCHFC		 RO 0

TOP:PRCM:OSCICR

Address Offset 0x0000 0298
Physical Address 0x4008 2298 Instance 0x4008 2298
Description Oscillator Raw Interrupt Clear
Type WO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. WO 0x00 0000
7 HFSRCPENDC Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 has no effect. WO 0
6 LFSRCDONEC Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 has no effect. WO 0
5 XOSCDLFC Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 has no effect. WO 0
4 XOSCLFC Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 has no effect. WO 0
3 RCOSCDLFC Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 has no effect. WO 0
2 RCOSCLFC Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 has no effect. WO 0
1 XOSCHFC Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 has no effect. WO 0
0 RCOSCHFC Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 has no effect. WO 0


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