hw_cpu_itm.h
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32 
33 
34 #ifndef __HW_CPU_ITM_H__
35 #define __HW_CPU_ITM_H__
36 
37 //*****************************************************************************
38 //
39 // This section defines the register offsets of
40 // CPU_ITM component
41 //
42 //*****************************************************************************
43 // Stimulus Port 0
44 #define CPU_ITM_O_STIM0 0x00000000
45 
46 // Stimulus Port 1
47 #define CPU_ITM_O_STIM1 0x00000004
48 
49 // Stimulus Port 2
50 #define CPU_ITM_O_STIM2 0x00000008
51 
52 // Stimulus Port 3
53 #define CPU_ITM_O_STIM3 0x0000000C
54 
55 // Stimulus Port 4
56 #define CPU_ITM_O_STIM4 0x00000010
57 
58 // Stimulus Port 5
59 #define CPU_ITM_O_STIM5 0x00000014
60 
61 // Stimulus Port 6
62 #define CPU_ITM_O_STIM6 0x00000018
63 
64 // Stimulus Port 7
65 #define CPU_ITM_O_STIM7 0x0000001C
66 
67 // Stimulus Port 8
68 #define CPU_ITM_O_STIM8 0x00000020
69 
70 // Stimulus Port 9
71 #define CPU_ITM_O_STIM9 0x00000024
72 
73 // Stimulus Port 10
74 #define CPU_ITM_O_STIM10 0x00000028
75 
76 // Stimulus Port 11
77 #define CPU_ITM_O_STIM11 0x0000002C
78 
79 // Stimulus Port 12
80 #define CPU_ITM_O_STIM12 0x00000030
81 
82 // Stimulus Port 13
83 #define CPU_ITM_O_STIM13 0x00000034
84 
85 // Stimulus Port 14
86 #define CPU_ITM_O_STIM14 0x00000038
87 
88 // Stimulus Port 15
89 #define CPU_ITM_O_STIM15 0x0000003C
90 
91 // Stimulus Port 16
92 #define CPU_ITM_O_STIM16 0x00000040
93 
94 // Stimulus Port 17
95 #define CPU_ITM_O_STIM17 0x00000044
96 
97 // Stimulus Port 18
98 #define CPU_ITM_O_STIM18 0x00000048
99 
100 // Stimulus Port 19
101 #define CPU_ITM_O_STIM19 0x0000004C
102 
103 // Stimulus Port 20
104 #define CPU_ITM_O_STIM20 0x00000050
105 
106 // Stimulus Port 21
107 #define CPU_ITM_O_STIM21 0x00000054
108 
109 // Stimulus Port 22
110 #define CPU_ITM_O_STIM22 0x00000058
111 
112 // Stimulus Port 23
113 #define CPU_ITM_O_STIM23 0x0000005C
114 
115 // Stimulus Port 24
116 #define CPU_ITM_O_STIM24 0x00000060
117 
118 // Stimulus Port 25
119 #define CPU_ITM_O_STIM25 0x00000064
120 
121 // Stimulus Port 26
122 #define CPU_ITM_O_STIM26 0x00000068
123 
124 // Stimulus Port 27
125 #define CPU_ITM_O_STIM27 0x0000006C
126 
127 // Stimulus Port 28
128 #define CPU_ITM_O_STIM28 0x00000070
129 
130 // Stimulus Port 29
131 #define CPU_ITM_O_STIM29 0x00000074
132 
133 // Stimulus Port 30
134 #define CPU_ITM_O_STIM30 0x00000078
135 
136 // Stimulus Port 31
137 #define CPU_ITM_O_STIM31 0x0000007C
138 
139 // Trace Enable
140 #define CPU_ITM_O_TER 0x00000E00
141 
142 // Trace Privilege
143 #define CPU_ITM_O_TPR 0x00000E40
144 
145 // Trace Control
146 #define CPU_ITM_O_TCR 0x00000E80
147 
148 // Lock Access
149 #define CPU_ITM_O_LAR 0x00000FB0
150 
151 // Lock Status
152 #define CPU_ITM_O_LSR 0x00000FB4
153 
154 //*****************************************************************************
155 //
156 // Register: CPU_ITM_O_STIM0
157 //
158 //*****************************************************************************
159 // Field: [31:0] STIM0
160 //
161 // A write to this location causes data to be written into the FIFO if
162 // TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status
163 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
164 // provide an atomic read-modify-write, so it's users responsibility to ensure
165 // exclusive read-modify-write if this ITM port is used concurrently by
166 // interrupts or other threads.
167 #define CPU_ITM_STIM0_STIM0_W 32
168 #define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF
169 #define CPU_ITM_STIM0_STIM0_S 0
170 
171 //*****************************************************************************
172 //
173 // Register: CPU_ITM_O_STIM1
174 //
175 //*****************************************************************************
176 // Field: [31:0] STIM1
177 //
178 // A write to this location causes data to be written into the FIFO if
179 // TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status
180 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
181 // provide an atomic read-modify-write, so it's users responsibility to ensure
182 // exclusive read-modify-write if this ITM port is used concurrently by
183 // interrupts or other threads.
184 #define CPU_ITM_STIM1_STIM1_W 32
185 #define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF
186 #define CPU_ITM_STIM1_STIM1_S 0
187 
188 //*****************************************************************************
189 //
190 // Register: CPU_ITM_O_STIM2
191 //
192 //*****************************************************************************
193 // Field: [31:0] STIM2
194 //
195 // A write to this location causes data to be written into the FIFO if
196 // TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status
197 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
198 // provide an atomic read-modify-write, so it's users responsibility to ensure
199 // exclusive read-modify-write if this ITM port is used concurrently by
200 // interrupts or other threads.
201 #define CPU_ITM_STIM2_STIM2_W 32
202 #define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF
203 #define CPU_ITM_STIM2_STIM2_S 0
204 
205 //*****************************************************************************
206 //
207 // Register: CPU_ITM_O_STIM3
208 //
209 //*****************************************************************************
210 // Field: [31:0] STIM3
211 //
212 // A write to this location causes data to be written into the FIFO if
213 // TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status
214 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
215 // provide an atomic read-modify-write, so it's users responsibility to ensure
216 // exclusive read-modify-write if this ITM port is used concurrently by
217 // interrupts or other threads.
218 #define CPU_ITM_STIM3_STIM3_W 32
219 #define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF
220 #define CPU_ITM_STIM3_STIM3_S 0
221 
222 //*****************************************************************************
223 //
224 // Register: CPU_ITM_O_STIM4
225 //
226 //*****************************************************************************
227 // Field: [31:0] STIM4
228 //
229 // A write to this location causes data to be written into the FIFO if
230 // TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status
231 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
232 // provide an atomic read-modify-write, so it's users responsibility to ensure
233 // exclusive read-modify-write if this ITM port is used concurrently by
234 // interrupts or other threads.
235 #define CPU_ITM_STIM4_STIM4_W 32
236 #define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF
237 #define CPU_ITM_STIM4_STIM4_S 0
238 
239 //*****************************************************************************
240 //
241 // Register: CPU_ITM_O_STIM5
242 //
243 //*****************************************************************************
244 // Field: [31:0] STIM5
245 //
246 // A write to this location causes data to be written into the FIFO if
247 // TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status
248 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
249 // provide an atomic read-modify-write, so it's users responsibility to ensure
250 // exclusive read-modify-write if this ITM port is used concurrently by
251 // interrupts or other threads.
252 #define CPU_ITM_STIM5_STIM5_W 32
253 #define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF
254 #define CPU_ITM_STIM5_STIM5_S 0
255 
256 //*****************************************************************************
257 //
258 // Register: CPU_ITM_O_STIM6
259 //
260 //*****************************************************************************
261 // Field: [31:0] STIM6
262 //
263 // A write to this location causes data to be written into the FIFO if
264 // TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status
265 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
266 // provide an atomic read-modify-write, so it's users responsibility to ensure
267 // exclusive read-modify-write if this ITM port is used concurrently by
268 // interrupts or other threads.
269 #define CPU_ITM_STIM6_STIM6_W 32
270 #define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF
271 #define CPU_ITM_STIM6_STIM6_S 0
272 
273 //*****************************************************************************
274 //
275 // Register: CPU_ITM_O_STIM7
276 //
277 //*****************************************************************************
278 // Field: [31:0] STIM7
279 //
280 // A write to this location causes data to be written into the FIFO if
281 // TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status
282 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
283 // provide an atomic read-modify-write, so it's users responsibility to ensure
284 // exclusive read-modify-write if this ITM port is used concurrently by
285 // interrupts or other threads.
286 #define CPU_ITM_STIM7_STIM7_W 32
287 #define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF
288 #define CPU_ITM_STIM7_STIM7_S 0
289 
290 //*****************************************************************************
291 //
292 // Register: CPU_ITM_O_STIM8
293 //
294 //*****************************************************************************
295 // Field: [31:0] STIM8
296 //
297 // A write to this location causes data to be written into the FIFO if
298 // TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status
299 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
300 // provide an atomic read-modify-write, so it's users responsibility to ensure
301 // exclusive read-modify-write if this ITM port is used concurrently by
302 // interrupts or other threads.
303 #define CPU_ITM_STIM8_STIM8_W 32
304 #define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF
305 #define CPU_ITM_STIM8_STIM8_S 0
306 
307 //*****************************************************************************
308 //
309 // Register: CPU_ITM_O_STIM9
310 //
311 //*****************************************************************************
312 // Field: [31:0] STIM9
313 //
314 // A write to this location causes data to be written into the FIFO if
315 // TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status
316 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
317 // provide an atomic read-modify-write, so it's users responsibility to ensure
318 // exclusive read-modify-write if this ITM port is used concurrently by
319 // interrupts or other threads.
320 #define CPU_ITM_STIM9_STIM9_W 32
321 #define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF
322 #define CPU_ITM_STIM9_STIM9_S 0
323 
324 //*****************************************************************************
325 //
326 // Register: CPU_ITM_O_STIM10
327 //
328 //*****************************************************************************
329 // Field: [31:0] STIM10
330 //
331 // A write to this location causes data to be written into the FIFO if
332 // TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status
333 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
334 // provide an atomic read-modify-write, so it's users responsibility to ensure
335 // exclusive read-modify-write if this ITM port is used concurrently by
336 // interrupts or other threads.
337 #define CPU_ITM_STIM10_STIM10_W 32
338 #define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF
339 #define CPU_ITM_STIM10_STIM10_S 0
340 
341 //*****************************************************************************
342 //
343 // Register: CPU_ITM_O_STIM11
344 //
345 //*****************************************************************************
346 // Field: [31:0] STIM11
347 //
348 // A write to this location causes data to be written into the FIFO if
349 // TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status
350 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
351 // provide an atomic read-modify-write, so it's users responsibility to ensure
352 // exclusive read-modify-write if this ITM port is used concurrently by
353 // interrupts or other threads.
354 #define CPU_ITM_STIM11_STIM11_W 32
355 #define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF
356 #define CPU_ITM_STIM11_STIM11_S 0
357 
358 //*****************************************************************************
359 //
360 // Register: CPU_ITM_O_STIM12
361 //
362 //*****************************************************************************
363 // Field: [31:0] STIM12
364 //
365 // A write to this location causes data to be written into the FIFO if
366 // TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status
367 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
368 // provide an atomic read-modify-write, so it's users responsibility to ensure
369 // exclusive read-modify-write if this ITM port is used concurrently by
370 // interrupts or other threads.
371 #define CPU_ITM_STIM12_STIM12_W 32
372 #define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF
373 #define CPU_ITM_STIM12_STIM12_S 0
374 
375 //*****************************************************************************
376 //
377 // Register: CPU_ITM_O_STIM13
378 //
379 //*****************************************************************************
380 // Field: [31:0] STIM13
381 //
382 // A write to this location causes data to be written into the FIFO if
383 // TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status
384 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
385 // provide an atomic read-modify-write, so it's users responsibility to ensure
386 // exclusive read-modify-write if this ITM port is used concurrently by
387 // interrupts or other threads.
388 #define CPU_ITM_STIM13_STIM13_W 32
389 #define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF
390 #define CPU_ITM_STIM13_STIM13_S 0
391 
392 //*****************************************************************************
393 //
394 // Register: CPU_ITM_O_STIM14
395 //
396 //*****************************************************************************
397 // Field: [31:0] STIM14
398 //
399 // A write to this location causes data to be written into the FIFO if
400 // TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status
401 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
402 // provide an atomic read-modify-write, so it's users responsibility to ensure
403 // exclusive read-modify-write if this ITM port is used concurrently by
404 // interrupts or other threads.
405 #define CPU_ITM_STIM14_STIM14_W 32
406 #define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF
407 #define CPU_ITM_STIM14_STIM14_S 0
408 
409 //*****************************************************************************
410 //
411 // Register: CPU_ITM_O_STIM15
412 //
413 //*****************************************************************************
414 // Field: [31:0] STIM15
415 //
416 // A write to this location causes data to be written into the FIFO if
417 // TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status
418 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
419 // provide an atomic read-modify-write, so it's users responsibility to ensure
420 // exclusive read-modify-write if this ITM port is used concurrently by
421 // interrupts or other threads.
422 #define CPU_ITM_STIM15_STIM15_W 32
423 #define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF
424 #define CPU_ITM_STIM15_STIM15_S 0
425 
426 //*****************************************************************************
427 //
428 // Register: CPU_ITM_O_STIM16
429 //
430 //*****************************************************************************
431 // Field: [31:0] STIM16
432 //
433 // A write to this location causes data to be written into the FIFO if
434 // TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status
435 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
436 // provide an atomic read-modify-write, so it's users responsibility to ensure
437 // exclusive read-modify-write if this ITM port is used concurrently by
438 // interrupts or other threads.
439 #define CPU_ITM_STIM16_STIM16_W 32
440 #define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF
441 #define CPU_ITM_STIM16_STIM16_S 0
442 
443 //*****************************************************************************
444 //
445 // Register: CPU_ITM_O_STIM17
446 //
447 //*****************************************************************************
448 // Field: [31:0] STIM17
449 //
450 // A write to this location causes data to be written into the FIFO if
451 // TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status
452 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
453 // provide an atomic read-modify-write, so it's users responsibility to ensure
454 // exclusive read-modify-write if this ITM port is used concurrently by
455 // interrupts or other threads.
456 #define CPU_ITM_STIM17_STIM17_W 32
457 #define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF
458 #define CPU_ITM_STIM17_STIM17_S 0
459 
460 //*****************************************************************************
461 //
462 // Register: CPU_ITM_O_STIM18
463 //
464 //*****************************************************************************
465 // Field: [31:0] STIM18
466 //
467 // A write to this location causes data to be written into the FIFO if
468 // TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status
469 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
470 // provide an atomic read-modify-write, so it's users responsibility to ensure
471 // exclusive read-modify-write if this ITM port is used concurrently by
472 // interrupts or other threads.
473 #define CPU_ITM_STIM18_STIM18_W 32
474 #define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF
475 #define CPU_ITM_STIM18_STIM18_S 0
476 
477 //*****************************************************************************
478 //
479 // Register: CPU_ITM_O_STIM19
480 //
481 //*****************************************************************************
482 // Field: [31:0] STIM19
483 //
484 // A write to this location causes data to be written into the FIFO if
485 // TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status
486 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
487 // provide an atomic read-modify-write, so it's users responsibility to ensure
488 // exclusive read-modify-write if this ITM port is used concurrently by
489 // interrupts or other threads.
490 #define CPU_ITM_STIM19_STIM19_W 32
491 #define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF
492 #define CPU_ITM_STIM19_STIM19_S 0
493 
494 //*****************************************************************************
495 //
496 // Register: CPU_ITM_O_STIM20
497 //
498 //*****************************************************************************
499 // Field: [31:0] STIM20
500 //
501 // A write to this location causes data to be written into the FIFO if
502 // TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status
503 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
504 // provide an atomic read-modify-write, so it's users responsibility to ensure
505 // exclusive read-modify-write if this ITM port is used concurrently by
506 // interrupts or other threads.
507 #define CPU_ITM_STIM20_STIM20_W 32
508 #define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF
509 #define CPU_ITM_STIM20_STIM20_S 0
510 
511 //*****************************************************************************
512 //
513 // Register: CPU_ITM_O_STIM21
514 //
515 //*****************************************************************************
516 // Field: [31:0] STIM21
517 //
518 // A write to this location causes data to be written into the FIFO if
519 // TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status
520 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
521 // provide an atomic read-modify-write, so it's users responsibility to ensure
522 // exclusive read-modify-write if this ITM port is used concurrently by
523 // interrupts or other threads.
524 #define CPU_ITM_STIM21_STIM21_W 32
525 #define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF
526 #define CPU_ITM_STIM21_STIM21_S 0
527 
528 //*****************************************************************************
529 //
530 // Register: CPU_ITM_O_STIM22
531 //
532 //*****************************************************************************
533 // Field: [31:0] STIM22
534 //
535 // A write to this location causes data to be written into the FIFO if
536 // TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status
537 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
538 // provide an atomic read-modify-write, so it's users responsibility to ensure
539 // exclusive read-modify-write if this ITM port is used concurrently by
540 // interrupts or other threads.
541 #define CPU_ITM_STIM22_STIM22_W 32
542 #define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF
543 #define CPU_ITM_STIM22_STIM22_S 0
544 
545 //*****************************************************************************
546 //
547 // Register: CPU_ITM_O_STIM23
548 //
549 //*****************************************************************************
550 // Field: [31:0] STIM23
551 //
552 // A write to this location causes data to be written into the FIFO if
553 // TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status
554 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
555 // provide an atomic read-modify-write, so it's users responsibility to ensure
556 // exclusive read-modify-write if this ITM port is used concurrently by
557 // interrupts or other threads.
558 #define CPU_ITM_STIM23_STIM23_W 32
559 #define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF
560 #define CPU_ITM_STIM23_STIM23_S 0
561 
562 //*****************************************************************************
563 //
564 // Register: CPU_ITM_O_STIM24
565 //
566 //*****************************************************************************
567 // Field: [31:0] STIM24
568 //
569 // A write to this location causes data to be written into the FIFO if
570 // TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status
571 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
572 // provide an atomic read-modify-write, so it's users responsibility to ensure
573 // exclusive read-modify-write if this ITM port is used concurrently by
574 // interrupts or other threads.
575 #define CPU_ITM_STIM24_STIM24_W 32
576 #define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF
577 #define CPU_ITM_STIM24_STIM24_S 0
578 
579 //*****************************************************************************
580 //
581 // Register: CPU_ITM_O_STIM25
582 //
583 //*****************************************************************************
584 // Field: [31:0] STIM25
585 //
586 // A write to this location causes data to be written into the FIFO if
587 // TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status
588 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
589 // provide an atomic read-modify-write, so it's users responsibility to ensure
590 // exclusive read-modify-write if this ITM port is used concurrently by
591 // interrupts or other threads.
592 #define CPU_ITM_STIM25_STIM25_W 32
593 #define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF
594 #define CPU_ITM_STIM25_STIM25_S 0
595 
596 //*****************************************************************************
597 //
598 // Register: CPU_ITM_O_STIM26
599 //
600 //*****************************************************************************
601 // Field: [31:0] STIM26
602 //
603 // A write to this location causes data to be written into the FIFO if
604 // TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status
605 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
606 // provide an atomic read-modify-write, so it's users responsibility to ensure
607 // exclusive read-modify-write if this ITM port is used concurrently by
608 // interrupts or other threads.
609 #define CPU_ITM_STIM26_STIM26_W 32
610 #define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF
611 #define CPU_ITM_STIM26_STIM26_S 0
612 
613 //*****************************************************************************
614 //
615 // Register: CPU_ITM_O_STIM27
616 //
617 //*****************************************************************************
618 // Field: [31:0] STIM27
619 //
620 // A write to this location causes data to be written into the FIFO if
621 // TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status
622 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
623 // provide an atomic read-modify-write, so it's users responsibility to ensure
624 // exclusive read-modify-write if this ITM port is used concurrently by
625 // interrupts or other threads.
626 #define CPU_ITM_STIM27_STIM27_W 32
627 #define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF
628 #define CPU_ITM_STIM27_STIM27_S 0
629 
630 //*****************************************************************************
631 //
632 // Register: CPU_ITM_O_STIM28
633 //
634 //*****************************************************************************
635 // Field: [31:0] STIM28
636 //
637 // A write to this location causes data to be written into the FIFO if
638 // TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status
639 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
640 // provide an atomic read-modify-write, so it's users responsibility to ensure
641 // exclusive read-modify-write if this ITM port is used concurrently by
642 // interrupts or other threads.
643 #define CPU_ITM_STIM28_STIM28_W 32
644 #define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF
645 #define CPU_ITM_STIM28_STIM28_S 0
646 
647 //*****************************************************************************
648 //
649 // Register: CPU_ITM_O_STIM29
650 //
651 //*****************************************************************************
652 // Field: [31:0] STIM29
653 //
654 // A write to this location causes data to be written into the FIFO if
655 // TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status
656 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
657 // provide an atomic read-modify-write, so it's users responsibility to ensure
658 // exclusive read-modify-write if this ITM port is used concurrently by
659 // interrupts or other threads.
660 #define CPU_ITM_STIM29_STIM29_W 32
661 #define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF
662 #define CPU_ITM_STIM29_STIM29_S 0
663 
664 //*****************************************************************************
665 //
666 // Register: CPU_ITM_O_STIM30
667 //
668 //*****************************************************************************
669 // Field: [31:0] STIM30
670 //
671 // A write to this location causes data to be written into the FIFO if
672 // TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status
673 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
674 // provide an atomic read-modify-write, so it's users responsibility to ensure
675 // exclusive read-modify-write if this ITM port is used concurrently by
676 // interrupts or other threads.
677 #define CPU_ITM_STIM30_STIM30_W 32
678 #define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF
679 #define CPU_ITM_STIM30_STIM30_S 0
680 
681 //*****************************************************************************
682 //
683 // Register: CPU_ITM_O_STIM31
684 //
685 //*****************************************************************************
686 // Field: [31:0] STIM31
687 //
688 // A write to this location causes data to be written into the FIFO if
689 // TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status
690 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
691 // provide an atomic read-modify-write, so it's users responsibility to ensure
692 // exclusive read-modify-write if this ITM port is used concurrently by
693 // interrupts or other threads.
694 #define CPU_ITM_STIM31_STIM31_W 32
695 #define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF
696 #define CPU_ITM_STIM31_STIM31_S 0
697 
698 //*****************************************************************************
699 //
700 // Register: CPU_ITM_O_TER
701 //
702 //*****************************************************************************
703 // Field: [31] STIMENA31
704 //
705 // Bit mask to enable tracing on ITM stimulus port 31.
706 #define CPU_ITM_TER_STIMENA31 0x80000000
707 #define CPU_ITM_TER_STIMENA31_BITN 31
708 #define CPU_ITM_TER_STIMENA31_M 0x80000000
709 #define CPU_ITM_TER_STIMENA31_S 31
710 
711 // Field: [30] STIMENA30
712 //
713 // Bit mask to enable tracing on ITM stimulus port 30.
714 #define CPU_ITM_TER_STIMENA30 0x40000000
715 #define CPU_ITM_TER_STIMENA30_BITN 30
716 #define CPU_ITM_TER_STIMENA30_M 0x40000000
717 #define CPU_ITM_TER_STIMENA30_S 30
718 
719 // Field: [29] STIMENA29
720 //
721 // Bit mask to enable tracing on ITM stimulus port 29.
722 #define CPU_ITM_TER_STIMENA29 0x20000000
723 #define CPU_ITM_TER_STIMENA29_BITN 29
724 #define CPU_ITM_TER_STIMENA29_M 0x20000000
725 #define CPU_ITM_TER_STIMENA29_S 29
726 
727 // Field: [28] STIMENA28
728 //
729 // Bit mask to enable tracing on ITM stimulus port 28.
730 #define CPU_ITM_TER_STIMENA28 0x10000000
731 #define CPU_ITM_TER_STIMENA28_BITN 28
732 #define CPU_ITM_TER_STIMENA28_M 0x10000000
733 #define CPU_ITM_TER_STIMENA28_S 28
734 
735 // Field: [27] STIMENA27
736 //
737 // Bit mask to enable tracing on ITM stimulus port 27.
738 #define CPU_ITM_TER_STIMENA27 0x08000000
739 #define CPU_ITM_TER_STIMENA27_BITN 27
740 #define CPU_ITM_TER_STIMENA27_M 0x08000000
741 #define CPU_ITM_TER_STIMENA27_S 27
742 
743 // Field: [26] STIMENA26
744 //
745 // Bit mask to enable tracing on ITM stimulus port 26.
746 #define CPU_ITM_TER_STIMENA26 0x04000000
747 #define CPU_ITM_TER_STIMENA26_BITN 26
748 #define CPU_ITM_TER_STIMENA26_M 0x04000000
749 #define CPU_ITM_TER_STIMENA26_S 26
750 
751 // Field: [25] STIMENA25
752 //
753 // Bit mask to enable tracing on ITM stimulus port 25.
754 #define CPU_ITM_TER_STIMENA25 0x02000000
755 #define CPU_ITM_TER_STIMENA25_BITN 25
756 #define CPU_ITM_TER_STIMENA25_M 0x02000000
757 #define CPU_ITM_TER_STIMENA25_S 25
758 
759 // Field: [24] STIMENA24
760 //
761 // Bit mask to enable tracing on ITM stimulus port 24.
762 #define CPU_ITM_TER_STIMENA24 0x01000000
763 #define CPU_ITM_TER_STIMENA24_BITN 24
764 #define CPU_ITM_TER_STIMENA24_M 0x01000000
765 #define CPU_ITM_TER_STIMENA24_S 24
766 
767 // Field: [23] STIMENA23
768 //
769 // Bit mask to enable tracing on ITM stimulus port 23.
770 #define CPU_ITM_TER_STIMENA23 0x00800000
771 #define CPU_ITM_TER_STIMENA23_BITN 23
772 #define CPU_ITM_TER_STIMENA23_M 0x00800000
773 #define CPU_ITM_TER_STIMENA23_S 23
774 
775 // Field: [22] STIMENA22
776 //
777 // Bit mask to enable tracing on ITM stimulus port 22.
778 #define CPU_ITM_TER_STIMENA22 0x00400000
779 #define CPU_ITM_TER_STIMENA22_BITN 22
780 #define CPU_ITM_TER_STIMENA22_M 0x00400000
781 #define CPU_ITM_TER_STIMENA22_S 22
782 
783 // Field: [21] STIMENA21
784 //
785 // Bit mask to enable tracing on ITM stimulus port 21.
786 #define CPU_ITM_TER_STIMENA21 0x00200000
787 #define CPU_ITM_TER_STIMENA21_BITN 21
788 #define CPU_ITM_TER_STIMENA21_M 0x00200000
789 #define CPU_ITM_TER_STIMENA21_S 21
790 
791 // Field: [20] STIMENA20
792 //
793 // Bit mask to enable tracing on ITM stimulus port 20.
794 #define CPU_ITM_TER_STIMENA20 0x00100000
795 #define CPU_ITM_TER_STIMENA20_BITN 20
796 #define CPU_ITM_TER_STIMENA20_M 0x00100000
797 #define CPU_ITM_TER_STIMENA20_S 20
798 
799 // Field: [19] STIMENA19
800 //
801 // Bit mask to enable tracing on ITM stimulus port 19.
802 #define CPU_ITM_TER_STIMENA19 0x00080000
803 #define CPU_ITM_TER_STIMENA19_BITN 19
804 #define CPU_ITM_TER_STIMENA19_M 0x00080000
805 #define CPU_ITM_TER_STIMENA19_S 19
806 
807 // Field: [18] STIMENA18
808 //
809 // Bit mask to enable tracing on ITM stimulus port 18.
810 #define CPU_ITM_TER_STIMENA18 0x00040000
811 #define CPU_ITM_TER_STIMENA18_BITN 18
812 #define CPU_ITM_TER_STIMENA18_M 0x00040000
813 #define CPU_ITM_TER_STIMENA18_S 18
814 
815 // Field: [17] STIMENA17
816 //
817 // Bit mask to enable tracing on ITM stimulus port 17.
818 #define CPU_ITM_TER_STIMENA17 0x00020000
819 #define CPU_ITM_TER_STIMENA17_BITN 17
820 #define CPU_ITM_TER_STIMENA17_M 0x00020000
821 #define CPU_ITM_TER_STIMENA17_S 17
822 
823 // Field: [16] STIMENA16
824 //
825 // Bit mask to enable tracing on ITM stimulus port 16.
826 #define CPU_ITM_TER_STIMENA16 0x00010000
827 #define CPU_ITM_TER_STIMENA16_BITN 16
828 #define CPU_ITM_TER_STIMENA16_M 0x00010000
829 #define CPU_ITM_TER_STIMENA16_S 16
830 
831 // Field: [15] STIMENA15
832 //
833 // Bit mask to enable tracing on ITM stimulus port 15.
834 #define CPU_ITM_TER_STIMENA15 0x00008000
835 #define CPU_ITM_TER_STIMENA15_BITN 15
836 #define CPU_ITM_TER_STIMENA15_M 0x00008000
837 #define CPU_ITM_TER_STIMENA15_S 15
838 
839 // Field: [14] STIMENA14
840 //
841 // Bit mask to enable tracing on ITM stimulus port 14.
842 #define CPU_ITM_TER_STIMENA14 0x00004000
843 #define CPU_ITM_TER_STIMENA14_BITN 14
844 #define CPU_ITM_TER_STIMENA14_M 0x00004000
845 #define CPU_ITM_TER_STIMENA14_S 14
846 
847 // Field: [13] STIMENA13
848 //
849 // Bit mask to enable tracing on ITM stimulus port 13.
850 #define CPU_ITM_TER_STIMENA13 0x00002000
851 #define CPU_ITM_TER_STIMENA13_BITN 13
852 #define CPU_ITM_TER_STIMENA13_M 0x00002000
853 #define CPU_ITM_TER_STIMENA13_S 13
854 
855 // Field: [12] STIMENA12
856 //
857 // Bit mask to enable tracing on ITM stimulus port 12.
858 #define CPU_ITM_TER_STIMENA12 0x00001000
859 #define CPU_ITM_TER_STIMENA12_BITN 12
860 #define CPU_ITM_TER_STIMENA12_M 0x00001000
861 #define CPU_ITM_TER_STIMENA12_S 12
862 
863 // Field: [11] STIMENA11
864 //
865 // Bit mask to enable tracing on ITM stimulus port 11.
866 #define CPU_ITM_TER_STIMENA11 0x00000800
867 #define CPU_ITM_TER_STIMENA11_BITN 11
868 #define CPU_ITM_TER_STIMENA11_M 0x00000800
869 #define CPU_ITM_TER_STIMENA11_S 11
870 
871 // Field: [10] STIMENA10
872 //
873 // Bit mask to enable tracing on ITM stimulus port 10.
874 #define CPU_ITM_TER_STIMENA10 0x00000400
875 #define CPU_ITM_TER_STIMENA10_BITN 10
876 #define CPU_ITM_TER_STIMENA10_M 0x00000400
877 #define CPU_ITM_TER_STIMENA10_S 10
878 
879 // Field: [9] STIMENA9
880 //
881 // Bit mask to enable tracing on ITM stimulus port 9.
882 #define CPU_ITM_TER_STIMENA9 0x00000200
883 #define CPU_ITM_TER_STIMENA9_BITN 9
884 #define CPU_ITM_TER_STIMENA9_M 0x00000200
885 #define CPU_ITM_TER_STIMENA9_S 9
886 
887 // Field: [8] STIMENA8
888 //
889 // Bit mask to enable tracing on ITM stimulus port 8.
890 #define CPU_ITM_TER_STIMENA8 0x00000100
891 #define CPU_ITM_TER_STIMENA8_BITN 8
892 #define CPU_ITM_TER_STIMENA8_M 0x00000100
893 #define CPU_ITM_TER_STIMENA8_S 8
894 
895 // Field: [7] STIMENA7
896 //
897 // Bit mask to enable tracing on ITM stimulus port 7.
898 #define CPU_ITM_TER_STIMENA7 0x00000080
899 #define CPU_ITM_TER_STIMENA7_BITN 7
900 #define CPU_ITM_TER_STIMENA7_M 0x00000080
901 #define CPU_ITM_TER_STIMENA7_S 7
902 
903 // Field: [6] STIMENA6
904 //
905 // Bit mask to enable tracing on ITM stimulus port 6.
906 #define CPU_ITM_TER_STIMENA6 0x00000040
907 #define CPU_ITM_TER_STIMENA6_BITN 6
908 #define CPU_ITM_TER_STIMENA6_M 0x00000040
909 #define CPU_ITM_TER_STIMENA6_S 6
910 
911 // Field: [5] STIMENA5
912 //
913 // Bit mask to enable tracing on ITM stimulus port 5.
914 #define CPU_ITM_TER_STIMENA5 0x00000020
915 #define CPU_ITM_TER_STIMENA5_BITN 5
916 #define CPU_ITM_TER_STIMENA5_M 0x00000020
917 #define CPU_ITM_TER_STIMENA5_S 5
918 
919 // Field: [4] STIMENA4
920 //
921 // Bit mask to enable tracing on ITM stimulus port 4.
922 #define CPU_ITM_TER_STIMENA4 0x00000010
923 #define CPU_ITM_TER_STIMENA4_BITN 4
924 #define CPU_ITM_TER_STIMENA4_M 0x00000010
925 #define CPU_ITM_TER_STIMENA4_S 4
926 
927 // Field: [3] STIMENA3
928 //
929 // Bit mask to enable tracing on ITM stimulus port 3.
930 #define CPU_ITM_TER_STIMENA3 0x00000008
931 #define CPU_ITM_TER_STIMENA3_BITN 3
932 #define CPU_ITM_TER_STIMENA3_M 0x00000008
933 #define CPU_ITM_TER_STIMENA3_S 3
934 
935 // Field: [2] STIMENA2
936 //
937 // Bit mask to enable tracing on ITM stimulus port 2.
938 #define CPU_ITM_TER_STIMENA2 0x00000004
939 #define CPU_ITM_TER_STIMENA2_BITN 2
940 #define CPU_ITM_TER_STIMENA2_M 0x00000004
941 #define CPU_ITM_TER_STIMENA2_S 2
942 
943 // Field: [1] STIMENA1
944 //
945 // Bit mask to enable tracing on ITM stimulus port 1.
946 #define CPU_ITM_TER_STIMENA1 0x00000002
947 #define CPU_ITM_TER_STIMENA1_BITN 1
948 #define CPU_ITM_TER_STIMENA1_M 0x00000002
949 #define CPU_ITM_TER_STIMENA1_S 1
950 
951 // Field: [0] STIMENA0
952 //
953 // Bit mask to enable tracing on ITM stimulus port 0.
954 #define CPU_ITM_TER_STIMENA0 0x00000001
955 #define CPU_ITM_TER_STIMENA0_BITN 0
956 #define CPU_ITM_TER_STIMENA0_M 0x00000001
957 #define CPU_ITM_TER_STIMENA0_S 0
958 
959 //*****************************************************************************
960 //
961 // Register: CPU_ITM_O_TPR
962 //
963 //*****************************************************************************
964 // Field: [3:0] PRIVMASK
965 //
966 // Bit mask to enable unprivileged (User) access to ITM stimulus ports:
967 //
968 // Bit [0] enables stimulus ports 0, 1, ..., and 7.
969 // Bit [1] enables stimulus ports 8, 9, ..., and 15.
970 // Bit [2] enables stimulus ports 16, 17, ..., and 23.
971 // Bit [3] enables stimulus ports 24, 25, ..., and 31.
972 //
973 // 0: User access allowed to stimulus ports
974 // 1: Privileged access only to stimulus ports
975 #define CPU_ITM_TPR_PRIVMASK_W 4
976 #define CPU_ITM_TPR_PRIVMASK_M 0x0000000F
977 #define CPU_ITM_TPR_PRIVMASK_S 0
978 
979 //*****************************************************************************
980 //
981 // Register: CPU_ITM_O_TCR
982 //
983 //*****************************************************************************
984 // Field: [23] BUSY
985 //
986 // Set when ITM events present and being drained.
987 #define CPU_ITM_TCR_BUSY 0x00800000
988 #define CPU_ITM_TCR_BUSY_BITN 23
989 #define CPU_ITM_TCR_BUSY_M 0x00800000
990 #define CPU_ITM_TCR_BUSY_S 23
991 
992 // Field: [22:16] ATBID
993 //
994 // Trace Bus ID for CoreSight system. Optional identifier for multi-source
995 // trace stream formatting. If multi-source trace is in use, this field must be
996 // written with a non-zero value.
997 #define CPU_ITM_TCR_ATBID_W 7
998 #define CPU_ITM_TCR_ATBID_M 0x007F0000
999 #define CPU_ITM_TCR_ATBID_S 16
1000 
1001 // Field: [9:8] TSPRESCALE
1002 //
1003 // Timestamp prescaler
1004 // ENUMs:
1005 // DIV64 Divide by 64
1006 // DIV16 Divide by 16
1007 // DIV4 Divide by 4
1008 // NOPRESCALING No prescaling
1009 #define CPU_ITM_TCR_TSPRESCALE_W 2
1010 #define CPU_ITM_TCR_TSPRESCALE_M 0x00000300
1011 #define CPU_ITM_TCR_TSPRESCALE_S 8
1012 #define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300
1013 #define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200
1014 #define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100
1015 #define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000
1016 
1017 // Field: [4] SWOENA
1018 //
1019 // Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If
1020 // TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of
1021 // the timestamp counter.
1022 //
1023 // 0x0: Mode disabled. Timestamp counter uses system clock from the core and
1024 // counts continuously.
1025 // 0x1: Timestamp counter uses lineout (data related) clock from TPIU
1026 // interface. The timestamp counter is held in reset while the output line is
1027 // idle.
1028 #define CPU_ITM_TCR_SWOENA 0x00000010
1029 #define CPU_ITM_TCR_SWOENA_BITN 4
1030 #define CPU_ITM_TCR_SWOENA_M 0x00000010
1031 #define CPU_ITM_TCR_SWOENA_S 4
1032 
1033 // Field: [3] DWTENA
1034 //
1035 // Enables the DWT stimulus (hardware event packet emission to the TPIU from
1036 // the DWT)
1037 #define CPU_ITM_TCR_DWTENA 0x00000008
1038 #define CPU_ITM_TCR_DWTENA_BITN 3
1039 #define CPU_ITM_TCR_DWTENA_M 0x00000008
1040 #define CPU_ITM_TCR_DWTENA_S 3
1041 
1042 // Field: [2] SYNCENA
1043 //
1044 // Enables synchronization packet transmission for a synchronous TPIU.
1045 // CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization
1046 // speed.
1047 #define CPU_ITM_TCR_SYNCENA 0x00000004
1048 #define CPU_ITM_TCR_SYNCENA_BITN 2
1049 #define CPU_ITM_TCR_SYNCENA_M 0x00000004
1050 #define CPU_ITM_TCR_SYNCENA_S 2
1051 
1052 // Field: [1] TSENA
1053 //
1054 // Enables differential timestamps. Differential timestamps are emitted when a
1055 // packet is written to the FIFO with a non-zero timestamp counter, and when
1056 // the timestamp counter overflows. Timestamps are emitted during idle times
1057 // after a fixed number of two million cycles. This provides a time reference
1058 // for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps
1059 // are triggered by activity on the internal trace bus only. In this case there
1060 // is no regular timestamp output when the ITM is idle.
1061 #define CPU_ITM_TCR_TSENA 0x00000002
1062 #define CPU_ITM_TCR_TSENA_BITN 1
1063 #define CPU_ITM_TCR_TSENA_M 0x00000002
1064 #define CPU_ITM_TCR_TSENA_S 1
1065 
1066 // Field: [0] ITMENA
1067 //
1068 // Enables ITM. This is the master enable, and must be set before ITM Stimulus
1069 // and Trace Enable registers can be written.
1070 #define CPU_ITM_TCR_ITMENA 0x00000001
1071 #define CPU_ITM_TCR_ITMENA_BITN 0
1072 #define CPU_ITM_TCR_ITMENA_M 0x00000001
1073 #define CPU_ITM_TCR_ITMENA_S 0
1074 
1075 //*****************************************************************************
1076 //
1077 // Register: CPU_ITM_O_LAR
1078 //
1079 //*****************************************************************************
1080 // Field: [31:0] LOCK_ACCESS
1081 //
1082 // A privileged write of 0xC5ACCE55 enables more write access to Control
1083 // Registers TER, TPR and TCR. An invalid write removes write access.
1084 #define CPU_ITM_LAR_LOCK_ACCESS_W 32
1085 #define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF
1086 #define CPU_ITM_LAR_LOCK_ACCESS_S 0
1087 
1088 //*****************************************************************************
1089 //
1090 // Register: CPU_ITM_O_LSR
1091 //
1092 //*****************************************************************************
1093 // Field: [2] BYTEACC
1094 //
1095 // Reads 0 which means 8-bit lock access is not be implemented.
1096 #define CPU_ITM_LSR_BYTEACC 0x00000004
1097 #define CPU_ITM_LSR_BYTEACC_BITN 2
1098 #define CPU_ITM_LSR_BYTEACC_M 0x00000004
1099 #define CPU_ITM_LSR_BYTEACC_S 2
1100 
1101 // Field: [1] ACCESS
1102 //
1103 // Write access to component is blocked. All writes are ignored, reads are
1104 // permitted.
1105 #define CPU_ITM_LSR_ACCESS 0x00000002
1106 #define CPU_ITM_LSR_ACCESS_BITN 1
1107 #define CPU_ITM_LSR_ACCESS_M 0x00000002
1108 #define CPU_ITM_LSR_ACCESS_S 1
1109 
1110 // Field: [0] PRESENT
1111 //
1112 // Indicates that a lock mechanism exists for this component.
1113 #define CPU_ITM_LSR_PRESENT 0x00000001
1114 #define CPU_ITM_LSR_PRESENT_BITN 0
1115 #define CPU_ITM_LSR_PRESENT_M 0x00000001
1116 #define CPU_ITM_LSR_PRESENT_S 0
1117 
1118 
1119 #endif // __CPU_ITM__
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