Instance: AUX_SPIM
Component: AUX_SPIM
Base address: 0x400C1000
The AUX Serial Peripheral Interface Master (AUX_SPIM) enables AUX_SCE with power-efficient SPI communication.
It is not possible to write a register while SPI transmission occurs. An attempt to do so will stall the bus until transmission is complete.
Read of RX8.DATA or RX16.DATA stalls the bus until LSB has been captured. Read of SCLKIDLE.STAT or DATAIDLE.STAT stalls the bus until condition described is met. Other read operations do not stall the bus.
AUX_SCE becomes clock gated if it encounters a bus stall. This is useful as AUX_SCE can write TX8.DATA and then read RX8.DATA immediately to read a SPI slave. In such case there is no need for software to wait or to poll registers.
AUX_SYSIF:PEROPRATE.SPIM_OP_RATE selects the peripheral clock frequency which is used to derive the SCLK frequency.
AUX_SCE must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to SCE_RATE to access and use AUX_SPIM. System CPU must set AUX_SYSIF:PEROPRATE.SPIM_OP_RATE to BUS_RATE to access and use AUX_SPIM. Failure to do so can result in incorrect SPI transmission.
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 1000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C 1004 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C 1008 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 000C |
0x400C 100C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 1010 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 1014 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 1018 |
|
|
RO |
32 |
0x0000 0001 |
0x0000 001C |
0x400C 101C |
|
|
RO |
32 |
0x0000 0001 |
0x0000 0020 |
0x400C 1020 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x400C 1000 | Instance | 0x400C 1000 |
| Description | SPI Master Configuration Write operation stalls until current transfer completes. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:2 | DIV | SCLK divider. Peripheral clock frequency division gives the SCLK clock frequency. The division factor equals (2 * (DIV+1)): 0x00: Divide by 2. 0x01: Divide by 4. 0x02: Divide by 6. ... 0x3F: Divide by 128. |
RW | 0b00 0000 | ||
| 1 | PHA | Phase of the MOSI and MISO data signals. 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) edges of SCLK. 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) edges of SCLK. |
RW | 0 | ||
| 0 | POL | Polarity of the SCLK signal. 0: SCLK is low when idle, first clock edge rises. 1: SCLK is high when idle, first clock edge falls. |
RW | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x400C 1004 | Instance | 0x400C 1004 |
| Description | MISO Configuration Write operation stalls until current transfer completes. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | AUXIO | AUXIO to MISO mux. Select the AUXIO pin that connects to MISO. |
RW | 0b0 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x400C 1008 | Instance | 0x400C 1008 |
| Description | MOSI Control Write operation stalls until current transfer completes. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | VALUE | MOSI level control. 0: Set MOSI low. 1: Set MOSI high. |
WO | 0 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x400C 100C | Instance | 0x400C 100C |
| Description | Transmit 8 Bit Write operation stalls until current transfer completes. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0x00 0000 | ||
| 7:0 | DATA | 8 bit data transfer. Write DATA to start transfer, MSB first. When transfer completes, MOSI stays at the value of LSB. |
WO | 0x00 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x400C 1010 | Instance | 0x400C 1010 |
| Description | Transmit 16 Bit Write operation stalls until current transfer completes. |
||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0x0000 | ||
| 15:0 | DATA | 16 bit data transfer. Write DATA to start transfer, MSB first. When transfer completes, MOSI stays at the value of LSB. |
WO | 0x0000 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x400C 1014 | Instance | 0x400C 1014 |
| Description | Receive 8 Bit Read operation stalls until current transfer completes. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | DATA | Latest 8 bits received on MISO. | RO | 0x00 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x400C 1018 | Instance | 0x400C 1018 |
| Description | Receive 16 Bit Read operation stalls until current transfer completes. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | DATA | Latest 16 bits received on MISO. | RO | 0x0000 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0x400C 101C | Instance | 0x400C 101C |
| Description | SCLK Idle Read operation stalls until SCLK is idle with no remaining clock edges. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | STAT | Wait for SCLK idle. Read operation stalls until SCLK is idle with no remaining clock edges. Read then returns 1. AUX_SCE can use this to control CS deassertion. |
RO | 1 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0x400C 1020 | Instance | 0x400C 1020 |
| Description | Data Idle Read operation stalls until current transfer completes. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | STAT | Wait for data idle. Read operation stalls until the SCLK period associated with LSB transmission completes. Read then returns 1. AUX_SCE can use this to control CS deassertion. |
RO | 1 | ||
| © 2015 - 2016. Texas Instruments | All Rights Reserved |