Instance: SRAM_MMR
Component: SRAM_MMR
Base address: 0x40035000
General Purpose RAM
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4003 5000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4003 5004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4003 5008 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4003 500C |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4003 5000 | Instance | 0x4003 5000 |
| Description | Parity Error Control Parity error check controls |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
| 8 | PER_DISABLE | Parity Status Disable 0: A parity error will update PER_CHK.PER_ADDR field 1: Parity error does not update PER_CHK.PER_ADDR field |
RW | 0 | ||
| 7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | 0b000 0000 | |||
| 0 | PER_DEBUG_ENABLE | Parity Error Debug Enable 0: Normal operation 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity errors will be generated on reads from within this offset |
RW | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4003 5004 | Instance | 0x4003 5004 |
| Description | Parity Error Check Parity error check results |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:0 | PER_ADDR | Parity Error Address Offset Returns the last address offset which resulted in a parity error during an SRAM read. The address offset returned is always the word-aligned address that contains the location with the parity error. For parity faults on non word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the location that resulted in parity error. |
RO | 0x00 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x4003 5008 | Instance | 0x4003 5008 |
| Description | Parity Error Debug Parity error check debug address setting |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:0 | PER_DEBUG_ADDR | Debug Parity Error Address Offset When PER_CTL.PER_DEBUG is 1, this field is used to set a parity debug address offset. The address offset must be a word-aligned address. Writes within this address offset will force incorrect parity bits to be stored together with the data written. The following reads within this same address offset will thus result in parity errors to be generated. |
RW | 0x00 0000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x4003 500C | Instance | 0x4003 500C |
| Description | Memory Control Controls memory initialization |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | MEM_BUSY | Memory Busy status 0: Memory accepts transfers 1: Memory controller is busy during initialization. Read and write transfers are not performed. |
RO | 0 | ||
| 0 | MEM_CLR_EN | Memory Contents Initialization enable Writing 1 to MEM_CLR_EN will start memory initialization. The contents of all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until memory initialization has completed. |
RW | 0 | ||
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