Instance: AUX_ANAIF
Component: AUX_ANAIF
Base address: 0x400C9000
AUX Analog Interface (AUX_ANAIF) encapsulates direct data and control interfaces between AUX digital and AUX analog circuits. It lets UDMA0, and system CPU:
-Trigger ADC sample and conversion process.
- Write ADC samples to FIFO.
- Charge analog nodes by the use of the analog ISRC module. See ADI_4_AUX:ISRC and ADI_4_AUX:COMP.COMPA_REF_CURR_EN for further information.
- Use the DAC to generate a programmable voltage on COMPB_REF, COMPA_REF, or COMPA_IN analog nodes.
To use:
- DAC : System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE as long as DAC state machine generates the sample clock. See DACSMPLCTL.EN for further information.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 3F00 |
0x0000 0010 |
0x400C 9010 |
|
RO |
32 |
0x0000 0001 |
0x0000 0014 |
0x400C 9014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 9018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x400C 901C |
|
RW |
32 |
0x0000 0001 |
0x0000 0020 |
0x400C 9020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x400C 9030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x400C 9034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x400C 9038 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x400C 903C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x400C 9040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x400C 9044 |
|
RO |
32 |
0x0000 0000 |
0x0000 0048 |
0x400C 9048 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x400C 9010 | Instance | 0x400C 9010 |
Description | ADC Control Configuration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | ||||||||||||||
14 | START_POL | Select active polarity for START_SRC event.
|
RW | 0 | ||||||||||||||
13:8 | START_SRC | Select ADC trigger event source from the asynchronous AUX event bus. Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b11 1111 | ||||||||||||||
7:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||||||||||||||
1:0 | CMD | ADC interface command. Non-enumerated values are not supported. The written value is returned when read.
|
RW | 0b00 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x400C 9014 | Instance | 0x400C 9014 |
Description | ADC FIFO Status FIFO can hold up to four ADC samples. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
4 | OVERFLOW | FIFO overflow flag. 0: FIFO has not overflowed. 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO write pointer is static. It is not possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. |
RO | 0 | ||
3 | UNDERFLOW | FIFO underflow flag. 0: FIFO has not underflowed. 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO read pointer is static. Read returns the previous sample that was read. Flush FIFO to clear the flag. |
RO | 0 | ||
2 | FULL | FIFO full flag. 0: FIFO is not full, there is less than 4 samples in the FIFO. 1: FIFO is full, there are 4 samples in the FIFO. When the flag is set, it is not possible to add more samples to the ADC FIFO. An attempt to add samples sets the OVERFLOW flag. |
RO | 0 | ||
1 | ALMOST_FULL | FIFO almost full flag. 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL flag is also asserted in the latter case. 1: There are 3 samples in the FIFO, there is room for one more sample. |
RO | 0 | ||
0 | EMPTY | FIFO empty flag. 0: FIFO contains one or more samples. 1: FIFO is empty. When the flag is set, read returns the previous sample that was read and sets the UNDERFLOW flag. |
RO | 1 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C 9018 | Instance | 0x400C 9018 |
Description | ADC FIFO | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | ||
11:0 | DATA | FIFO data. Read: Get oldest ADC sample from FIFO. Write: Write dummy sample to FIFO. This is useful for code development when you do not have real ADC samples. |
RW | 0x000 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x400C 901C | Instance | 0x400C 901C |
Description | ADC Trigger | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | START | Manual ADC trigger. Write any value to START to trigger ADC. To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to avoid conflict with event-driven ADC trigger. |
WO | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x400C 9020 | Instance | 0x400C 9020 |
Description | Current Source Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | RESET_N | ISRC reset control. 0: ISRC drives 0 uA. 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. |
RW | 1 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x400C 9030 | Instance | 0x400C 9030 |
Description | DAC Control This register controls the analog part of the DAC. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
5 | DAC_EN | DAC module enable. 0: Disable DAC. 1: Enable DAC. The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA in Standby TI-RTOS power mode. The System CPU must set AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active and Idle TI-RTOS power modes. |
RW | 0 | |||||||||||||||||
4 | DAC_BUFFER_EN | DAC buffer enable. DAC buffer reduces the time required to produce the programmed voltage at the expense of increased current consumption. 0: Disable DAC buffer. 1: Enable DAC buffer. Enable buffer when DAC_VOUT_SEL equals COMPA_IN. Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP. |
RW | 0 | |||||||||||||||||
3 | DAC_PRECHARGE_EN | DAC precharge enable. Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and VDDS is higher than 2.65 V. DAC output voltage range: 0: 0 V to 1.28 V. 1: 1.28 V to 2.56 V. Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range. Enable precharge 1 us before you enable the DAC and the buffer. |
RW | 0 | |||||||||||||||||
2:0 | DAC_VOUT_SEL | DAC output connection. An analog node must only have one driver. Other drivers for the following analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*].
|
RW | 0b000 |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x400C 9034 | Instance | 0x400C 9034 |
Description | Low Power Mode Bias Control The low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | Module enable. 0: Disable low power mode bias module. 1: Enable low power mode bias module. Set EN to 1 15 us before you enable the DAC or Comparator A. |
RW | 0 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x400C 9038 | Instance | 0x400C 9038 |
Description | DAC Sample Control The DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor. The DAC sample clock waveform consists of a setup phase followed by a hold phase. In the setup phase the sample-and-hold capacitor charges to the programmed voltage. The hold phase maintains the voltage with minimal power. DACSMPLCFG0 and DACSMPLCFG1 configure the DAC sample clock waveform. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | DAC sample clock enable. 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0 when the current sample clock period completes. 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample clock. |
RW | 0 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x400C 903C | Instance | 0x400C 903C |
Description | DAC Sample Configuration 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
5:0 | CLKDIV | Clock division. AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the sample clock base frequency. 0: Divide by 1. 1: Divide by 2. ... 63: Divide by 64. |
RW | 0b00 0000 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x400C 9040 | Instance | 0x400C 9040 |
Description | DAC Sample Configuration 1 The sample clock period equals (high time + low time) * base period. DACSMPLCFG0.CLKDIV determines the base period. Timing requirements (DAC Buffer On / DAC Buffer Off): - (high time + low time) * base period > (4 us / 1 us) - (high time * base period) > (2 us / 0.5 us) - (low time * base period) > (2 us / 0.5 us) - (low time * base period + HOLD_INTERVAL * sample clock period) < 32 us If AUX_SYSIF:OPMODEREQ.REQ equals PDLP, you must set: - H_PER = L_PER = HOLD_INTERVAL = 0. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | ||
14 | H_PER | High time. The sample clock period is high for this many base periods. 0: 2 periods 1: 4 periods |
RW | 0 | ||
13:12 | L_PER | Low time. The sample clock period is low for this many base periods. 0: 1 period 1: 2 periods 2: 3 periods 3: 4 periods |
RW | 0b00 | ||
11:8 | SETUP_CNT | Setup count. Number of active sample clock periods during the setup phase. 0: 1 sample clock period 1: 2 sample clock periods ... 15 : 16 sample clock periods |
RW | 0x0 | ||
7:0 | HOLD_INTERVAL | Hold interval. Number of inactive sample clock periods between each active sample clock period during hold phase. The sample clock is low when inactive. The range is 0 to 255. |
RW | 0x00 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x400C 9044 | Instance | 0x400C 9044 |
Description | DAC Value | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | VALUE | DAC value. Digital data word for the DAC. Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable the DAC. |
RW | 0x00 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x400C 9048 | Instance | 0x400C 9048 |
Description | DAC Status | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | SETUP_ACTIVE | DAC setup phase status. 0: Sample clock is disabled or setup phase is complete. 1: Setup phase in progress. |
RO | 0 | ||
0 | HOLD_ACTIVE | DAC hold phase status. 0: Sample clock is disabled or DAC is not in hold phase. 1: Hold phase in progress. |
RO | 0 |
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