Instance: AUX_SYSIF
Component: AUX_SYSIF
Base address: 0x400C6000
AUX System Interface (AUX_SYSIF) is responsible for:
- system resource requests, such as power supply, clock and, wakeup requests.
- configuration of AUX peripheral operational rates for AUX_SPIM, AUX_MAC, AUX_ANAIF DAC state machine and AUX_TIMER01.
- configuration of event synchronization rate for AUX_EVCTL:EVSTAT2 and AUX_EVCTL:EVSTAT3.
- configuration of AUX_SCE wakeup vectors that trigger AUX_SCE execution from sleep.
Peripheral operational rate for AUX modules mentioned above can either be:
- SCE rate, which is configured in AON_PMCTL:AUXSCECLK.
- AUX bus rate, which equals SCE rate or SCLK_HF divided by two when MCU domain is active or AUX operational mode is active.
AUX_SYSIF also interfaces AON_RTC and AON_BATMON to enable read access to data and sub-second increment control of AON_RTC.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 6000 |
|
RO |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C 6004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C 6008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x400C 600C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 6010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 6014 |
|
WO |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 6018 |
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0x400C 601C |
|
RW |
32 |
0x0000 000F |
0x0000 0020 |
0x400C 6020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x400C 6024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x400C 6028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x400C 602C |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x400C 6030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x400C 6034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x400C 6038 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x400C 603C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x400C 6040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x400C 6044 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x400C 6048 |
|
RW |
32 |
0x0000 0000 |
0x0000 004C |
0x400C 604C |
|
RW |
32 |
0x0000 0000 |
0x0000 0050 |
0x400C 6050 |
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0x400C 6054 |
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0x400C 6058 |
|
RW |
32 |
0x0000 0000 |
0x0000 005C |
0x400C 605C |
|
RO |
32 |
0x0000 0000 |
0x0000 0060 |
0x400C 6060 |
|
RO |
32 |
0x0000 0001 |
0x0000 0064 |
0x400C 6064 |
|
RW |
32 |
0x0000 0000 |
0x0000 0068 |
0x400C 6068 |
|
RW |
32 |
0x0000 0001 |
0x0000 0070 |
0x400C 6070 |
|
RW |
32 |
0x0000 0000 |
0x0000 0074 |
0x400C 6074 |
|
RW |
32 |
0x0000 0000 |
0x0000 0078 |
0x400C 6078 |
|
RW |
32 |
0x0000 0000 |
0x0000 007C |
0x400C 607C |
|
RW |
32 |
0x0000 0000 |
0x0000 0080 |
0x400C 6080 |
|
RW |
32 |
0x0000 0000 |
0x0000 0084 |
0x400C 6084 |
|
RO |
32 |
0x0000 0000 |
0x0000 0088 |
0x400C 6088 |
|
RO |
32 |
0x0000 0000 |
0x0000 008C |
0x400C 608C |
|
RW |
32 |
0x0000 0000 |
0x0000 0090 |
0x400C 6090 |
|
RO |
32 |
0x0000 0000 |
0x0000 0094 |
0x400C 6094 |
|
RO |
32 |
0x0000 0000 |
0x0000 009C |
0x400C 609C |
|
RW |
32 |
0x0000 0000 |
0x0000 00A0 |
0x400C 60A0 |
|
RO |
32 |
0x0000 0000 |
0x0000 00B0 |
0x400C 60B0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00B4 |
0x400C 60B4 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x400C 6000 | Instance | 0x400C 6000 |
Description | Operational Mode Request AUX can operate in three operational modes. Each mode is associated with: - a SCE clock source or rate, given by AON_PMCTL:AUXSCECLK. This rate is termed SCE_RATE. - a system power supply state request. AUX can request powerdown (uLDO) or active (GLDO or DCDC) system power supply state. - a specific system response to an active AUX wakeup flag. The response is dependent on what operational mode is requested. uLDO power supply state offers limited current supply. AUX_SCE cannot use certain peripherals and functions such as AUX_DDI0_OSC, AUX_TDC and AUX_ANAIF ADC interface in this power supply state. Follow these rules: - It is not allowed to change a request until it has been acknowledged through OPMODEACK. - A change in mode request must happen stepwise along this sequence, the direction is irrelevant: PDA - A - LP - PDLP. Failure to follow these rules might result in unexpected behavior and must be avoided. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
1:0 | REQ | AUX operational mode request.
|
RW | 0b00 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x400C 6004 | Instance | 0x400C 6004 |
Description | Operational Mode Acknowledgement AUX_SCE program must assume that the current operational mode is the one acknowledged. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
1:0 | ACK | AUX operational mode acknowledgement.
|
RO | 0b00 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x400C 6008 | Instance | 0x400C 6008 |
Description | Programmable Wakeup 0 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU0 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
7 | POL | Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU0.
|
RW | 0 | |||||||||||
6 | EN | Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag. |
RW | 0 | |||||||||||
5:0 | WU_SRC | Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b00 0000 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x400C 600C | Instance | 0x400C 600C |
Description | Programmable Wakeup 1 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU1 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
7 | POL | Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU1.
|
RW | 0 | |||||||||||
6 | EN | Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag. |
RW | 0 | |||||||||||
5:0 | WU_SRC | Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b00 0000 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x400C 6010 | Instance | 0x400C 6010 |
Description | Programmable Wakeup 2 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU2 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
7 | POL | Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU2.
|
RW | 0 | |||||||||||
6 | EN | Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag. |
RW | 0 | |||||||||||
5:0 | WU_SRC | Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b00 0000 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x400C 6014 | Instance | 0x400C 6014 |
Description | Programmable Wakeup 3 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU3 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
7 | POL | Polarity of WU_SRC. The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU3.
|
RW | 0 | |||||||||||
6 | EN | Programmable wakeup flag enable. 0: Disable wakeup flag. 1: Enable wakeup flag. |
RW | 0 | |||||||||||
5:0 | WU_SRC | Wakeup source from the asynchronous AUX event bus. Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b00 0000 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C 6018 | Instance | 0x400C 6018 |
Description | Software Wakeup Triggers System CPU uses these wakeup flags to perform handshaking with AUX_SCE. The wakeup flags can change the operational mode of AUX and guarantees a non-zero SCE clock rate. AUX_SCE wakeup vectors are configured in VECCFGn. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0x000 0000 | ||
3 | SW_WU3 | Software wakeup 3 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup. |
WO | 0 | ||
2 | SW_WU2 | Software wakeup 2 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup. |
WO | 0 | ||
1 | SW_WU1 | Software wakeup 1 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup. |
WO | 0 | ||
0 | SW_WU0 | Software wakeup 0 trigger. 0: No effect. 1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup. |
WO | 0 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x400C 601C | Instance | 0x400C 601C |
Description | Wakeup Flags This register holds the eight AUX wakeup flags. Each flag can cause AUX operational mode to change as given in OPMODEREQ. To clear flag n you must set bit n in WUFLAGSCLR until flag n is read as 0. You must clear bit n in WUFLAGSCLR before flag n can be set again. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7 | SW_WU3 | Software wakeup 3 flag. 0: Software wakeup 3 not triggered. 1: Software wakeup 3 triggered. |
RO | 0 | ||
6 | SW_WU2 | Software wakeup 2 flag. 0: Software wakeup 2 not triggered. 1: Software wakeup 2 triggered. |
RO | 0 | ||
5 | SW_WU1 | Software wakeup 1 flag. 0: Software wakeup 1 not triggered. 1: Software wakeup 1 triggered. |
RO | 0 | ||
4 | SW_WU0 | Software wakeup 0 flag. 0: Software wakeup 0 not triggered. 1: Software wakeup 0 triggered. |
RO | 0 | ||
3 | PROG_WU3 | Programmable wakeup 3. 0: Programmable wakeup 3 not triggered. 1: Programmable wakeup 3 triggered. |
RO | 0 | ||
2 | PROG_WU2 | Programmable wakeup 2. 0: Programmable wakeup 2 not triggered. 1: Programmable wakeup 2 triggered. |
RO | 0 | ||
1 | PROG_WU1 | Programmable wakeup 1. 0: Programmable wakeup 1 not triggered. 1: Programmable wakeup 1 triggered. |
RO | 0 | ||
0 | PROG_WU0 | Programmable wakeup 0. 0: Programmable wakeup 0 not triggered. 1: Programmable wakeup 0 triggered. |
RO | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x400C 6020 | Instance | 0x400C 6020 |
Description | Wakeup Flags Clear This register clears AUX wakeup flags WUFLAGS. To clear programmable wakeup flags you must disable the AUX wakeup output first. After the programmable wakeup flags are cleared you must re-enable the AUX wakeup output. Write WUGATE to disable or enable the AUX wakeup output. This procedure is not required when you want to clear a software-triggered wakeup. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7 | SW_WU3 | Clear software wakeup flag 3. 0: No effect. 1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0. |
RW | 0 | ||
6 | SW_WU2 | Clear software wakeup flag 2. 0: No effect. 1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0. |
RW | 0 | ||
5 | SW_WU1 | Clear software wakeup flag 1. 0: No effect. 1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0. |
RW | 0 | ||
4 | SW_WU0 | Clear software wakeup flag 0. 0: No effect. 1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0. |
RW | 0 | ||
3 | PROG_WU3 | Programmable wakeup flag 3. 0: No effect. 1: Clear WUFLAGS.PROG_WU3. Keep high until WUFLAGS.PROG_WU3 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU3 to 0 when PROGWU3CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN. |
RW | 1 | ||
2 | PROG_WU2 | Programmable wakeup flag 2. 0: No effect. 1: Clear WUFLAGS.PROG_WU2. Keep high until WUFLAGS.PROG_WU2 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU2 to 0 when PROGWU2CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN. |
RW | 1 | ||
1 | PROG_WU1 | Programmable wakeup flag 1. 0: No effect. 1: Clear WUFLAGS.PROG_WU1. Keep high until WUFLAGS.PROG_WU1 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU1 to 0 when PROGWU1CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN. |
RW | 1 | ||
0 | PROG_WU0 | Programmable wakeup flag 0. 0: No effect. 1: Clear WUFLAGS.PROG_WU0. Keep high until WUFLAGS.PROG_WU0 is 0. The wakeup flag becomes edge sensitive if you write PROG_WU0 to 0 when PROGWU0CFG.EN is 1. The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN. |
RW | 1 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x400C 6024 | Instance | 0x400C 6024 |
Description | Wakeup Gate You must disable the AUX wakeup output: - Before you clear a programmable wakeup flag. - Before you change the value of PROGWUnCFG.EN or PROGWUnCFG.WU_SRC. The AUX wakeup output must be re-enabled after clear operation or programmable wakeup configuration. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | Wakeup output enable. 0: Disable AUX wakeup output. 1: Enable AUX wakeup output. |
RW | 0 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x400C 6028 | Instance | 0x400C 6028 |
Description | Vector Configuration 0 AUX_SCE wakeup vector 0 configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||
3:0 | VEC_EV | Select trigger event for vector 0. Non-enumerated values are treated as NONE.
|
RW | 0x0 |
Address Offset | 0x0000 002C | ||
Physical Address | 0x400C 602C | Instance | 0x400C 602C |
Description | Vector Configuration 1 AUX_SCE wakeup vector 1 configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||
3:0 | VEC_EV | Select trigger event for vector 1. Non-enumerated values are treated as NONE.
|
RW | 0x0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x400C 6030 | Instance | 0x400C 6030 |
Description | Vector Configuration 2 AUX_SCE wakeup vector 2 configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||
3:0 | VEC_EV | Select trigger event for vector 2. Non-enumerated values are treated as NONE.
|
RW | 0x0 |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x400C 6034 | Instance | 0x400C 6034 |
Description | Vector Configuration 3 AUX_SCE wakeup vector 3 configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||
3:0 | VEC_EV | Select trigger event for vector 3. Non-enumerated values are treated as NONE.
|
RW | 0x0 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x400C 6038 | Instance | 0x400C 6038 |
Description | Vector Configuration 4 AUX_SCE wakeup vector 4 configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||
3:0 | VEC_EV | Select trigger event for vector 4. Non-enumerated values are treated as NONE.
|
RW | 0x0 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x400C 603C | Instance | 0x400C 603C |
Description | Vector Configuration 5 AUX_SCE wakeup vector 5 configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||
3:0 | VEC_EV | Select trigger event for vector 5. Non-enumerated values are treated as NONE.
|
RW | 0x0 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x400C 6040 | Instance | 0x400C 6040 |
Description | Vector Configuration 6 AUX_SCE wakeup vector 6 configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||
3:0 | VEC_EV | Select trigger event for vector 6. Non-enumerated values are treated as NONE.
|
RW | 0x0 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x400C 6044 | Instance | 0x400C 6044 |
Description | Vector Configuration 7 AUX_SCE wakeup vector 7 configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||
3:0 | VEC_EV | Select trigger event for vector 7. Non-enumerated values are treated as NONE.
|
RW | 0x0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x400C 6048 | Instance | 0x400C 6048 |
Description | Event Synchronization Rate Configure synchronization rate for certain events to the synchronous AUX event bus. You must select SCE rate when AUX_SCE uses the event. You must select AUX bus rate when system CPU uses the event. SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by two when MCU domain is active. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | AUX_COMPA_SYNC_RATE | Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event.
|
RW | 0 | |||||||||||
1 | AUX_COMPB_SYNC_RATE | Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event.
|
RW | 0 | |||||||||||
0 | AUX_TIMER2_SYNC_RATE | Select synchronization rate for: - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 - AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
|
RW | 0 |
Address Offset | 0x0000 004C | ||
Physical Address | 0x400C 604C | Instance | 0x400C 604C |
Description | Peripheral Operational Rate Some AUX peripherals are operated at either SCE or at AUX bus rate. You must select SCE rate when AUX_SCE uses such peripheral or an event produced by it. You must select AUX bus rate when system CPU uses such peripheral. SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by 2 when MCU domain is active. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | ANAIF_DAC_OP_RATE | Select operational rate for AUX_ANAIF DAC sample clock state machine.
|
RW | 0 | |||||||||||
2 | TIMER01_OP_RATE | Select operational rate for AUX_TIMER01.
|
RW | 0 | |||||||||||
1 | SPIM_OP_RATE | Select operational rate for AUX_SPIM.
|
RW | 0 | |||||||||||
0 | MAC_OP_RATE | Select operational rate for AUX_MAC.
|
RW | 0 |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x400C 6050 | Instance | 0x400C 6050 |
Description | ADC Clock Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | ACK | Clock acknowledgement. 0: ADC clock is disabled. 1: ADC clock is enabled. |
RO | 0 | ||
0 | REQ | ADC clock request. 0: Disable ADC clock. 1: Enable ADC clock. Only modify REQ when equal to ACK. |
RW | 0 |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x400C 6054 | Instance | 0x400C 6054 |
Description | TDC Counter Clock Control Controls if the AUX_TDC counter clock source is enabled. TDC counter clock source is configured in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | ACK | TDC counter clock acknowledgement. 0: TDC counter clock is disabled. 1: TDC counter clock is enabled. |
RO | 0 | ||
0 | REQ | TDC counter clock request. 0: Disable TDC counter clock. 1: Enable TDC counter clock. Only modify REQ when equal to ACK. |
RW | 0 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x400C 6058 | Instance | 0x400C 6058 |
Description | TDC Reference Clock Control Controls if the AUX_TDC reference clock source is enabled. This clock is compared against the AUX_TDC counter clock. TDC reference clock source is configured in DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | ACK | TDC reference clock acknowledgement. 0: TDC reference clock is disabled. 1: TDC reference clock is enabled. |
RO | 0 | ||
0 | REQ | TDC reference clock request. 0: Disable TDC reference clock. 1: Enable TDC reference clock. Only modify REQ when equal to ACK. |
RW | 0 |
Address Offset | 0x0000 005C | ||
Physical Address | 0x400C 605C | Instance | 0x400C 605C |
Description | AUX_TIMER2 Clock Control Access to AUX_TIMER2 is only possible when TIMER2CLKSTAT.STAT is different from NONE. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
2:0 | SRC | Select clock source for AUX_TIMER2. Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or TIMER2CLKSWITCH.RDY is 1. It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0. A non-enumerated value is ignored.
|
RW | 0b000 |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x400C 6060 | Instance | 0x400C 6060 |
Description | AUX_TIMER2 Clock Status | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
2:0 | STAT | AUX_TIMER2 clock source status.
|
RO | 0b000 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x400C 6064 | Instance | 0x400C 6064 |
Description | AUX_TIMER2 Clock Switch | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | RDY | Status of clock switcher. 0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT. 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT. RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY. |
RO | 1 |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x400C 6068 | Instance | 0x400C 6068 |
Description | AUX_TIMER2 Debug Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | DBG_FREEZE_EN | Debug freeze enable. 0: AUX_TIMER2 does not halt when the system CPU halts in debug mode. 1: Halt AUX_TIMER2 when the system CPU halts in debug mode. |
RW | 0 |
Address Offset | 0x0000 0070 | ||
Physical Address | 0x400C 6070 | Instance | 0x400C 6070 |
Description | Clock Shift Detection A transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF: - A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when MCU domain enters active state. - A single SCE clock cycle is 6 thru 8 SCLK_HF cycles shorter when MCU domain exits active state. AUX_SCE detects if such events occurred to the SCE clock during the time period between a clear of STAT and a read of STAT. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | STAT | Clock shift detection. Write: 0: Restart clock shift detection. 1: Do not use. Read: 0: MCU domain did not enter or exit active state since you wrote 0 to STAT. 1: MCU domain entered or exited active state since you wrote 0 to STAT. |
RW | 1 |
Address Offset | 0x0000 0074 | ||
Physical Address | 0x400C 6074 | Instance | 0x400C 6074 |
Description | VDDR Recharge Trigger | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | TRIG | Recharge trigger. 0: No effect. 1: Request VDDR recharge. Request VDDR recharge only when AUX_EVCTL:EVSTAT2.PWR_DWN is 1. Follow this sequence when OPMODEREQ.REQ is LP: - Set TRIG. - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 1. - Clear TRIG. - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 0. Follow this sequence when OPMODEREQ.REQ is PDA or PDLP: - Set TRIG. - Clear TRIG. |
RW | 0 |
Address Offset | 0x0000 0078 | ||
Physical Address | 0x400C 6078 | Instance | 0x400C 6078 |
Description | VDDR Recharge Detection Some applications can be sensitive to power noise caused by recharge of VDDR. You can detect if VDDR recharge occurs. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | STAT | VDDR recharge detector status. 0: No recharge of VDDR has occurred since EN was set. 1: Recharge of VDDR has occurred since EN was set. |
RO | 0 | ||
0 | EN | VDDR recharge detector enable. 0: Disable recharge detection. STAT becomes zero. 1: Enable recharge detection. |
RW | 0 |
Address Offset | 0x0000 007C | ||
Physical Address | 0x400C 607C | Instance | 0x400C 607C |
Description | Real Time Counter Sub Second Increment 0 INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | INC15_0 | New value for bits 15:0 in AON_RTC:SUBSECINC. | RW | 0x0000 |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x400C 6080 | Instance | 0x400C 6080 |
Description | Real Time Counter Sub Second Increment 1 INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | INC23_16 | New value for bits 23:16 in AON_RTC:SUBSECINC. | RW | 0x00 |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x400C 6084 | Instance | 0x400C 6084 |
Description | Real Time Counter Sub Second Increment Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | UPD_ACK | Update acknowledgement. 0: AON_RTC has not acknowledged UPD_REQ. 1: AON_RTC has acknowledged UPD_REQ. |
RO | 0 | ||
0 | UPD_REQ | Request AON_RTC to update AON_RTC:SUBSECINC. 0: Clear request to update. 1: Set request to update. Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is 1. |
RW | 0 |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x400C 6088 | Instance | 0x400C 6088 |
Description | Real Time Counter Second System CPU must not access this register. Instead, system CPU must access AON_RTC:SEC.VALUE directly. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | SEC | Bits 15:0 in AON_RTC:SEC.VALUE. Follow this procedure to get the correct value: - Do two dummy reads of SEC. - Then read SEC until two consecutive reads are equal. |
RO | 0x0000 |
Address Offset | 0x0000 008C | ||
Physical Address | 0x400C 608C | Instance | 0x400C 608C |
Description | Real Time Counter Sub-Second System CPU must not access this register. Instead, system CPU must access AON_RTC:SUBSEC.VALUE directly. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | SUBSEC | Bits 31:16 in AON_RTC:SUBSEC.VALUE. Follow this procedure to get the correct value: - Do two dummy reads SUBSEC. - Then read SUBSEC until two consecutive reads are equal. |
RO | 0x0000 |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x400C 6090 | Instance | 0x400C 6090 |
Description | AON_RTC Event Clear Request to clear events: - AON_RTC:EVFLAGS.CH2. - AON_RTC:EVFLAGS.CH2 delayed version. - AUX_EVCTL:EVSTAT2.AON_RTC_CH2. - AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | RTC_CH2_EV_CLR | Clear events from AON_RTC channel 2. 0: No effect. 1: Clear events from AON_RTC channel 2. Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0. |
RW | 0 |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x400C 6094 | Instance | 0x400C 6094 |
Description | AON_BATMON Battery Voltage Value Read access to AON_BATMON:BAT. System CPU must not access this register. Instead, system CPU must access AON_BATMON:BAT directly. AON_BATMON:BAT updates during VDDR recharge or active operational mode. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | ||
10:8 | INT | See AON_BATMON:BAT.INT. Follow this procedure to get the correct value: - Do two dummy reads of INT. - Then read INT until two consecutive reads are equal. |
RO | 0b000 | ||
7:0 | FRAC | See AON_BATMON:BAT.FRAC. Follow this procedure to get the correct value: - Do two dummy reads of FRAC. - Then read FRAC until two consecutive reads are equal. |
RO | 0x00 |
Address Offset | 0x0000 009C | ||
Physical Address | 0x400C 609C | Instance | 0x400C 609C |
Description | AON_BATMON Temperature Value Read access to AON_BATMON:TEMP. System CPU must not access this register. Instead, system CPU must access AON_BATMON:TEMP directly. AON_BATMON:TEMP updates during VDDR recharge or active operational mode. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:11 | SIGN | Sign extension of INT. Follow this procedure to get the correct value: - Do two dummy reads of SIGN. - Then read SIGN until two consecutive reads are equal. |
RO | 0b0 0000 | ||
10:2 | INT | See AON_BATMON:TEMP.INT. Follow this procedure to get the correct value: - Do two dummy reads of INT. - Then read INT until two consecutive reads are equal. |
RO | 0b0 0000 0000 | ||
1:0 | FRAC | See AON_BATMON:TEMP.FRAC. Follow this procedure to get the correct value: - Do two dummy reads of FRAC. - Then read FRAC until two consecutive reads are equal. |
RO | 0b00 |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x400C 60A0 | Instance | 0x400C 60A0 |
Description | Timer Halt Debug register |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
3 | PROGDLY | Halt programmable delay. 0: AUX_EVCTL:PROGDLY.VALUE decrements as normal. 1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation. |
RW | 0 | ||
2 | AUX_TIMER2 | Halt AUX_TIMER2. 0: AUX_TIMER2 operates as normal. 1: Halt AUX_TIMER2 operation. |
RW | 0 | ||
1 | AUX_TIMER1 | Halt AUX_TIMER01 Timer 1. 0: AUX_TIMER01 Timer 1 operates as normal. 1: Halt AUX_TIMER01 Timer 1 operation. |
RW | 0 | ||
0 | AUX_TIMER0 | Halt AUX_TIMER01 Timer 0. 0: AUX_TIMER01 Timer 0 operates as normal. 1: Halt AUX_TIMER01 Timer 0 operation. |
RW | 0 |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x400C 60B0 | Instance | 0x400C 60B0 |
Description | AUX_TIMER2 Bridge | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | BUSY | Status of bus transactions to AUX_TIMER2. 0: No unfinished bus transactions. 1: A bus transaction is ongoing. |
RO | 0 |
Address Offset | 0x0000 00B4 | ||
Physical Address | 0x400C 60B4 | Instance | 0x400C 60B4 |
Description | Software Power Profiler | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
2:0 | STAT | Software status bits that can be read by the power profiler. | RW | 0b000 |
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