Instance: GPT1
Component: GPT
Base address: 0x40011000
General Purpose Timer.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4001 1000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4001 1004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4001 1008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4001 100C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x4001 1010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4001 1018 |
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0x4001 101C |
|
RO |
32 |
0x0000 0000 |
0x0000 0020 |
0x4001 1020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4001 1024 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0028 |
0x4001 1028 |
|
RW |
32 |
0x0000 FFFF |
0x0000 002C |
0x4001 102C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0030 |
0x4001 1030 |
|
RW |
32 |
0x0000 FFFF |
0x0000 0034 |
0x4001 1034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4001 1038 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x4001 103C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x4001 1040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4001 1044 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0048 |
0x4001 1048 |
|
RO |
32 |
0x0000 FFFF |
0x0000 004C |
0x4001 104C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0050 |
0x4001 1050 |
|
RW |
32 |
0x0000 FFFF |
0x0000 0054 |
0x4001 1054 |
|
RO |
32 |
0x0000 0000 |
0x0000 005C |
0x4001 105C |
|
RO |
32 |
0x0000 0000 |
0x0000 0060 |
0x4001 1060 |
|
RO |
32 |
0x0000 0000 |
0x0000 0064 |
0x4001 1064 |
|
RO |
32 |
0x0000 0000 |
0x0000 0068 |
0x4001 1068 |
|
RW |
32 |
0x0000 0000 |
0x0000 006C |
0x4001 106C |
|
RO |
32 |
0x0000 0400 |
0x0000 0FB0 |
0x4001 1FB0 |
|
RW |
32 |
0x0000 0000 |
0x0000 0FB4 |
0x4001 1FB4 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4001 1000 | Instance | 0x4001 1000 |
Description | Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2:0 | CFG | GPT Configuration 0x2- 0x3 - Reserved 0x5- 0x7 - Reserved
|
RW | 0b000 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4001 1004 | Instance | 0x4001 1004 |
Description | Timer A Mode | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||||||||||||||||||||
15:13 | TCACT | Timer Compare Action Select
|
RW | 0b000 | |||||||||||||||||||||||||||||
12 | TACINTD | One-Shot/Periodic Interrupt Disable
|
RW | 0 | |||||||||||||||||||||||||||||
11 | TAPLO | GPTM Timer A PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode.
|
RW | 0 | |||||||||||||||||||||||||||||
10 | TAMRSU | Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit.
|
RW | 0 | |||||||||||||||||||||||||||||
9 | TAPWMIE | GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode.
|
RW | 0 | |||||||||||||||||||||||||||||
8 | TAILD | GPT Timer A PWM Interval Load Write
|
RW | 0 | |||||||||||||||||||||||||||||
7 | TASNAPS | GPT Timer A Snap-Shot Mode
|
RW | 0 | |||||||||||||||||||||||||||||
6 | TAWOT | GPT Timer A Wait-On-Trigger
|
RW | 0 | |||||||||||||||||||||||||||||
5 | TAMIE | GPT Timer A Match Interrupt Enable
|
RW | 0 | |||||||||||||||||||||||||||||
4 | TACDIR | GPT Timer A Count Direction
|
RW | 0 | |||||||||||||||||||||||||||||
3 | TAAMS | GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2.
|
RW | 0 | |||||||||||||||||||||||||||||
2 | TACM | GPT Timer A Capture Mode
|
RW | 0 | |||||||||||||||||||||||||||||
1:0 | TAMR | GPT Timer A Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register
|
RW | 0b00 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4001 1008 | Instance | 0x4001 1008 |
Description | Timer B Mode | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||||||||||||||||||||
15:13 | TCACT | Timer Compare Action Select
|
RW | 0b000 | |||||||||||||||||||||||||||||
12 | TBCINTD | One-Shot/Periodic Interrupt Mode
|
RW | 0 | |||||||||||||||||||||||||||||
11 | TBPLO | GPTM Timer B PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode.
|
RW | 0 | |||||||||||||||||||||||||||||
10 | TBMRSU | Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updated If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit.
|
RW | 0 | |||||||||||||||||||||||||||||
9 | TBPWMIE | GPTM Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TBEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode.
|
RW | 0 | |||||||||||||||||||||||||||||
8 | TBILD | GPT Timer B PWM Interval Load Write
|
RW | 0 | |||||||||||||||||||||||||||||
7 | TBSNAPS | GPT Timer B Snap-Shot Mode
|
RW | 0 | |||||||||||||||||||||||||||||
6 | TBWOT | GPT Timer B Wait-On-Trigger
|
RW | 0 | |||||||||||||||||||||||||||||
5 | TBMIE | GPT Timer B Match Interrupt Enable.
|
RW | 0 | |||||||||||||||||||||||||||||
4 | TBCDIR | GPT Timer B Count Direction
|
RW | 0 | |||||||||||||||||||||||||||||
3 | TBAMS | GPT Timer B Alternate Mode Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2.
|
RW | 0 | |||||||||||||||||||||||||||||
2 | TBCM | GPT Timer B Capture Mode
|
RW | 0 | |||||||||||||||||||||||||||||
1:0 | TBMR | GPT Timer B Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register
|
RW | 0b00 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4001 100C | Instance | 0x4001 100C |
Description | Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | ||||||||||||||
14 | TBPWML | GPT Timer B PWM Output Level 0: Output is unaffected. 1: Output is inverted.
|
RW | 0 | ||||||||||||||
13:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 | ||||||||||||||
11:10 | TBEVENT | GPT Timer B Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal.
|
RW | 0b00 | ||||||||||||||
9 | TBSTALL | GPT Timer B Stall Enable
|
RW | 0 | ||||||||||||||
8 | TBEN | GPT Timer B Enable
|
RW | 0 | ||||||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||
6 | TAPWML | GPT Timer A PWM Output Level
|
RW | 0 | ||||||||||||||
5:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 | ||||||||||||||
3:2 | TAEVENT | GPT Timer A Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal.
|
RW | 0b00 | ||||||||||||||
1 | TASTALL | GPT Timer A Stall Enable
|
RW | 0 | ||||||||||||||
0 | TAEN | GPT Timer A Enable
|
RW | 0 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4001 1010 | Instance | 0x4001 1010 |
Description | Synch Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||||||||
7:6 | SYNC3 | Synchronize GPT Timer 3.
|
WO | 0b00 | |||||||||||||||||
5:4 | SYNC2 | Synchronize GPT Timer 2.
|
WO | 0b00 | |||||||||||||||||
3:2 | SYNC1 | Synchronize GPT Timer 1
|
WO | 0b00 | |||||||||||||||||
1:0 | SYNC0 | Synchronize GPT Timer 0
|
WO | 0b00 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4001 1018 | Instance | 0x4001 1018 |
Description | Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | |||||||||||
13 | DMABIM | Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS
|
RW | 0 | |||||||||||
12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
11 | TBMIM | Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS
|
RW | 0 | |||||||||||
10 | CBEIM | Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS
|
RW | 0 | |||||||||||
9 | CBMIM | Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS
|
RW | 0 | |||||||||||
8 | TBTOIM | Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS
|
RW | 0 | |||||||||||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
5 | DMAAIM | Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS
|
RW | 0 | |||||||||||
4 | TAMIM | Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS
|
RW | 0 | |||||||||||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | |||||||||||
2 | CAEIM | Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS
|
RW | 0 | |||||||||||
1 | CAMIM | Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS
|
RW | 0 | |||||||||||
0 | TATOIM | Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS
|
RW | 0 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4001 101C | Instance | 0x4001 101C |
Description | Raw Interrupt Status Associated registers: IMR, MIS, ICLR |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | ||
13 | DMABRIS | GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed |
RO | 0 | ||
12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
11 | TBMRIS | GPT Timer B Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode. |
RO | 0 | ||
10 | CBERIS | GPT Timer B Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode |
RO | 0 | ||
9 | CBMRIS | GPT Timer B Capture Mode Match Raw Interrupt 0: The capture mode match for Timer B has not occurred. 1: A capture mode match has occurred for Timer B. This interrupt asserts when the values in the TBR and TBPR match the values in the TBMATCHR and TBPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. |
RO | 0 | ||
8 | TBTORIS | GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1: Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction. |
RO | 0 | ||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
5 | DMAARIS | GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed |
RO | 0 | ||
4 | TAMRIS | GPT Timer A Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode. |
RO | 0 | ||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
2 | CAERIS | GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode |
RO | 0 | ||
1 | CAMRIS | GPT Timer A Capture Mode Match Raw Interrupt 0: The capture mode match for Timer A has not occurred. 1: A capture mode match has occurred for Timer A. This interrupt asserts when the values in the TAR and TAPR match the values in the TAMATCHR and TAPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. |
RO | 0 | ||
0 | TATORIS | GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1: Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction. |
RO | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4001 1020 | Instance | 0x4001 1020 |
Description | Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | ||
13 | DMABMIS | 0: No interrupt or interrupt not enabled 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 |
RO | 0 | ||
12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
11 | TBMMIS | 0: No interrupt or interrupt not enabled 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 |
RO | 0 | ||
10 | CBEMIS | 0: No interrupt or interrupt not enabled 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 |
RO | 0 | ||
9 | CBMMIS | 0: No interrupt or interrupt not enabled 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 |
RO | 0 | ||
8 | TBTOMIS | 0: No interrupt or interrupt not enabled 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 |
RO | 0 | ||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
5 | DMAAMIS | 0: No interrupt or interrupt not enabled 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 |
RO | 0 | ||
4 | TAMMIS | 0: No interrupt or interrupt not enabled 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 |
RO | 0 | ||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
2 | CAEMIS | 0: No interrupt or interrupt not enabled 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 |
RO | 0 | ||
1 | CAMMIS | 0: No interrupt or interrupt not enabled 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 |
RO | 0 | ||
0 | TATOMIS | 0: No interrupt or interrupt not enabled 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 |
RO | 0 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4001 1024 | Instance | 0x4001 1024 |
Description | Interrupt Clear This register is used to clear status bits in the RIS and MIS registers |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | ||
13 | DMABINT | 0: Do nothing. 1: Clear RIS.DMABRIS and MIS.DMABMIS |
RW | 0 | ||
12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
11 | TBMCINT | 0: Do nothing. 1: Clear RIS.TBMRIS and MIS.TBMMIS |
RW | 0 | ||
10 | CBECINT | 0: Do nothing. 1: Clear RIS.CBERIS and MIS.CBEMIS |
RW | 0 | ||
9 | CBMCINT | 0: Do nothing. 1: Clear RIS.CBMRIS and MIS.CBMMIS |
RW | 0 | ||
8 | TBTOCINT | 0: Do nothing. 1: Clear RIS.TBTORIS and MIS.TBTOMIS |
RW | 0 | ||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
5 | DMAAINT | 0: Do nothing. 1: Clear RIS.DMAARIS and MIS.DMAAMIS |
RW | 0 | ||
4 | TAMCINT | 0: Do nothing. 1: Clear RIS.TAMRIS and MIS.TAMMIS |
RW | 0 | ||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
2 | CAECINT | 0: Do nothing. 1: Clear RIS.CAERIS and MIS.CAEMIS |
RW | 0 | ||
1 | CAMCINT | 0: Do nothing. 1: Clear RIS.CAMRIS and MIS.CAMMIS |
RW | 0 | ||
0 | TATOCINT | 0: Do nothing. 1: Clear RIS.TATORIS and MIS.TATOMIS |
RW | 0 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4001 1028 | Instance | 0x4001 1028 |
Description | Timer A Interval Load Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TAILR | GPT Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of TAILR. |
RW | 0xFFFF FFFF |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4001 102C | Instance | 0x4001 102C |
Description | Timer B Interval Load Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TBILR | GPT Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of TBILR. |
RW | 0x0000 FFFF |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4001 1030 | Instance | 0x4001 1030 |
Description | Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and this register. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TAMATCHR | GPT Timer A Match Register | RW | 0xFFFF FFFF |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4001 1034 | Instance | 0x4001 1034 |
Description | Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | TBMATCHR | GPT Timer B Match Register | RW | 0xFFFF |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4001 1038 | Instance | 0x4001 1038 |
Description | Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | TAPSR | Timer A Pre-scale. Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 |
RW | 0x00 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4001 103C | Instance | 0x4001 103C |
Description | Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | TBPSR | Timer B Pre-scale. Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 |
RW | 0x00 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4001 1040 | Instance | 0x4001 1040 |
Description | Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | TAPSMR | GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. | RW | 0x00 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4001 1044 | Instance | 0x4001 1044 |
Description | Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | TBPSMR | GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16. | RW | 0x00 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4001 1048 | Instance | 0x4001 1048 |
Description | Timer A Register This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPT is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the Timer B (TBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TAV register. To read the value of the prescalar in periodic snapshot mode, read the Timer A Prescale Snapshot (TAPS) register. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TAR | GPT Timer A Register Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4001 104C | Instance | 0x4001 104C |
Description | Timer B Register This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TBV register. To read the value of the prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (TBPS) register. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TBR | GPT Timer B Register Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. |
RO | 0x0000 FFFF |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4001 1050 | Instance | 0x4001 1050 |
Description | Timer A Value When read, this register shows the current, free-running value of Timer A in all modes. Softwarecan use this value to determine the time elapsed between an interrupt and the ISR entry when using the snapshot feature with the periodic operating mode. When written, the value written into this register is loaded into the TAR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (TBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TAV | GPT Timer A Register A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the TAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect |
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4001 1054 | Instance | 0x4001 1054 |
Description | Timer B Value When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the TBR register on the next clock cycle. When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the TAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TBV | GPT Timer B Register A read returns the current, free-running value of Timer B in all modes. When written, the value written into this register is loaded into the TBR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect |
RW | 0x0000 FFFF |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4001 105C | Instance | 0x4001 105C |
Description | Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | PSS | GPT Timer A Pre-scaler | RO | 0x00 |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4001 1060 | Instance | 0x4001 1060 |
Description | Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | PSS | GPT Timer B Pre-scaler | RO | 0x00 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4001 1064 | Instance | 0x4001 1064 |
Description | Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | PSV | GPT Timer A Pre-scaler Value | RO | 0x00 |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4001 1068 | Instance | 0x4001 1068 |
Description | Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | PSV | GPT Timer B Pre-scaler Value | RO | 0x00 |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4001 106C | Instance | 0x4001 106C |
Description | DMA Event This register allows software to enable/disable GPT DMA trigger events. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:12 | RESERVED12 | Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. | RO | 0x0 0000 | ||
11 | TBMDMAEN | GPT Timer B Match DMA Trigger Enable | RW | 0 | ||
10 | CBEDMAEN | GPT Timer B Capture Event DMA Trigger Enable | RW | 0 | ||
9 | CBMDMAEN | GPT Timer B Capture Match DMA Trigger Enable | RW | 0 | ||
8 | TBTODMAEN | GPT Timer B Time-Out DMA Trigger Enable | RW | 0 | ||
7:5 | RESERVED5 | Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. | RW | 0b000 | ||
4 | TAMDMAEN | GPT Timer A Match DMA Trigger Enable | RW | 0 | ||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
2 | CAEDMAEN | GPT Timer A Capture Event DMA Trigger Enable | RW | 0 | ||
1 | CAMDMAEN | GPT Timer A Capture Match DMA Trigger Enable | RW | 0 | ||
0 | TATODMAEN | GPT Timer A Time-Out DMA Trigger Enable | RW | 0 |
Address Offset | 0x0000 0FB0 | ||
Physical Address | 0x4001 1FB0 | Instance | 0x4001 1FB0 |
Description | Peripheral Version This register provides information regarding the GPT version |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VERSION | Timer Revision. | RO | 0x0000 0400 |
Address Offset | 0x0000 0FB4 | ||
Physical Address | 0x4001 1FB4 | Instance | 0x4001 1FB4 |
Description | Combined CCP Output This register is used to logically AND CCP output pairs for each timer |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | LD_TO_EN | PWM assertion would happen at timeout 0: PWM assertion happens when counter matches load value 1: PWM assertion happens at timeout of the counter |
RW | 0 | ||
0 | CCP_AND_EN | Enables AND operation of the CCP outputs for timers A and B. 0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers. 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals and Timer B PWM ouput is Timer B PWM signal only. |
RW | 0 |
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