Instance: WDT
Component: WDT
Base address: 0x40080000
Watchdog Timer
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0xFFFF FFFF |
0x0000 0000 |
0x4008 0000 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0004 |
0x4008 0004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4008 0008 |
|
WO |
32 |
0x0000 0000 |
0x0000 000C |
0x4008 000C |
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x4008 0010 |
|
RO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4008 0014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0418 |
0x4008 0418 |
|
RO |
32 |
0x0000 0000 |
0x0000 041C |
0x4008 041C |
|
RW |
32 |
0x0000 0000 |
0x0000 0C00 |
0x4008 0C00 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4008 0000 | Instance | 0x4008 0000 |
Description | Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | WDTLOAD | This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter is restarted to count down from the new value. If this register is loaded with 0x0000.0000, an interrupt is immediately generated. | RW | 0xFFFF FFFF |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4008 0004 | Instance | 0x4008 0004 |
Description | Current Count Value | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | WDTVALUE | This register contains the current count value of the timer. | RO | 0xFFFF FFFF |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4008 0008 | Instance | 0x4008 0008 |
Description | Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | INTTYPE | WDT Interrupt Type 0: WDT interrupt is a standard interrupt. 1: WDT interrupt is a non-maskable interrupt.
|
RW | 0 | |||||||||||
1 | RESEN | WDT Reset Enable. Defines the function of the WDT reset source (see PRCM:WARMRESET.WDT_STAT if enabled) 0: Disabled. 1: Enable the Watchdog reset output.
|
RW | 0 | |||||||||||
0 | INTEN | WDT Interrupt Enable 0: Interrupt event disabled. 1: Interrupt event enabled. Once set, this bit can only be cleared by a hardware reset.
|
RW | 0 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4008 000C | Instance | 0x4008 000C |
Description | Interrupt Clear | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | WDTICR | This register is the interrupt clear register. A write of any value to this register clears the WDT interrupt and reloads the 32-bit counter from the LOAD register. | WO | 0x0000 0000 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4008 0010 | Instance | 0x4008 0010 |
Description | Raw Interrupt Status | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | WDTRIS | This register is the raw interrupt status register. WDT interrupt events can be monitored via this register if the controller interrupt is masked. Value Description 0: The WDT has not timed out 1: A WDT time-out event has occurred |
RO | 0 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4008 0014 | Instance | 0x4008 0014 |
Description | Masked Interrupt Status | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | WDTMIS | This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the WDT interrupt enable bit CTL.INTEN. Value Description 0: The WDT has not timed out or is masked. 1: An unmasked WDT time-out event has occurred. |
RO | 0 |
Address Offset | 0x0000 0418 | ||
Physical Address | 0x4008 0418 | Instance | 0x4008 0418 |
Description | Test Mode | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | STALL | WDT Stall Enable 0: The WDT timer continues counting if the CPU is stopped with a debugger. 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the CPU is restarted, the WDT resumes counting.
|
RW | 0 | |||||||||||
7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||
0 | TEST_EN | The test enable bit 0: Enable external reset 1: Disables the generation of an external reset. Instead bit 1 of the INT_CAUS register is set and an interrupt is generated
|
RW | 0 |
Address Offset | 0x0000 041C | ||
Physical Address | 0x4008 041C | Instance | 0x4008 041C |
Description | Interrupt Cause Test Mode | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | CAUSE_RESET | Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). | RO | 0 | ||
0 | CAUSE_INTR | Replica of RIS.WDTRIS | RO | 0 |
Address Offset | 0x0000 0C00 | ||
Physical Address | 0x4008 0C00 | Instance | 0x4008 0C00 |
Description | Lock | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | WDTLOCK | WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates (NOTE: TEST.TEST_EN bit is not lockable). A read of this register returns the following values: 0x0000.0000: Unlocked 0x0000.0001: Locked |
RW | 0x0000 0000 |
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