Instance: ADI_3_REFSYS
Component: ADI_3_REFSYS
Base address: 0x40086200
ADI for REFSYS modules.
Registers Fields should be considered static unless otherwise noted (as dynamic)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
8 |
0x00 |
0x0000 0001 |
0x4008 6201 |
|
RW |
8 |
0x00 |
0x0000 0002 |
0x4008 6202 |
|
RW |
8 |
0x00 |
0x0000 0003 |
0x4008 6203 |
|
RW |
8 |
0x00 |
0x0000 0004 |
0x4008 6204 |
|
RW |
8 |
0x00 |
0x0000 0005 |
0x4008 6205 |
|
RW |
8 |
0x00 |
0x0000 0006 |
0x4008 6206 |
|
RW |
8 |
0x00 |
0x0000 0007 |
0x4008 6207 |
|
RW |
8 |
0x00 |
0x0000 0008 |
0x4008 6208 |
|
RW |
8 |
0x00 |
0x0000 0009 |
0x4008 6209 |
|
RW |
8 |
0x00 |
0x0000 000A |
0x4008 620A |
|
RW |
8 |
0x00 |
0x0000 000B |
0x4008 620B |
|
RW |
8 |
0x00 |
0x0000 000C |
0x4008 620C |
|
RW |
8 |
0x00 |
0x0000 000D |
0x4008 620D |
|
RW |
8 |
0x00 |
0x0000 000E |
0x4008 620E |
Address Offset | 0x0000 0001 | ||
Physical Address | 0x4008 6201 | Instance | 0x4008 6201 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
7:5 | RESERVED5 | Internal. Only to be used through TI provided API. | RW | 0b000 | |||||||||||||||||
4:3 | ATEST0_CTL | Internal. Only to be used through TI provided API.
|
RW | 0b00 | |||||||||||||||||
2:0 | ATEST1_CTL | Internal. Only to be used through TI provided API.
|
RW | 0b000 |
Address Offset | 0x0000 0002 | ||
Physical Address | 0x4008 6202 | Instance | 0x4008 6202 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||
7:0 | TESTCTL | Internal. Only to be used through TI provided API.
|
RW | 0x00 |
Address Offset | 0x0000 0003 | ||
Physical Address | 0x4008 6203 | Instance | 0x4008 6203 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:3 | TRIM_VDDS_BOD | Internal. Only to be used through TI provided API.
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | BATMON_COMP_TEST_EN | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1:0 | TESTCTL | Internal. Only to be used through TI provided API.
|
RW | 0b00 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4008 6204 | Instance | 0x4008 6204 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:4 | TRIM_VREF | Internal. Only to be used through TI provided API. | RW | 0x0 | ||
3 | BOD_EXTERNAL_REG_MODE | Internal. Only to be used through TI provided API. | RW | 0 | ||
2 | RESERVED2 | Internal. Only to be used through TI provided API. | RW | 0 | ||
1:0 | TRIM_TSENSE | Internal. Only to be used through TI provided API. | RW | 0b00 |
Address Offset | 0x0000 0005 | ||
Physical Address | 0x4008 6205 | Instance | 0x4008 6205 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
7 | BOD_BG_TRIM_EN | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
6 | VTEMP_EN | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
5:0 | TRIM_VBG | Internal. Only to be used through TI provided API. | RW | 0b00 0000 |
Address Offset | 0x0000 0006 | ||
Physical Address | 0x4008 6206 | Instance | 0x4008 6206 |
Description | DCDC Control 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:5 | GLDO_ISRC | Set charge and re-charge current level. 2's complement encoding. 0x0: Default 11mA. 0x3: Max 15mA. 0x4: Max 5mA |
RW | 0b000 | ||
4:0 | VDDR_TRIM | Set the VDDR voltage. Proprietary encoding. Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. Step size = 16mV 0x00: Default, about 1.63V. 0x05: Typical voltage after trim voltage 1.71V. 0x15: Max voltage 1.96V. 0x16: Min voltage 1.47V. |
RW | 0b0 0000 |
Address Offset | 0x0000 0007 | ||
Physical Address | 0x4008 6207 | Instance | 0x4008 6207 |
Description | DCDC Control 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:6 | IPTAT_TRIM | Trim GLDO bias current. Proprietary encoding. 0x0: Default 0x1: Increase GLDO bias by 1.3x. 0x2: Increase GLDO bias by 1.6x. 0x3: Decrease GLDO bias by 0.7x. |
RW | 0b00 | ||
5 | VDDR_OK_HYST | Increase the hysteresis for when VDDR is considered ok. 0: Hysteresis = 60mV 1: Hysteresis = 70mV |
RW | 0 | ||
4:0 | VDDR_TRIM_SLEEP | Set the min VDDR voltage threshold during sleep mode. Proprietary encoding. Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. Step size = 16mV 0x00: Default, about 1.63V. 0x19: Typical voltage after trim voltage 1.52V. 0x15: Max voltage 1.96V. 0x16: Min voltage 1.47V. |
RW | 0b0 0000 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4008 6208 | Instance | 0x4008 6208 |
Description | DCDC Control 2 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||||||||||||||||||||
6 | TURNON_EA_SW | Turn on erroramp switch 0: Erroramp Off (Default) 1: Erroramp On. Turns on GLDO error amp switch. |
RW | 0 | ||||||||||||||||||||
5 | TEST_VDDR | Connect VDDR to ATEST bus 0: Not connected. 1: Connected Set TESTSEL = 0x0 first before setting this bit. |
RW | 0 | ||||||||||||||||||||
4 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off |
RW | 0 | ||||||||||||||||||||
3:0 | TESTSEL | Select signal for test bus, one hot.
|
RW | 0x0 |
Address Offset | 0x0000 0009 | ||
Physical Address | 0x4008 6209 | Instance | 0x4008 6209 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
7:5 | RESERVED0 | Internal. Only to be used through TI provided API. | RW | 0b000 | |||||||||||||||||
4:2 | DCDC_DRV_DS | Internal. Only to be used through TI provided API. | RW | 0b000 | |||||||||||||||||
1:0 | VDDR_BOOST_COMP | Internal. Only to be used through TI provided API.
|
RW | 0b00 |
Address Offset | 0x0000 000A | ||
Physical Address | 0x4008 620A | Instance | 0x4008 620A |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:6 | DEADTIME_TRIM | Internal. Only to be used through TI provided API. | RW | 0b00 | ||
5:3 | LOW_EN_SEL | Internal. Only to be used through TI provided API. | RW | 0b000 | ||
2:0 | HIGH_EN_SEL | Internal. Only to be used through TI provided API. | RW | 0b000 |
Address Offset | 0x0000 000B | ||
Physical Address | 0x4008 620B | Instance | 0x4008 620B |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
7:6 | RESERVED6 | Internal. Only to be used through TI provided API. | RW | 0b00 | |||||||||||
5 | TESTN | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
4 | TESTP | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
3 | DITHER_EN | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
2:0 | IPEAK | Internal. Only to be used through TI provided API. | RW | 0b000 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4008 620C | Instance | 0x4008 620C |
Description | RECHARGE_CONTROL_1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
6 | LPM_BIAS_BACKUP_EN | Activate the backup circuit in case the main circuit does not work | RW | 0 | ||
5 | DAC_DBG_OFFSET_COMP | Offset compensation signal (Debug Mode) | RW | 0 | ||
4 | DAC_DBG_HOLD | S-H Cap hold signal (Debug Mode) | RW | 0 | ||
3 | DAC_DBG_PRECHARGE | PRE-CHARGE signal (Debug Mode) | RW | 0 | ||
2 | DAC_DBG_CAP_SAMPLE | Cap-array sample signal (Debug Mode) | RW | 0 | ||
1 | DAC_DBG_SAMPLE | S-H Cap sample signal (Debug Mode) | RW | 0 | ||
0 | DAC_DBG_EN | Enable Debug Mode | RW | 0 |
Address Offset | 0x0000 000D | ||
Physical Address | 0x4008 620D | Instance | 0x4008 620D |
Description | Recharge Comparator Control Byte 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 | |||||||||||
4 | COMP_CLK_DISABLE | Enable/Disable the 32 kHz clock (SCLK_LF) to the recharge comparator
|
RW | 0 | |||||||||||
3:0 | TRIM_RECHARGE_COMP_REFLEVEL | Trim ref level of recharge. 0xF: 90% of VDDR level. 0x0: 100% of VDDR level. Step size = 0.67% of VDDR level. |
RW | 0x0 |
Address Offset | 0x0000 000E | ||
Physical Address | 0x4008 620E | Instance | 0x4008 620E |
Description | Recharge Comparator Control Byte 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
7 | RECHARGE_BLOCK_VTRIG_EN | Enable/Disable ATEST input to VDDR input of recharge comparator. Used for trimming the recharge voltage reference level
|
RW | 0 | |||||||||||
6 | RECHARGE_BLOCK_ATEST_EN | Enable/Disable test inputs/outputs to recharge comparator block
|
RW | 0 | |||||||||||
5 | FORCE_SAMPLE_VDDR | Force Sample of VDDR on cap divider
|
RW | 0 | |||||||||||
4:0 | TRIM_RECHARGE_COMP_OFFSET | Trim offset of Recharge comparator. 0x00: Maximum degeneration on input side (VDDR side). 0x1F: Maximum degeneration on reference side from cap divider. 0x10: Nominal code. |
RW | 0b0 0000 |
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