VIMS

Instance: VIMS
Component: VIMS
Base address: 0x40034000


Versatile Instruction Memory System
Controls memory access to the Flash and encapsulates the following instruction memories:
- Boot ROM
- Cache / GPRAM

TOP:VIMS Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

STAT

RO

32

0x0000 0000

0x0000 0000

0x4003 4000

CTL

RW

32

0x0000 0000

0x0000 0004

0x4003 4004

TOP:VIMS Register Descriptions

TOP:VIMS:STAT

Address Offset 0x0000 0000
Physical Address 0x4003 4000 Instance 0x4003 4000
Description Status
Displays current VIMS mode and line buffer status
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 IDCODE_LB_DIS Icode/Dcode flash line buffer status

0: Enabled or in transition to disabled
1: Disabled and flushed		 RO 0
4 SYSBUS_LB_DIS Sysbus flash line buffer control

0: Enabled or in transition to disabled
1: Disabled and flushed		 RO 0
3 MODE_CHANGING VIMS mode change status

0: VIMS is in the mode defined by MODE
1: VIMS is in the process of changing to the mode given in CTL.MODE		 RO 0
2 INV This bit is set when invalidation of the cache memory is active / ongoing RO 0
1:0 MODE Current VIMS mode
Value ENUM Name Description
0x0 GPRAM VIMS GPRAM mode
0x1 CACHE VIMS Cache mode
0x3 OFF VIMS Off mode
RO 0b00

TOP:VIMS:CTL

Address Offset 0x0000 0004
Physical Address 0x4003 4004 Instance 0x4003 4004
Description Control
Configure VIMS mode and line buffer settings
Type RW
Bits Field Name Description Type Reset
31 STATS_CLR Set this bit to clear statistic counters. RW 0
30 STATS_EN Set this bit to enable statistic counters. RW 0
29 DYN_CG_EN 0: The in-built clock gate functionality is bypassed.
1: The in-built clock gate functionality is enabled, automatically gating the clock when not needed.		 RW 0
28:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
5 IDCODE_LB_DIS Icode/Dcode flash line buffer control

0: Enable
1: Disable		 RW 0
4 SYSBUS_LB_DIS Sysbus flash line buffer control

0: Enable
1: Disable		 RW 0
3 ARB_CFG Icode/Dcode and sysbus arbitation scheme

0: Static arbitration (icode/docde > sysbus)
1: Round-robin arbitration		 RW 0
2 PREF_EN Tag prefetch control

0: Disabled
1: Enabled		 RW 0
1:0 MODE VIMS mode request.
Write accesses to this field will be blocked while STAT.MODE_CHANGING is set to 1.
Note: Transaction from CACHE mode to GPRAM mode should be done through OFF mode to minimize flash block delay.
Value ENUM Name Description
0x0 GPRAM VIMS GPRAM mode
0x1 CACHE VIMS Cache mode
0x3 OFF VIMS Off mode
RW 0b00


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