Data Movement Architecture

Jacinto 7 family of devices have a heterogeneous architecture including compute cores like Arm Cortex A, real time cores like Arm Cortex R, TI DSPs like C7x and C6x (in older devices) along with many hardware accelerators. The Jacinto 7 processors: heterogeneous processing cores in this training series talks about this.

There is also a UDMA overview presentation in the SDK which can be accessed here

Note

Please note this is specific to TDA4VM/DRA829 but is still largely applicable for other Jacinto 7 devices.

NAVSS Architecture (UDMA Focused) and Terminology

• NAVSS (Navigator Subsystem)

  • Container which groups together components which are involved in providing DMA services in a SoC

• UDMA-C (Controller)

  • Triggers request and receives response from UTC (Channel controller), DRU, PDMA

• UTC (Unified Transfer Controller)

  • Received Transfer Request from UDMA and performs actual transfers (Transfer Controller)

• DRU (Data Routing Unit)

  • Special UTC for high performance data movement esp meant for C7x algorithms

• PDMA (Peripheral DMA)

  • Located close to peripherals

• PSILSS (Packet Streaming Interface)

  • Switch fabric: Pairing source/destination, routing PSI-L packets

• Key Features:

  • Split DMA: Needs a paired TX and RX channel and transfer request contains independent params for TX and RX

  • Multiple Instances in an SOC: Main NAVSS and MCU NAVSS (*varies from SOC to SOC)

• RA (Ring Accelerator)

  • Mechanism to submit request to UDMA and get response back from UDMA

  • Manages queue and state for producer and consumer to exchange data (Note: not limited to UDMA alone)

• Proxy

  • Mechanism to access RA in an atomic way: Ex: 32-bit CPU like R5 can’t perform a 64-bit single atomic write to RA

• Events

  • 16-bit unique global entity which can be generated by specific sources

  • Can be used to trigger interrupt to CPU via IA/IR or to trigger other transfers

  • Sources include: RA, DMA channel, Ring monitors, various error events

• IA (Interrupt Aggregator)

  • With so many events possible in a system (up to 64K), it is not possible to route all events to the CPU interrupt (which are usually limited and in ~100 range)

  • Mechanism to aggregate events: Up to 64 event aggregation per VINT (Virtual interrupt: not yet an interrupt to the CPU, see IR)

  • Supports polling mode as well without generating interrupts

• IR (Interrupt Router)

  • M:N mux (cross bar) to generate interrupt to various CPU in the system

    • where M is larger compared to N with sources from VINT, other NAVSS modules like Timer Manager

    • N interrupts to the CPU (N usually in the range of 128 to MPU/GIC, 32 to each of R5FSS; specific value varies from SOC to SOC)

  • There are multiple IR in the system which are identical in functionality – only source and destination differs. We will cover only NAVSS IR specifics in this training