Hardware Architecture¶
The TI royalty-free SimpleLink CC2640R2 SDK is a complete software platform for developing CC2640R2F applications. This kit is based on the SimpleLink CC2640R2F, complete System-on-Chip (SoC) solution. The CC2640R2F combines a 2.4-GHz RF transceiver, 128-KB in-system programmable memory, 20KB of SRAM, and a full range of peripherals. The device is centered on an Arm ® Cortex ® M3 series processor that handles the application layer and RF protocol stacks and an autonomous radio core centered on an Arm Cortex®-M0 processor that handles all the low-level radio control and processing associated with the physical layer and parts of the link layer. The sensor controller block provides additional flexibility by allowing autonomous data acquisition and control independent of the Cortex-M3 processor, further extending the low-power capabilities of the CC2640R2F. Figure 3. shows the block diagram. For more information on the CC2640R2F, see the CC13x0 CC26x0 SimpleLink Wireless MCU Technical Reference Manual.
Figure 3. SimpleLink CC2640R2F Block Diagram
For detailed descriptions of the hardware described here, refer to the chapter 23 of the CC13x0 CC26x0 SimpleLink Wireless MCU Technical Reference Manual.
Arm Cortex-M0 (Radio Core)¶
The Cortex-M0 (CM0) core within the CC2640R2F is responsible for both interfacing to the radio hardware, and translating complex instructions from the Cortex-M3 (CM3) core into bits that are sent over the air using the radio. For the RF protocols, the CM0 implements the PHY layer of the protocol stack. Often, the CM0 is able to operate autonomously, which frees up the CM3 for higher-level protocol and application-layer processing.
The CM3 communicates with the CM0 through a hardware interface called the RF doorbell, which is documented in section 23.2 of the CC13x0 CC26x0 SimpleLink Wireless MCU Technical Reference Manual. The radio core firmware is not intended to be used or modified by the application developer.
Arm Cortex-M3 (System Core)¶
The system core (CM3) is designed to run the wireless protocol stack from the link layer up to the user application. The link layer interfaces to the radio core through a software module called the RF driver, which sits above the RF doorbell. The RF driver runs on the CM3 and acts as an interface to the radio on the CC2640R2F, and also manages the power domains of the radio hardware and core. Documentation for the RF driver can be found at the TI Driver API Reference.
Flash, RAM, and Peripherals¶
The CC2640R2F contains 128KB of in-system programmable flash memory, 20KB of SRAM, and a full range of peripherals. The flash is split into erasable pages of 4KB. The CC2640R2F also contains 8KB of cache SRAM that can be utilized to extend RAM capacity or can function as a normal cache to increase application performance. Other peripherals include UART, I2C, I2S, AES, TRNG, temperature and battery monitors, 4x 32-bit timers, 2x SSI, and an itegrated and autonomous sensor controller. See Sensor Controller for more information on the sensor controller.
Programming Internal Flash With the ROM Bootloader¶
The CC2640R2F internal flash memory can be programmed using the bootloader in the ROM of the device. Both UART and SPI protocols are supported. For more details on the programming protocol and requirements, see the Bootloader chapter of the CC13x0 CC26x0 SimpleLink Wireless MCU Technical Reference Manual.
Note
Because the ROM bootloader uses predefined DIO pins for internal flash programming, allocate these pins in the layout of your board. For details on the pins allocated to the bootloader based on the chip package type, see CC13x0 CC26x0 SimpleLink Wireless MCU Technical Reference Manual.
Startup Sequence¶
For a complete description of the CC2640R2F reset sequence, see the CC13x0 CC26x0 SimpleLink Wireless MCU Technical Reference Manual.
