135 #ifndef ti_drivers_spi_SPIMSP432DMA__include 136 #define ti_drivers_spi_SPIMSP432DMA__include 144 #include <ti/devices/DeviceFamily.h> 146 #include <ti/drivers/dpl/HwiP.h> 147 #include <ti/drivers/dpl/SemaphoreP.h> 201 #define SPIMSP432DMA_P1_0_UCA0STE 0x00000110 202 #define SPIMSP432DMA_P1_1_UCA0CLK 0x00000111 203 #define SPIMSP432DMA_P1_2_UCA0SOMI 0x00000112 204 #define SPIMSP432DMA_P1_3_UCA0SIMO 0x00000113 207 #define SPIMSP432DMA_P1_4_UCB0STE 0x00000114 208 #define SPIMSP432DMA_P1_5_UCB0CLK 0x00000115 209 #define SPIMSP432DMA_P1_6_UCB0SIMO 0x00000116 210 #define SPIMSP432DMA_P1_7_UCB0SOMI 0x00000117 213 #define SPIMSP432DMA_P2_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x20) 214 #define SPIMSP432DMA_P2_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x20) 215 #define SPIMSP432DMA_P2_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x20) 216 #define SPIMSP432DMA_P2_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x20) 217 #define SPIMSP432DMA_P2_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x20) 218 #define SPIMSP432DMA_P2_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x20) 219 #define SPIMSP432DMA_P2_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x20) 220 #define SPIMSP432DMA_P2_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x20) 221 #define SPIMSP432DMA_P2_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x20) 222 #define SPIMSP432DMA_P2_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x20) 223 #define SPIMSP432DMA_P2_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x20) 224 #define SPIMSP432DMA_P2_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x20) 225 #define SPIMSP432DMA_P2_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x20) 226 #define SPIMSP432DMA_P2_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x20) 227 #define SPIMSP432DMA_P2_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x20) 228 #define SPIMSP432DMA_P2_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x20) 229 #define SPIMSP432DMA_P2_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x20) 230 #define SPIMSP432DMA_P2_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x20) 233 #define SPIMSP432DMA_P2_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x21) 234 #define SPIMSP432DMA_P2_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x21) 235 #define SPIMSP432DMA_P2_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x21) 236 #define SPIMSP432DMA_P2_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x21) 237 #define SPIMSP432DMA_P2_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x21) 238 #define SPIMSP432DMA_P2_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x21) 239 #define SPIMSP432DMA_P2_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x21) 240 #define SPIMSP432DMA_P2_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x21) 241 #define SPIMSP432DMA_P2_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x21) 242 #define SPIMSP432DMA_P2_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x21) 243 #define SPIMSP432DMA_P2_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x21) 244 #define SPIMSP432DMA_P2_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x21) 245 #define SPIMSP432DMA_P2_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x21) 246 #define SPIMSP432DMA_P2_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x21) 247 #define SPIMSP432DMA_P2_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x21) 248 #define SPIMSP432DMA_P2_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x21) 249 #define SPIMSP432DMA_P2_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x21) 250 #define SPIMSP432DMA_P2_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x21) 253 #define SPIMSP432DMA_P2_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x22) 254 #define SPIMSP432DMA_P2_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x22) 255 #define SPIMSP432DMA_P2_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x22) 256 #define SPIMSP432DMA_P2_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x22) 257 #define SPIMSP432DMA_P2_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x22) 258 #define SPIMSP432DMA_P2_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x22) 259 #define SPIMSP432DMA_P2_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x22) 260 #define SPIMSP432DMA_P2_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x22) 261 #define SPIMSP432DMA_P2_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x22) 262 #define SPIMSP432DMA_P2_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x22) 263 #define SPIMSP432DMA_P2_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x22) 264 #define SPIMSP432DMA_P2_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x22) 265 #define SPIMSP432DMA_P2_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x22) 266 #define SPIMSP432DMA_P2_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x22) 267 #define SPIMSP432DMA_P2_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x22) 268 #define SPIMSP432DMA_P2_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x22) 269 #define SPIMSP432DMA_P2_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x22) 270 #define SPIMSP432DMA_P2_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x22) 273 #define SPIMSP432DMA_P2_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x23) 274 #define SPIMSP432DMA_P2_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x23) 275 #define SPIMSP432DMA_P2_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x23) 276 #define SPIMSP432DMA_P2_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x23) 277 #define SPIMSP432DMA_P2_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x23) 278 #define SPIMSP432DMA_P2_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x23) 279 #define SPIMSP432DMA_P2_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x23) 280 #define SPIMSP432DMA_P2_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x23) 281 #define SPIMSP432DMA_P2_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x23) 282 #define SPIMSP432DMA_P2_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x23) 283 #define SPIMSP432DMA_P2_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x23) 284 #define SPIMSP432DMA_P2_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x23) 285 #define SPIMSP432DMA_P2_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x23) 286 #define SPIMSP432DMA_P2_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x23) 287 #define SPIMSP432DMA_P2_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x23) 288 #define SPIMSP432DMA_P2_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x23) 289 #define SPIMSP432DMA_P2_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x23) 290 #define SPIMSP432DMA_P2_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x23) 293 #define SPIMSP432DMA_P2_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x24) 294 #define SPIMSP432DMA_P2_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x24) 295 #define SPIMSP432DMA_P2_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x24) 296 #define SPIMSP432DMA_P2_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x24) 297 #define SPIMSP432DMA_P2_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x24) 298 #define SPIMSP432DMA_P2_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x24) 299 #define SPIMSP432DMA_P2_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x24) 300 #define SPIMSP432DMA_P2_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x24) 301 #define SPIMSP432DMA_P2_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x24) 302 #define SPIMSP432DMA_P2_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x24) 303 #define SPIMSP432DMA_P2_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x24) 304 #define SPIMSP432DMA_P2_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x24) 305 #define SPIMSP432DMA_P2_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x24) 306 #define SPIMSP432DMA_P2_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x24) 307 #define SPIMSP432DMA_P2_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x24) 308 #define SPIMSP432DMA_P2_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x24) 309 #define SPIMSP432DMA_P2_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x24) 310 #define SPIMSP432DMA_P2_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x24) 313 #define SPIMSP432DMA_P2_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x25) 314 #define SPIMSP432DMA_P2_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x25) 315 #define SPIMSP432DMA_P2_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x25) 316 #define SPIMSP432DMA_P2_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x25) 317 #define SPIMSP432DMA_P2_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x25) 318 #define SPIMSP432DMA_P2_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x25) 319 #define SPIMSP432DMA_P2_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x25) 320 #define SPIMSP432DMA_P2_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x25) 321 #define SPIMSP432DMA_P2_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x25) 322 #define SPIMSP432DMA_P2_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x25) 323 #define SPIMSP432DMA_P2_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x25) 324 #define SPIMSP432DMA_P2_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x25) 325 #define SPIMSP432DMA_P2_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x25) 326 #define SPIMSP432DMA_P2_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x25) 327 #define SPIMSP432DMA_P2_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x25) 328 #define SPIMSP432DMA_P2_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x25) 329 #define SPIMSP432DMA_P2_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x25) 330 #define SPIMSP432DMA_P2_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x25) 333 #define SPIMSP432DMA_P2_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x26) 334 #define SPIMSP432DMA_P2_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x26) 335 #define SPIMSP432DMA_P2_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x26) 336 #define SPIMSP432DMA_P2_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x26) 337 #define SPIMSP432DMA_P2_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x26) 338 #define SPIMSP432DMA_P2_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x26) 339 #define SPIMSP432DMA_P2_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x26) 340 #define SPIMSP432DMA_P2_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x26) 341 #define SPIMSP432DMA_P2_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x26) 342 #define SPIMSP432DMA_P2_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x26) 343 #define SPIMSP432DMA_P2_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x26) 344 #define SPIMSP432DMA_P2_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x26) 345 #define SPIMSP432DMA_P2_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x26) 346 #define SPIMSP432DMA_P2_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x26) 347 #define SPIMSP432DMA_P2_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x26) 348 #define SPIMSP432DMA_P2_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x26) 349 #define SPIMSP432DMA_P2_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x26) 350 #define SPIMSP432DMA_P2_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x26) 353 #define SPIMSP432DMA_P2_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x27) 354 #define SPIMSP432DMA_P2_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x27) 355 #define SPIMSP432DMA_P2_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x27) 356 #define SPIMSP432DMA_P2_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x27) 357 #define SPIMSP432DMA_P2_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x27) 358 #define SPIMSP432DMA_P2_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x27) 359 #define SPIMSP432DMA_P2_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x27) 360 #define SPIMSP432DMA_P2_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x27) 361 #define SPIMSP432DMA_P2_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x27) 362 #define SPIMSP432DMA_P2_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x27) 363 #define SPIMSP432DMA_P2_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x27) 364 #define SPIMSP432DMA_P2_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x27) 365 #define SPIMSP432DMA_P2_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x27) 366 #define SPIMSP432DMA_P2_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x27) 367 #define SPIMSP432DMA_P2_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x27) 368 #define SPIMSP432DMA_P2_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x27) 369 #define SPIMSP432DMA_P2_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x27) 370 #define SPIMSP432DMA_P2_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x27) 373 #define SPIMSP432DMA_P3_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x30) 374 #define SPIMSP432DMA_P3_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x30) 375 #define SPIMSP432DMA_P3_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x30) 376 #define SPIMSP432DMA_P3_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x30) 377 #define SPIMSP432DMA_P3_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x30) 378 #define SPIMSP432DMA_P3_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x30) 379 #define SPIMSP432DMA_P3_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x30) 380 #define SPIMSP432DMA_P3_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x30) 381 #define SPIMSP432DMA_P3_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x30) 382 #define SPIMSP432DMA_P3_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x30) 383 #define SPIMSP432DMA_P3_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x30) 384 #define SPIMSP432DMA_P3_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x30) 385 #define SPIMSP432DMA_P3_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x30) 386 #define SPIMSP432DMA_P3_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x30) 387 #define SPIMSP432DMA_P3_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x30) 388 #define SPIMSP432DMA_P3_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x30) 389 #define SPIMSP432DMA_P3_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x30) 390 #define SPIMSP432DMA_P3_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x30) 393 #define SPIMSP432DMA_P3_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x31) 394 #define SPIMSP432DMA_P3_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x31) 395 #define SPIMSP432DMA_P3_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x31) 396 #define SPIMSP432DMA_P3_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x31) 397 #define SPIMSP432DMA_P3_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x31) 398 #define SPIMSP432DMA_P3_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x31) 399 #define SPIMSP432DMA_P3_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x31) 400 #define SPIMSP432DMA_P3_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x31) 401 #define SPIMSP432DMA_P3_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x31) 402 #define SPIMSP432DMA_P3_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x31) 403 #define SPIMSP432DMA_P3_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x31) 404 #define SPIMSP432DMA_P3_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x31) 405 #define SPIMSP432DMA_P3_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x31) 406 #define SPIMSP432DMA_P3_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x31) 407 #define SPIMSP432DMA_P3_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x31) 408 #define SPIMSP432DMA_P3_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x31) 409 #define SPIMSP432DMA_P3_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x31) 410 #define SPIMSP432DMA_P3_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x31) 413 #define SPIMSP432DMA_P3_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x32) 414 #define SPIMSP432DMA_P3_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x32) 415 #define SPIMSP432DMA_P3_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x32) 416 #define SPIMSP432DMA_P3_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x32) 417 #define SPIMSP432DMA_P3_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x32) 418 #define SPIMSP432DMA_P3_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x32) 419 #define SPIMSP432DMA_P3_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x32) 420 #define SPIMSP432DMA_P3_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x32) 421 #define SPIMSP432DMA_P3_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x32) 422 #define SPIMSP432DMA_P3_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x32) 423 #define SPIMSP432DMA_P3_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x32) 424 #define SPIMSP432DMA_P3_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x32) 425 #define SPIMSP432DMA_P3_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x32) 426 #define SPIMSP432DMA_P3_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x32) 427 #define SPIMSP432DMA_P3_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x32) 428 #define SPIMSP432DMA_P3_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x32) 429 #define SPIMSP432DMA_P3_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x32) 430 #define SPIMSP432DMA_P3_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x32) 433 #define SPIMSP432DMA_P3_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x33) 434 #define SPIMSP432DMA_P3_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x33) 435 #define SPIMSP432DMA_P3_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x33) 436 #define SPIMSP432DMA_P3_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x33) 437 #define SPIMSP432DMA_P3_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x33) 438 #define SPIMSP432DMA_P3_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x33) 439 #define SPIMSP432DMA_P3_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x33) 440 #define SPIMSP432DMA_P3_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x33) 441 #define SPIMSP432DMA_P3_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x33) 442 #define SPIMSP432DMA_P3_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x33) 443 #define SPIMSP432DMA_P3_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x33) 444 #define SPIMSP432DMA_P3_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x33) 445 #define SPIMSP432DMA_P3_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x33) 446 #define SPIMSP432DMA_P3_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x33) 447 #define SPIMSP432DMA_P3_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x33) 448 #define SPIMSP432DMA_P3_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x33) 449 #define SPIMSP432DMA_P3_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x33) 450 #define SPIMSP432DMA_P3_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x33) 453 #define SPIMSP432DMA_P3_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x34) 454 #define SPIMSP432DMA_P3_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x34) 455 #define SPIMSP432DMA_P3_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x34) 456 #define SPIMSP432DMA_P3_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x34) 457 #define SPIMSP432DMA_P3_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x34) 458 #define SPIMSP432DMA_P3_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x34) 459 #define SPIMSP432DMA_P3_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x34) 460 #define SPIMSP432DMA_P3_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x34) 461 #define SPIMSP432DMA_P3_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x34) 462 #define SPIMSP432DMA_P3_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x34) 463 #define SPIMSP432DMA_P3_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x34) 464 #define SPIMSP432DMA_P3_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x34) 465 #define SPIMSP432DMA_P3_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x34) 466 #define SPIMSP432DMA_P3_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x34) 467 #define SPIMSP432DMA_P3_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x34) 468 #define SPIMSP432DMA_P3_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x34) 469 #define SPIMSP432DMA_P3_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x34) 470 #define SPIMSP432DMA_P3_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x34) 473 #define SPIMSP432DMA_P3_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x35) 474 #define SPIMSP432DMA_P3_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x35) 475 #define SPIMSP432DMA_P3_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x35) 476 #define SPIMSP432DMA_P3_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x35) 477 #define SPIMSP432DMA_P3_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x35) 478 #define SPIMSP432DMA_P3_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x35) 479 #define SPIMSP432DMA_P3_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x35) 480 #define SPIMSP432DMA_P3_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x35) 481 #define SPIMSP432DMA_P3_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x35) 482 #define SPIMSP432DMA_P3_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x35) 483 #define SPIMSP432DMA_P3_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x35) 484 #define SPIMSP432DMA_P3_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x35) 485 #define SPIMSP432DMA_P3_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x35) 486 #define SPIMSP432DMA_P3_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x35) 487 #define SPIMSP432DMA_P3_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x35) 488 #define SPIMSP432DMA_P3_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x35) 489 #define SPIMSP432DMA_P3_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x35) 490 #define SPIMSP432DMA_P3_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x35) 493 #define SPIMSP432DMA_P3_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x36) 494 #define SPIMSP432DMA_P3_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x36) 495 #define SPIMSP432DMA_P3_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x36) 496 #define SPIMSP432DMA_P3_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x36) 497 #define SPIMSP432DMA_P3_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x36) 498 #define SPIMSP432DMA_P3_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x36) 499 #define SPIMSP432DMA_P3_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x36) 500 #define SPIMSP432DMA_P3_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x36) 501 #define SPIMSP432DMA_P3_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x36) 502 #define SPIMSP432DMA_P3_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x36) 503 #define SPIMSP432DMA_P3_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x36) 504 #define SPIMSP432DMA_P3_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x36) 505 #define SPIMSP432DMA_P3_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x36) 506 #define SPIMSP432DMA_P3_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x36) 507 #define SPIMSP432DMA_P3_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x36) 508 #define SPIMSP432DMA_P3_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x36) 509 #define SPIMSP432DMA_P3_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x36) 510 #define SPIMSP432DMA_P3_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x36) 513 #define SPIMSP432DMA_P3_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x37) 514 #define SPIMSP432DMA_P3_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x37) 515 #define SPIMSP432DMA_P3_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x37) 516 #define SPIMSP432DMA_P3_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x37) 517 #define SPIMSP432DMA_P3_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x37) 518 #define SPIMSP432DMA_P3_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x37) 519 #define SPIMSP432DMA_P3_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x37) 520 #define SPIMSP432DMA_P3_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x37) 521 #define SPIMSP432DMA_P3_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x37) 522 #define SPIMSP432DMA_P3_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x37) 523 #define SPIMSP432DMA_P3_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x37) 524 #define SPIMSP432DMA_P3_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x37) 525 #define SPIMSP432DMA_P3_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x37) 526 #define SPIMSP432DMA_P3_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x37) 527 #define SPIMSP432DMA_P3_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x37) 528 #define SPIMSP432DMA_P3_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x37) 529 #define SPIMSP432DMA_P3_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x37) 530 #define SPIMSP432DMA_P3_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x37) 533 #define SPIMSP432DMA_P6_2_UCB1STE 0x00000162 534 #define SPIMSP432DMA_P6_3_UCB1CLK 0x00000163 535 #define SPIMSP432DMA_P6_4_UCB1SIMO 0x00000164 536 #define SPIMSP432DMA_P6_5_UCB1SOMI 0x00000165 537 #define SPIMSP432DMA_P6_6_UCB3SIMO 0x00000266 538 #define SPIMSP432DMA_P6_7_UCB3SOMI 0x00000267 541 #define SPIMSP432DMA_P7_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x70) 542 #define SPIMSP432DMA_P7_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x70) 543 #define SPIMSP432DMA_P7_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x70) 544 #define SPIMSP432DMA_P7_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x70) 545 #define SPIMSP432DMA_P7_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x70) 546 #define SPIMSP432DMA_P7_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x70) 547 #define SPIMSP432DMA_P7_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x70) 548 #define SPIMSP432DMA_P7_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x70) 549 #define SPIMSP432DMA_P7_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x70) 550 #define SPIMSP432DMA_P7_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x70) 551 #define SPIMSP432DMA_P7_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x70) 552 #define SPIMSP432DMA_P7_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x70) 553 #define SPIMSP432DMA_P7_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x70) 554 #define SPIMSP432DMA_P7_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x70) 555 #define SPIMSP432DMA_P7_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x70) 556 #define SPIMSP432DMA_P7_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x70) 557 #define SPIMSP432DMA_P7_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x70) 558 #define SPIMSP432DMA_P7_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x70) 561 #define SPIMSP432DMA_P7_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x71) 562 #define SPIMSP432DMA_P7_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x71) 563 #define SPIMSP432DMA_P7_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x71) 564 #define SPIMSP432DMA_P7_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x71) 565 #define SPIMSP432DMA_P7_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x71) 566 #define SPIMSP432DMA_P7_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x71) 567 #define SPIMSP432DMA_P7_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x71) 568 #define SPIMSP432DMA_P7_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x71) 569 #define SPIMSP432DMA_P7_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x71) 570 #define SPIMSP432DMA_P7_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x71) 571 #define SPIMSP432DMA_P7_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x71) 572 #define SPIMSP432DMA_P7_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x71) 573 #define SPIMSP432DMA_P7_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x71) 574 #define SPIMSP432DMA_P7_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x71) 575 #define SPIMSP432DMA_P7_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x71) 576 #define SPIMSP432DMA_P7_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x71) 577 #define SPIMSP432DMA_P7_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x71) 578 #define SPIMSP432DMA_P7_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x71) 581 #define SPIMSP432DMA_P7_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x72) 582 #define SPIMSP432DMA_P7_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x72) 583 #define SPIMSP432DMA_P7_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x72) 584 #define SPIMSP432DMA_P7_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x72) 585 #define SPIMSP432DMA_P7_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x72) 586 #define SPIMSP432DMA_P7_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x72) 587 #define SPIMSP432DMA_P7_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x72) 588 #define SPIMSP432DMA_P7_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x72) 589 #define SPIMSP432DMA_P7_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x72) 590 #define SPIMSP432DMA_P7_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x72) 591 #define SPIMSP432DMA_P7_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x72) 592 #define SPIMSP432DMA_P7_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x72) 593 #define SPIMSP432DMA_P7_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x72) 594 #define SPIMSP432DMA_P7_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x72) 595 #define SPIMSP432DMA_P7_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x72) 596 #define SPIMSP432DMA_P7_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x72) 597 #define SPIMSP432DMA_P7_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x72) 598 #define SPIMSP432DMA_P7_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x72) 601 #define SPIMSP432DMA_P7_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x73) 602 #define SPIMSP432DMA_P7_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x73) 603 #define SPIMSP432DMA_P7_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x73) 604 #define SPIMSP432DMA_P7_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x73) 605 #define SPIMSP432DMA_P7_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x73) 606 #define SPIMSP432DMA_P7_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x73) 607 #define SPIMSP432DMA_P7_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x73) 608 #define SPIMSP432DMA_P7_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x73) 609 #define SPIMSP432DMA_P7_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x73) 610 #define SPIMSP432DMA_P7_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x73) 611 #define SPIMSP432DMA_P7_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x73) 612 #define SPIMSP432DMA_P7_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x73) 613 #define SPIMSP432DMA_P7_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x73) 614 #define SPIMSP432DMA_P7_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x73) 615 #define SPIMSP432DMA_P7_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x73) 616 #define SPIMSP432DMA_P7_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x73) 617 #define SPIMSP432DMA_P7_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x73) 618 #define SPIMSP432DMA_P7_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x73) 621 #define SPIMSP432DMA_P7_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x74) 622 #define SPIMSP432DMA_P7_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x74) 623 #define SPIMSP432DMA_P7_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x74) 624 #define SPIMSP432DMA_P7_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x74) 625 #define SPIMSP432DMA_P7_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x74) 626 #define SPIMSP432DMA_P7_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x74) 627 #define SPIMSP432DMA_P7_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x74) 628 #define SPIMSP432DMA_P7_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x74) 629 #define SPIMSP432DMA_P7_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x74) 630 #define SPIMSP432DMA_P7_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x74) 631 #define SPIMSP432DMA_P7_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x74) 632 #define SPIMSP432DMA_P7_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x74) 633 #define SPIMSP432DMA_P7_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x74) 634 #define SPIMSP432DMA_P7_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x74) 635 #define SPIMSP432DMA_P7_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x74) 636 #define SPIMSP432DMA_P7_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x74) 637 #define SPIMSP432DMA_P7_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x74) 638 #define SPIMSP432DMA_P7_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x74) 641 #define SPIMSP432DMA_P7_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x75) 642 #define SPIMSP432DMA_P7_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x75) 643 #define SPIMSP432DMA_P7_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x75) 644 #define SPIMSP432DMA_P7_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x75) 645 #define SPIMSP432DMA_P7_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x75) 646 #define SPIMSP432DMA_P7_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x75) 647 #define SPIMSP432DMA_P7_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x75) 648 #define SPIMSP432DMA_P7_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x75) 649 #define SPIMSP432DMA_P7_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x75) 650 #define SPIMSP432DMA_P7_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x75) 651 #define SPIMSP432DMA_P7_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x75) 652 #define SPIMSP432DMA_P7_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x75) 653 #define SPIMSP432DMA_P7_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x75) 654 #define SPIMSP432DMA_P7_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x75) 655 #define SPIMSP432DMA_P7_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x75) 656 #define SPIMSP432DMA_P7_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x75) 657 #define SPIMSP432DMA_P7_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x75) 658 #define SPIMSP432DMA_P7_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x75) 661 #define SPIMSP432DMA_P7_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x76) 662 #define SPIMSP432DMA_P7_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x76) 663 #define SPIMSP432DMA_P7_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x76) 664 #define SPIMSP432DMA_P7_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x76) 665 #define SPIMSP432DMA_P7_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x76) 666 #define SPIMSP432DMA_P7_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x76) 667 #define SPIMSP432DMA_P7_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x76) 668 #define SPIMSP432DMA_P7_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x76) 669 #define SPIMSP432DMA_P7_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x76) 670 #define SPIMSP432DMA_P7_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x76) 671 #define SPIMSP432DMA_P7_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x76) 672 #define SPIMSP432DMA_P7_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x76) 673 #define SPIMSP432DMA_P7_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x76) 674 #define SPIMSP432DMA_P7_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x76) 675 #define SPIMSP432DMA_P7_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x76) 676 #define SPIMSP432DMA_P7_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x76) 677 #define SPIMSP432DMA_P7_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x76) 678 #define SPIMSP432DMA_P7_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x76) 681 #define SPIMSP432DMA_P7_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x77) 682 #define SPIMSP432DMA_P7_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x77) 683 #define SPIMSP432DMA_P7_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x77) 684 #define SPIMSP432DMA_P7_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x77) 685 #define SPIMSP432DMA_P7_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x77) 686 #define SPIMSP432DMA_P7_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x77) 687 #define SPIMSP432DMA_P7_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x77) 688 #define SPIMSP432DMA_P7_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x77) 689 #define SPIMSP432DMA_P7_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x77) 690 #define SPIMSP432DMA_P7_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x77) 691 #define SPIMSP432DMA_P7_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x77) 692 #define SPIMSP432DMA_P7_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x77) 693 #define SPIMSP432DMA_P7_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x77) 694 #define SPIMSP432DMA_P7_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x77) 695 #define SPIMSP432DMA_P7_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x77) 696 #define SPIMSP432DMA_P7_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x77) 697 #define SPIMSP432DMA_P7_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x77) 698 #define SPIMSP432DMA_P7_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x77) 701 #define SPIMSP432DMA_P8_0_UCB3STE 0x00000180 702 #define SPIMSP432DMA_P8_1_UCB3CLK 0x00000181 705 #define SPIMSP432DMA_P9_4_UCA3STE 0x00000194 706 #define SPIMSP432DMA_P9_5_UCA3CLK 0x00000195 707 #define SPIMSP432DMA_P9_6_UCA3SOMI 0x00000196 708 #define SPIMSP432DMA_P9_7_UCA3SIMO 0x00000197 711 #define SPIMSP432DMA_P10_0_UCB3STE 0x000001A0 712 #define SPIMSP432DMA_P10_1_UCB3CLK 0x000001A1 713 #define SPIMSP432DMA_P10_2_UCB3SIMO 0x000001A2 714 #define SPIMSP432DMA_P10_3_UCB3SOMI 0x000001A3 742 #define SPIMSP432DMA_PIN_NO_CONFIG (0x0000FFFF) SPI_TransferMode transferMode
Definition: SPIMSP432DMA.h:879
void(* SPI_CallbackFxn)(SPI_Handle handle, SPI_Transaction *transaction)
The definition of a callback function used by the SPI driver when used in SPI_MODE_CALLBACK.
Definition: SPI.h:569
uint16_t clockPhase
Definition: SPIMSP432DMA.h:876
enum SPI_Mode_ SPI_Mode
Definitions for various SPI modes of operation.
SPIMSP432DMA Hardware attributes These fields, with the exception of intPriority, are used by driverl...
Definition: SPIMSP432DMA.h:836
SPI_Mode spiMode
Definition: SPIMSP432DMA.h:878
A SPI_Transaction data structure is used with SPI_transfer(). It indicates how many SPI_FrameFormat f...
Definition: SPI.h:548
struct SPIMSP432DMA_HWAttrsV1 SPIMSP432DMA_HWAttrsV1
SPIMSP432DMA Hardware attributes These fields, with the exception of intPriority, are used by driverl...
uint16_t pinMode
Definition: SPIMSP432DMA.h:852
uint16_t bitOrder
Definition: SPIMSP432DMA.h:838
uint32_t baseAddr
Definition: SPIMSP432DMA.h:837
UDMAMSP432_Handle dmaHandle
Definition: SPIMSP432DMA.h:868
Power notify object structure.
Definition: Power.h:121
HwiP_Handle hwiHandle
Definition: SPIMSP432DMA.h:863
bool cancelInProgress
Definition: SPIMSP432DMA.h:881
uint32_t txDMAChannelIndex
Definition: SPIMSP432DMA.h:846
SPIMSP432DMA Object.
Definition: SPIMSP432DMA.h:862
size_t amtDataXferred
Definition: SPIMSP432DMA.h:870
uint8_t defaultTxBufValue
Definition: SPIMSP432DMA.h:841
enum SPI_TransferMode_ SPI_TransferMode
SPI transfer mode determines the whether the SPI controller operates synchronously or asynchronously...
The definition of a SPI function table that contains the required set of functions to control a speci...
Definition: SPI.h:683
SPI_Transaction * transaction
Definition: SPIMSP432DMA.h:867
uint16_t stePin
Definition: SPIMSP432DMA.h:851
struct SPIMSP432DMA_Object SPIMSP432DMA_Object
SPIMSP432DMA Object.
uint16_t minDmaTransferSize
Definition: SPIMSP432DMA.h:854
uDMA driver implementation for MSP432.
uint8_t dmaIntNum
Definition: SPIMSP432DMA.h:843
uint16_t somiPin
Definition: SPIMSP432DMA.h:849
uint8_t scratchBuffer
Definition: SPIMSP432DMA.h:883
uint16_t clockPolarity
Definition: SPIMSP432DMA.h:875
UDMAMSP432 Global configuration.
Definition: UDMAMSP432.h:127
uint32_t transferTimeout
Definition: SPIMSP432DMA.h:874
Power_NotifyObj perfChangeNotify
Definition: SPIMSP432DMA.h:864
uint32_t perfConstraintMask
Definition: SPIMSP432DMA.h:873
uint32_t bitRate
Definition: SPIMSP432DMA.h:872
const SPI_FxnTable SPIMSP432DMA_fxnTable
SPI_CallbackFxn transferCallbackFxn
Definition: SPIMSP432DMA.h:866
SemaphoreP_Handle transferComplete
Definition: SPIMSP432DMA.h:865
uint8_t clockSource
Definition: SPIMSP432DMA.h:839
bool isOpen
Definition: SPIMSP432DMA.h:882
struct SPIMSP432DMA_Object * SPIMSP432DMA_Handle
uint32_t intPriority
Definition: SPIMSP432DMA.h:844
uint16_t clkPin
Definition: SPIMSP432DMA.h:850
size_t currentXferAmt
Definition: SPIMSP432DMA.h:871
uint32_t rxDMAChannelIndex
Definition: SPIMSP432DMA.h:845
uint16_t simoPin
Definition: SPIMSP432DMA.h:848