SPI driver implementation for a EUSCI peripheral on MSP432 using the micro DMA controller.
============================================================================
The SPI header file should be included in an application as follows:
Refer to SPI.h for a complete description of APIs & example of use.
This SPI driver implementation is designed to operate on a EUCSI controller in SPI mode using a micro DMA controller.
- Warning
- This driver does not support queueing multiple SPI transactions.
Frame Formats
This SPI controller supports 4 phase & polarity formats. Refer to the device specific data sheets & technical reference manuals for specifics on each format.
SPI Chip Select
The SPI driver can be used in 3-pin or 4-pin mode. When in 4-pin mode the hardware manages a pin as the chip select. In 3-pin mode it is the application's responsibility to assert and de-assert a GPIO pin for chip select purposes.
| Chip select type | SPI_MASTER mode | SPI_SLAVE mode |
| Hardware chip select | No action is needed by the application to select the peripheral. | See the device documentation on it's chip select requirements. |
| Software chip select | The application is responsible to ensure that correct SPI slave is selected before performing a SPI_transfer(). | Up to the application's implementation. |
SPI data frames
The EUSCI controller only supports 8-bit data frames.
| dataSize | buffer element size |
| 8 bits | uint8_t |
DMA operation
DMA use in this driver varies based on the SPI_TransferMode set when the driver instance was opened. If the driver was opened in SPI_MODE_CALLBACK, all transfers make use of the DMA regardless of the amount of data.
If the driver was opened in SPI_MODE_BLOCKING, it verifies the amount of data frames to be transfered exceeds the minDmaTransferSize before performing a transfer using the DMA. minDmaTransferSize (in the SPIMSP432DMA_HWAttrs) allows users to set a minimum amount of data frames a transfer must have to perform a transfer using the DMA. If the amount of data is less than minDmaTransferSize, the driver performs a polling transfer (unless the device is a slave with a timeout configured). This feature is provided for situations where there is little data to be transfered & it is more efficient to simply perform a polling transfer instead of configuring the DMA & waiting until the task is unblocked.
DMA Interrupts
The MSP432 DMA controller has 4 interrupt vectors to handle all DMA related IRQ. Due to the "shared" nature of the DMA interrupts, this driver implementation requires each SPI instance to explicitly use a single DMA interrupt. It is up to the application to ensure no two peripherals are configured to respond to a given DMA interrupt at any moment.
DMA transfer size limit
The DMA controller only supports data transfers of up to 1024 data frames, so large amounts of data will be split & transfered accordingly. Each SPI driver instance requires 2 DMA channels (Tx and Rx) to operate.
DMA accessible memory
Ensure that the txBuf and rxBuf (in SPI_Transaction) point to memory that is accessible by the DMA.
Scratch Buffers
A uint8_t scratch buffer is used to allow SPI_transfers where txBuf or rxBuf are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer of size of the transfer count, a single DMA accessible uint8_t scratch buffer is used. When txBuf is NULL, an internal scratch buffer is initialized to the defaultTxBufValue so the DMA will send some known value.
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| #define | SPIMSP432DMA_P1_0_UCA0STE 0x00000110 /* Primary, port 1, pin 0 */ |
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| #define | SPIMSP432DMA_P1_1_UCA0CLK 0x00000111 /* Primary, port 1, pin 1 */ |
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| #define | SPIMSP432DMA_P1_2_UCA0SOMI 0x00000112 /* Primary, port 1, pin 2 */ |
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| #define | SPIMSP432DMA_P1_3_UCA0SIMO 0x00000113 /* Primary, port 1, pin 3 */ |
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| #define | SPIMSP432DMA_P1_4_UCB0STE 0x00000114 /* Primary, port 1, pin 4 */ |
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| #define | SPIMSP432DMA_P1_5_UCB0CLK 0x00000115 /* Primary, port 1, pin 5 */ |
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| #define | SPIMSP432DMA_P1_6_UCB0SIMO 0x00000116 /* Primary, port 1, pin 6 */ |
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| #define | SPIMSP432DMA_P1_7_UCB0SOMI 0x00000117 /* Primary, port 1, pin 7 */ |
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| #define | SPIMSP432DMA_P2_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x20) |
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| #define | SPIMSP432DMA_P2_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x21) |
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| #define | SPIMSP432DMA_P2_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x22) |
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| #define | SPIMSP432DMA_P2_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x23) |
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| #define | SPIMSP432DMA_P2_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x24) |
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| #define | SPIMSP432DMA_P2_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x25) |
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| #define | SPIMSP432DMA_P2_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x26) |
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| #define | SPIMSP432DMA_P2_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x27) |
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| #define | SPIMSP432DMA_P2_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x27) |
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| #define | SPIMSP432DMA_P3_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x30) |
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| #define | SPIMSP432DMA_P3_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x31) |
| |
| #define | SPIMSP432DMA_P3_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x32) |
| |
| #define | SPIMSP432DMA_P3_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x33) |
| |
| #define | SPIMSP432DMA_P3_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x34) |
| |
| #define | SPIMSP432DMA_P3_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x35) |
| |
| #define | SPIMSP432DMA_P3_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x36) |
| |
| #define | SPIMSP432DMA_P3_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P3_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x37) |
| |
| #define | SPIMSP432DMA_P6_2_UCB1STE 0x00000162 /* Primary, port 6, pin 2 */ |
| |
| #define | SPIMSP432DMA_P6_3_UCB1CLK 0x00000163 /* Primary, port 6, pin 3 */ |
| |
| #define | SPIMSP432DMA_P6_4_UCB1SIMO 0x00000164 /* Primary, port 6, pin 4 */ |
| |
| #define | SPIMSP432DMA_P6_5_UCB1SOMI 0x00000165 /* Primary, port 6, pin 5 */ |
| |
| #define | SPIMSP432DMA_P6_6_UCB3SIMO 0x00000266 /* Secondary, port 6, pin 6 */ |
| |
| #define | SPIMSP432DMA_P6_7_UCB3SOMI 0x00000267 /* Secondary, port 6, pin 7 */ |
| |
| #define | SPIMSP432DMA_P7_0_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA1STE ((PMAP_UCA1STE << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCA2STE ((PMAP_UCA2STE << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_0_UCB2STE ((PMAP_UCB2STE << 10) | 0x70) |
| |
| #define | SPIMSP432DMA_P7_1_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA1STE ((PMAP_UCA1STE << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCA2STE ((PMAP_UCA2STE << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_1_UCB2STE ((PMAP_UCB2STE << 10) | 0x71) |
| |
| #define | SPIMSP432DMA_P7_2_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA1STE ((PMAP_UCA1STE << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCA2STE ((PMAP_UCA2STE << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_2_UCB2STE ((PMAP_UCB2STE << 10) | 0x72) |
| |
| #define | SPIMSP432DMA_P7_3_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA1STE ((PMAP_UCA1STE << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCA2STE ((PMAP_UCA2STE << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_3_UCB2STE ((PMAP_UCB2STE << 10) | 0x73) |
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| #define | SPIMSP432DMA_P7_4_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA1STE ((PMAP_UCA1STE << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCA2STE ((PMAP_UCA2STE << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_4_UCB2STE ((PMAP_UCB2STE << 10) | 0x74) |
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| #define | SPIMSP432DMA_P7_5_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA1STE ((PMAP_UCA1STE << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCA2STE ((PMAP_UCA2STE << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_5_UCB2STE ((PMAP_UCB2STE << 10) | 0x75) |
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| #define | SPIMSP432DMA_P7_6_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA1STE ((PMAP_UCA1STE << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCA2STE ((PMAP_UCA2STE << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_6_UCB2STE ((PMAP_UCB2STE << 10) | 0x76) |
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| #define | SPIMSP432DMA_P7_7_UCA0CLK ((PMAP_UCA0CLK << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA0SIMO ((PMAP_UCA0SIMO << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA0SOMI ((PMAP_UCA0SOMI << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA1CLK ((PMAP_UCA1CLK << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA1SIMO ((PMAP_UCA1SIMO << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA1SOMI ((PMAP_UCA1SOMI << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA2CLK ((PMAP_UCA2CLK << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA2SIMO ((PMAP_UCA2SIMO << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA2SOMI ((PMAP_UCA2SOMI << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCB0CLK ((PMAP_UCB0CLK << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCB0SIMO ((PMAP_UCB0SIMO << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCB0SOMI ((PMAP_UCB0SOMI << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCB2CLK ((PMAP_UCB2CLK << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCB2SIMO ((PMAP_UCB2SIMO << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCB2SOMI ((PMAP_UCB2SOMI << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA1STE ((PMAP_UCA1STE << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCA2STE ((PMAP_UCA2STE << 10) | 0x77) |
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| #define | SPIMSP432DMA_P7_7_UCB2STE ((PMAP_UCB2STE << 10) | 0x77) |
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| #define | SPIMSP432DMA_P8_0_UCB3STE 0x00000180 /* Primary, port 8, pin 0 */ |
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| #define | SPIMSP432DMA_P8_1_UCB3CLK 0x00000181 /* Primary, port 8, pin 1 */ |
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| #define | SPIMSP432DMA_P9_4_UCA3STE 0x00000194 /* Primary, port 9, pin 4 */ |
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| #define | SPIMSP432DMA_P9_5_UCA3CLK 0x00000195 /* Primary, port 9, pin 5 */ |
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| #define | SPIMSP432DMA_P9_6_UCA3SOMI 0x00000196 /* Primary, port 9, pin 6 */ |
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| #define | SPIMSP432DMA_P9_7_UCA3SIMO 0x00000197 /* Primary, port 9, pin 7 */ |
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| #define | SPIMSP432DMA_P10_0_UCB3STE 0x000001A0 /* Primary, port 10, pin 0 */ |
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| #define | SPIMSP432DMA_P10_1_UCB3CLK 0x000001A1 /* Primary, port 10, pin 1 */ |
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| #define | SPIMSP432DMA_P10_2_UCB3SIMO 0x000001A2 /* Primary, port 10, pin 2 */ |
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| #define | SPIMSP432DMA_P10_3_UCB3SOMI 0x000001A3 /* Primary, port 10, pin 3 */ |
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| #define | SPIMSP432DMA_PIN_NO_CONFIG (0x0000FFFF) |
| | SPIMSP432DMA_PIN_NO_CONFIG can be used to inform the SPIMSP432DMA driver that a pin should not be configured for use in the SPI bus. If the simoPin, somiPin or stePin is set to SPIMSP432DMA_PIN_NO_CONFIG in the SPIMSP432DMA_HWAttrs, the pin is not configured to SPI functionality during SPI_open() and the pin can be used for another function. The clkPin cannot be set to SPIMSP432DMA_PIN_NO_CONFIG; the clock signal is always required during communication & must be driven by the SPI bus master. More...
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