Collaboration diagram for MSPM0C110X System Control (SYSCTL):

Modules
	DL_SYSCTL_RESET

	DL_SYSCTL_INTERRUPT

	DL_SYSCTL_NMI

	DL_SYSCTL_CLK_STATUS

	DL_SYSCTL_STATUS

Macros
#define	DL_SYSCTL_setMCLKSource(current, next, ...) DL_SYSCTL_switchMCLKfrom##current##to##next(__VA_ARGS__);
	Change MCLK source. More...

Enumerations
enum	DL_SYSCTL_IIDX { DL_SYSCTL_IIDX_LFOSC_GOOD = SYSCTL_IIDX_STAT_LFOSCGOOD, DL_SYSCTL_IIDX_ANALOG_CLOCK_ERROR = SYSCTL_IIDX_STAT_ANACLKERR }

enum	DL_SYSCTL_NMI_IIDX { DL_SYSCTL_NMI_IIDX_WWDT0_FAULT = SYSCTL_NMIIIDX_STAT_WWDT0, DL_SYSCTL_NMI_IIDX_BORLVL = SYSCTL_NMIIIDX_STAT_BORLVL, DL_SYSCTL_NMI_IIDX_NO_INT = SYSCTL_NMIIIDX_STAT_NO_INTR }

enum	DL_SYSCTL_ERROR_BEHAVIOR { DL_SYSCTL_ERROR_BEHAVIOR_RESET = 0x0, DL_SYSCTL_ERROR_BEHAVIOR_NMI = 0x1 }

enum	DL_SYSCTL_SYSOSC_FREQ { DL_SYSCTL_SYSOSC_FREQ_4M = (SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M), DL_SYSCTL_SYSOSC_FREQ_BASE = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE), DL_SYSCTL_SYSOSC_FREQ_USERTRIM = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER) }

enum	DL_SYSCTL_MCLK_SOURCE { DL_SYSCTL_MCLK_SOURCE_SYSOSC = SYSCTL_MCLKCFG_USEHSCLK_DISABLE, DL_SYSCTL_MCLK_SOURCE_HSCLK = SYSCTL_MCLKCFG_USEHSCLK_ENABLE, DL_SYSCTL_MCLK_SOURCE_LFCLK = SYSCTL_MCLKCFG_USELFCLK_ENABLE }

enum	DL_SYSCTL_MCLK_DIVIDER { DL_SYSCTL_MCLK_DIVIDER_DISABLE = 0x0, DL_SYSCTL_MCLK_DIVIDER_2 = 0x1, DL_SYSCTL_MCLK_DIVIDER_3 = 0x2, DL_SYSCTL_MCLK_DIVIDER_4 = 0x3, DL_SYSCTL_MCLK_DIVIDER_5 = 0x4, DL_SYSCTL_MCLK_DIVIDER_6 = 0x5, DL_SYSCTL_MCLK_DIVIDER_7 = 0x6, DL_SYSCTL_MCLK_DIVIDER_8 = 0x7, DL_SYSCTL_MCLK_DIVIDER_9 = 0x8, DL_SYSCTL_MCLK_DIVIDER_10 = 0x9, DL_SYSCTL_MCLK_DIVIDER_11 = 0xA, DL_SYSCTL_MCLK_DIVIDER_12 = 0xB, DL_SYSCTL_MCLK_DIVIDER_13 = 0xC, DL_SYSCTL_MCLK_DIVIDER_14 = 0xD, DL_SYSCTL_MCLK_DIVIDER_15 = 0xE, DL_SYSCTL_MCLK_DIVIDER_16 = 0xF }

enum	DL_SYSCTL_CLK_OUT_SOURCE { DL_SYSCTL_CLK_OUT_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC, DL_SYSCTL_CLK_OUT_SOURCE_ULPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK, DL_SYSCTL_CLK_OUT_SOURCE_LFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK, DL_SYSCTL_CLK_OUT_SOURCE_MFPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK, DL_SYSCTL_CLK_OUT_SOURCE_HFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK }

enum	DL_SYSCTL_CLK_OUT_DIVIDE { DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE = SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU, DL_SYSCTL_CLK_OUT_DIVIDE_2, DL_SYSCTL_CLK_OUT_DIVIDE_4, DL_SYSCTL_CLK_OUT_DIVIDE_6, DL_SYSCTL_CLK_OUT_DIVIDE_8, DL_SYSCTL_CLK_OUT_DIVIDE_10, DL_SYSCTL_CLK_OUT_DIVIDE_12, DL_SYSCTL_CLK_OUT_DIVIDE_14, DL_SYSCTL_CLK_OUT_DIVIDE_16 }

enum	DL_SYSCTL_VBOOST { DL_SYSCTL_VBOOST_ONDEMAND = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND, DL_SYSCTL_VBOOST_ONACTIVE = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE, DL_SYSCTL_VBOOST_ONALWAYS = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS }

enum	DL_SYSCTL_FCC_TRIG_TYPE { DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE = SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE, DL_SYSCTL_FCC_TRIG_TYPE_LEVEL = SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL }

enum	DL_SYSCTL_FCC_TRIG_SOURCE { DL_SYSCTL_FCC_TRIG_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN, DL_SYSCTL_FCC_TRIG_SOURCE_LFCLK = SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK }

enum	DL_SYSCTL_FCC_CLOCK_SOURCE { DL_SYSCTL_FCC_CLOCK_SOURCE_MCLK = SYSCTL_GENCLKCFG_FCCSELCLK_MCLK, DL_SYSCTL_FCC_CLOCK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC, DL_SYSCTL_FCC_CLOCK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK, DL_SYSCTL_FCC_CLOCK_SOURCE_CLK_OUT = SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK, DL_SYSCTL_FCC_CLOCK_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN }

enum	DL_SYSCTL_FCC_TRIG_CNT { DL_SYSCTL_FCC_TRIG_CNT_01, DL_SYSCTL_FCC_TRIG_CNT_02, DL_SYSCTL_FCC_TRIG_CNT_03, DL_SYSCTL_FCC_TRIG_CNT_04, DL_SYSCTL_FCC_TRIG_CNT_05, DL_SYSCTL_FCC_TRIG_CNT_06, DL_SYSCTL_FCC_TRIG_CNT_07, DL_SYSCTL_FCC_TRIG_CNT_08, DL_SYSCTL_FCC_TRIG_CNT_09, DL_SYSCTL_FCC_TRIG_CNT_10, DL_SYSCTL_FCC_TRIG_CNT_11, DL_SYSCTL_FCC_TRIG_CNT_12, DL_SYSCTL_FCC_TRIG_CNT_13, DL_SYSCTL_FCC_TRIG_CNT_14, DL_SYSCTL_FCC_TRIG_CNT_15, DL_SYSCTL_FCC_TRIG_CNT_16, DL_SYSCTL_FCC_TRIG_CNT_17, DL_SYSCTL_FCC_TRIG_CNT_18, DL_SYSCTL_FCC_TRIG_CNT_19, DL_SYSCTL_FCC_TRIG_CNT_20, DL_SYSCTL_FCC_TRIG_CNT_21, DL_SYSCTL_FCC_TRIG_CNT_22, DL_SYSCTL_FCC_TRIG_CNT_23, DL_SYSCTL_FCC_TRIG_CNT_24, DL_SYSCTL_FCC_TRIG_CNT_25, DL_SYSCTL_FCC_TRIG_CNT_26, DL_SYSCTL_FCC_TRIG_CNT_27, DL_SYSCTL_FCC_TRIG_CNT_28, DL_SYSCTL_FCC_TRIG_CNT_29, DL_SYSCTL_FCC_TRIG_CNT_30, DL_SYSCTL_FCC_TRIG_CNT_31, DL_SYSCTL_FCC_TRIG_CNT_32 }

enum	DL_SYSCTL_POWER_POLICY_RUN_SLEEP { DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED = 0x0, DL_SYSCTL_POWER_POLICY_RUN_SLEEP0 = 0x1, DL_SYSCTL_POWER_POLICY_RUN_SLEEP1 = 0x2, DL_SYSCTL_POWER_POLICY_RUN_SLEEP2 = 0x3 }

enum	DL_SYSCTL_POWER_POLICY_STOP { DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED = 0x0, DL_SYSCTL_POWER_POLICY_STOP0 = 0x1, DL_SYSCTL_POWER_POLICY_STOP2 = 0x3 }

enum	DL_SYSCTL_POWER_POLICY_STANDBY { DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED = 0x0, DL_SYSCTL_POWER_POLICY_STANDBY0 = 0x1, DL_SYSCTL_POWER_POLICY_STANDBY1 = 0x2 }

enum	DL_SYSCTL_BOR_THRESHOLD_LEVEL { DL_SYSCTL_BOR_THRESHOLD_LEVEL_0 = SYSCTL_BORTHRESHOLD_LEVEL_BORMIN }

enum	DL_SYSCTL_SHUTDOWN_STORAGE_BYTE { DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_0 = 0x0, DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_1 = 0x1, DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_2 = 0x2, DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_3 = 0x3 }

enum	DL_SYSCTL_RESET_CAUSE { DL_SYSCTL_RESET_CAUSE_NO_RESET = SYSCTL_RSTCAUSE_ID_NORST, DL_SYSCTL_RESET_CAUSE_POR_HW_FAILURE = SYSCTL_RSTCAUSE_ID_PORHWFAIL, DL_SYSCTL_RESET_CAUSE_POR_EXTERNAL_NRST = SYSCTL_RSTCAUSE_ID_POREXNRST, DL_SYSCTL_RESET_CAUSE_POR_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_PORSW, DL_SYSCTL_RESET_CAUSE_BOR_SUPPLY_FAILURE = SYSCTL_RSTCAUSE_ID_BORSUPPLY, DL_SYSCTL_RESET_CAUSE_BOR_WAKE_FROM_SHUTDOWN, DL_SYSCTL_RESET_CAUSE_BOOTRST_NON_PMU_PARITY_FAULT, DL_SYSCTL_RESET_CAUSE_BOOTRST_CLOCK_FAULT = SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL, DL_SYSCTL_RESET_CAUSE_BOOTRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_BOOTSW, DL_SYSCTL_RESET_CAUSE_BOOTRST_EXTERNAL_NRST, DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_EXIT = SYSCTL_RSTCAUSE_ID_SYSBSLEXIT, DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_ENTRY = SYSCTL_RSTCAUSE_ID_SYSBSLENTRY, DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT0_VIOLATION = SYSCTL_RSTCAUSE_ID_SYSWWDT0, DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT1_VIOLATION = SYSCTL_RSTCAUSE_ID_SYSWWDT1, DL_SYSCTL_RESET_CAUSE_SYSRST_FLASH_ECC_ERROR, DL_SYSCTL_RESET_CAUSE_SYSRST_CPU_LOCKUP_VIOLATION, DL_SYSCTL_RESET_CAUSE_SYSRST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSDBG, DL_SYSCTL_RESET_CAUSE_SYSRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSSW, DL_SYSCTL_RESET_CAUSE_CPURST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUDBG, DL_SYSCTL_RESET_CAUSE_CPURST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUSW }

enum	DL_SYSCTL_BEEPER_FREQ { DL_SYSCTL_BEEPER_FREQ_1KHZ = SYSCTL_BEEPCFG_FREQ_1KHZ, DL_SYSCTL_BEEPER_FREQ_2KHZ = SYSCTL_BEEPCFG_FREQ_2KHZ, DL_SYSCTL_BEEPER_FREQ_4KHZ = SYSCTL_BEEPCFG_FREQ_4KHZ, DL_SYSCTL_BEEPER_FREQ_8KHZ = SYSCTL_BEEPCFG_FREQ_8KHZ }

Functions
__STATIC_INLINE void	DL_SYSCTL_enableSleepOnExit (void)
	Enable sleep on exit. More...

__STATIC_INLINE void	DL_SYSCTL_disableSleepOnExit (void)
	Disable sleep on exit. More...

__STATIC_INLINE bool	DL_SYSCTL_isSleepOnExitEnabled (void)
	Check if sleep on exit is enabled.

__STATIC_INLINE void	DL_SYSCTL_enableEventOnPend (void)
	Enable send event on pending bit. More...

__STATIC_INLINE void	DL_SYSCTL_disableEventOnPend (void)
	Disable send event on pending bit. More...

__STATIC_INLINE bool	DL_SYSCTL_isEventOnPendEnabled (void)
	Check if send event on pending bit is enabled. More...

void	DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK (bool disableSYSOSC)
	Change MCLK source from SYSOSC to LFCLK. More...

void	DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC (void)
	Change MCLK source from LFCLK to SYSOSC. More...

void	DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK (void)
	Change MCLK source from SYSOSC to HSCLK. More...

void	DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC (void)
	Change MCLK source from HSCLK to SYSOSC. More...

__STATIC_INLINE void	DL_SYSCTL_setPowerPolicyRUN0SLEEP0 (void)
	Set the RUN/SLEEP mode power policy to RUN0/SLEEP0. More...

__STATIC_INLINE void	DL_SYSCTL_setPowerPolicyRUN1SLEEP1 (void)
	Set the RUN/SLEEP mode power policy to RUN1/SLEEP1. More...

__STATIC_INLINE void	DL_SYSCTL_setPowerPolicyRUN2SLEEP2 (void)
	Set the RUN/SLEEP mode power policy to RUN2/SLEEP2. More...

DL_SYSCTL_POWER_POLICY_RUN_SLEEP	DL_SYSCTL_getPowerPolicyRUNSLEEP (void)
	Get the RUN/SLEEP mode power policy. More...

__STATIC_INLINE void	DL_SYSCTL_setPowerPolicySTOP0 (void)
	Set the STOP mode power policy to STOP0. More...

__STATIC_INLINE void	DL_SYSCTL_setPowerPolicySTOP2 (void)
	Set the STOP mode power policy to STOP2. More...

DL_SYSCTL_POWER_POLICY_STOP	DL_SYSCTL_getPowerPolicySTOP (void)
	Get the STOP mode power policy. More...

__STATIC_INLINE void	DL_SYSCTL_setPowerPolicySTANDBY0 (void)
	Set the STANDBY mode power policy to STANDBY0. More...

__STATIC_INLINE void	DL_SYSCTL_setPowerPolicySTANDBY1 (void)
	Set the STANDBY mode power policy to STANDBY1. More...

DL_SYSCTL_POWER_POLICY_STANDBY	DL_SYSCTL_getPowerPolicySTANDBY (void)
	Get the STANDBY mode power policy. More...

__STATIC_INLINE void	DL_SYSCTL_setPowerPolicySHUTDOWN (void)
	Set power policy to SHUTDOWN mode. More...

__STATIC_INLINE void	DL_SYSCTL_setBORThreshold (DL_SYSCTL_BOR_THRESHOLD_LEVEL thresholdLevel)
	Set the brown-out reset (BOR) threshold level. More...

__STATIC_INLINE DL_SYSCTL_BOR_THRESHOLD_LEVEL	DL_SYSCTL_getBORThreshold (void)
	Get the brown-out reset (BOR) threshold level. More...

__STATIC_INLINE void	DL_SYSCTL_activateBORThreshold (void)
	Activate the BOR threshold level. More...

__STATIC_INLINE void	DL_SYSCTL_resetDevice (uint32_t resetType)
	Resets the device. More...

__STATIC_INLINE void	DL_SYSCTL_enableInterrupt (uint32_t interruptMask)
	Enable SYSCTL interrupts. More...

__STATIC_INLINE void	DL_SYSCTL_disableInterrupt (uint32_t interruptMask)
	Disable SYSCTL interrupts. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_getEnabledInterrupts (uint32_t interruptMask)
	Check which SYSCTL interrupts are enabled. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_getEnabledInterruptStatus (uint32_t interruptMask)
	Check interrupt flag of enabled SYSCTL interrupts. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_getRawInterruptStatus (uint32_t interruptMask)
	Check interrupt flag of any SYSCTL interrupt. More...

__STATIC_INLINE DL_SYSCTL_IIDX	DL_SYSCTL_getPendingInterrupt (void)
	Get highest priority pending SYSCTL interrupt. More...

__STATIC_INLINE void	DL_SYSCTL_clearInterruptStatus (uint32_t interruptMask)
	Clear pending SYSCTL interrupts. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_getRawNonMaskableInterruptStatus (uint32_t interruptMask)
	Check interrupt flag of any SYSCTL non-maskable interrupt. More...

__STATIC_INLINE DL_SYSCTL_NMI_IIDX	DL_SYSCTL_getPendingNonMaskableInterrupt (void)
	Get highest priority pending SYSCTL non-maskable interrupt. More...

__STATIC_INLINE void	DL_SYSCTL_clearNonMaskableInterruptStatus (uint32_t interruptMask)
	Clear pending SYSCTL non-maskable interrupts. More...

__STATIC_INLINE void	DL_SYSCTL_setWWDT0ErrorBehavior (DL_SYSCTL_ERROR_BEHAVIOR behavior)
	Set the behavior when a WWDT0 error occurs. More...

__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR	DL_SYSCTL_getWWDT0ErrorBehavior (void)
	Get the behavior when a WWDT0 error occurs. More...

__STATIC_INLINE void	DL_SYSCTL_setMCLKDivider (DL_SYSCTL_MCLK_DIVIDER divider)
	Set the Main Clock (MCLK) divider (MDIV) More...

__STATIC_INLINE DL_SYSCTL_MCLK_DIVIDER	DL_SYSCTL_getMCLKDivider (void)
	Get the Main Clock (MCLK) divider (MDIV) More...

__STATIC_INLINE DL_SYSCTL_MCLK_SOURCE	DL_SYSCTL_getMCLKSource (void)
	Get the source for the Main Clock (MCLK) More...

__STATIC_INLINE void	DL_SYSCTL_setSYSOSCFreq (DL_SYSCTL_SYSOSC_FREQ freq)
	Set the target frequency of the System Oscillator (SYSOSC) More...

__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ	DL_SYSCTL_getTargetSYSOSCFreq (void)
	Get the target frequency of the System Oscillator (SYSOSC) Target/desired SYSOSC frequency may be different than current/actual SYSOSC frequency during gear shift and other operations. This function matches what is input by DL_SYSCTL_setSYSOSCFreq. More...

__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ	DL_SYSCTL_getCurrentSYSOSCFreq (void)
	Get the current frequency of the System Oscillator (SYSOSC) Current/actual SYSOSC frequency may be different than target/desired SYSOSC frequency during gear shift and other operations. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_getClockStatus (void)
	Returns status of the different clocks in CKM. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_getStatus (void)
	Returns general status of SYSCTL. More...

__STATIC_INLINE void	DL_SYSCTL_clearECCErrorStatus (void)
	Clear the ECC error bits in SYSSTATUS. More...

__STATIC_INLINE void	DL_SYSCTL_setLFCLKSourceEXLF (void)
	Change LFCLK source to external digital LFCLK_IN. More...

__STATIC_INLINE void	DL_SYSCTL_setHFCLKSourceHFCLKIN (void)
	Change HFCLK source to external digital HFCLK_IN. More...

__STATIC_INLINE void	DL_SYSCTL_enableMFCLK (void)
	Enable the Medium Frequency Clock (MFCLK) More...

__STATIC_INLINE void	DL_SYSCTL_disableMFCLK (void)
	Disable the Medium Frequency Clock (MFCLK)

__STATIC_INLINE void	DL_SYSCTL_enableExternalClock (DL_SYSCTL_CLK_OUT_SOURCE source, DL_SYSCTL_CLK_OUT_DIVIDE divider)
	Enable the External Clock (CLK_OUT) More...

__STATIC_INLINE void	DL_SYSCTL_disableExternalClock (void)
	Disable the External Clock (CLK_OUT) More...

__STATIC_INLINE void	DL_SYSCTL_disableExternalClockDivider (void)
	Disable the External Clock (CLK_OUT) Divider. More...

__STATIC_INLINE void	DL_SYSCTL_enableMFPCLK (void)
	Enable the Middle Frequency Precision Clock (MFPCLK) More...

__STATIC_INLINE void	DL_SYSCTL_disableMFPCLK (void)
	Disable the Middle Frequency Precision Clock (MFPCLK) More...

__STATIC_INLINE void	DL_SYSCTL_blockAllAsyncFastClockRequests (void)
	Blocks all asynchronous fast clock requests. More...

__STATIC_INLINE void	DL_SYSCTL_allowAllAsyncFastClockRequests (void)
	Allows all asynchronous fast clock requests. More...

__STATIC_INLINE void	DL_SYSCTL_enableFastCPUEventHandling (void)
	Generates an asynchronous fast clock request upon any IRQ request to CPU. More...

__STATIC_INLINE void	DL_SYSCTL_disableFastCPUEventHandling (void)
	Maintains current system clock speed for IRQ request to CPU. More...

__STATIC_INLINE void	DL_SYSCTL_setSRAMBoundaryAddress (uint32_t address)
	Set the SRAM boundary address to act as partition for read-execute permission. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_getSRAMBoundaryAddress (void)
	Get the SRAM boundary address. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_readFCC (void)
	Read Frequency Clock Counter (FCC) More...

__STATIC_INLINE void	DL_SYSCTL_startFCC (void)
	Start Frequency Clock Counter (FCC) More...

__STATIC_INLINE bool	DL_SYSCTL_isFCCDone (void)
	Returns whether FCC is done capturing. More...

void	DL_SYSCTL_configFCC (DL_SYSCTL_FCC_TRIG_TYPE trigLvl, DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
	Configure the Frequency Clock Counter (FCC) More...

__STATIC_INLINE void	DL_SYSCTL_setFCCPeriods (DL_SYSCTL_FCC_TRIG_CNT periods)
	Sets number of rising-edge to rising-edge period for Frequency Clock Counter (FCC) More...

__STATIC_INLINE DL_SYSCTL_FCC_TRIG_CNT	DL_SYSCTL_getFCCPeriods (void)
	Gets number of rising-edge to rising-edge period for Frequency Clock Counter (FCC) More...

__STATIC_INLINE void	DL_SYSCTL_enableSYSOSCFCL (void)
	Enable Frequency Correction Loop (FCL) in Internal Resistor mode. More...

__STATIC_INLINE void	DL_SYSCTL_enableWriteLock (void)
	Enable write protection of selected SYSCTL registers. More...

__STATIC_INLINE void	DL_SYSCTL_disableWriteLock (void)
	Disable write protection of selected SYSCTL registers. More...

__STATIC_INLINE void	DL_SYSCTL_setVBOOSTConfig (DL_SYSCTL_VBOOST setting)
	Sets operating mode of VBOOST (analog charge pump) More...

__STATIC_INLINE DL_SYSCTL_VBOOST	DL_SYSCTL_getVBOOSTConfig (void)
	Gets operating mode of VBOOST (analog charge pump) More...

__STATIC_INLINE uint8_t	DL_SYSCTL_getShutdownStorageByte (DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index)
	Return byte that was saved through SHUTDOWN. More...

__STATIC_INLINE void	DL_SYSCTL_setShutdownStorageByte (DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index, uint8_t data)
	Save a byte to SHUTDOWN memory. More...

__STATIC_INLINE void	DL_SYSCTL_releaseShutdownIO (void)
	Enable SHUTDOWN IO Release. More...

__STATIC_INLINE void	DL_SYSCTL_disableNRSTPin (void)
	Disable the reset functionality of the NRST pin. More...

__STATIC_INLINE void	DL_SYSCTL_disableSWD (void)
	Disable Serial Wire Debug (SWD) functionality. More...

__STATIC_INLINE DL_SYSCTL_RESET_CAUSE	DL_SYSCTL_getResetCause (void)
	Return byte that is stored in RSTCAUSE. More...

__STATIC_INLINE uint32_t	DL_SYSCTL_getTempCalibrationConstant (void)
	Retrieves the calibration constant of the temperature sensor to be used in temperature calculation. More...

__STATIC_INLINE void	DL_SYSCTL_enableBeeperOutput (void)
	Enable Beeper output. More...

__STATIC_INLINE void	DL_SYSCTL_disableBeeperOutput (void)
	Disable Beeper output.

__STATIC_INLINE void	DL_SYSCTL_setBeeperFreq (DL_SYSCTL_BEEPER_FREQ freq)
	Set the target frequency of the Beeper output. More...

__STATIC_INLINE DL_SYSCTL_BEEPER_FREQ	DL_SYSCTL_getBeeperFreq (void)
	Get the target frequency of the the Beeper output. More...

__STATIC_INLINE bool	DL_SYSCTL_isBeeperEnabled (void)
	Check if Beeper is enabled. More...

__STATIC_INLINE bool	DL_SYSCTL_isFlashBankSwapEnabled (void)
	Checks if Flash Bank swapping is enabled. More...

__STATIC_INLINE bool	DL_SYSCTL_isExecuteFromUpperFlashBank (void)
	Checks if executing from upper flash bank. More...

Detailed Description

Overview

The System Control (SysCtl) module enables control over system wide settings like clocks and power management.

Macro Definition Documentation

§ DL_SYSCTL_setMCLKSource

#define DL_SYSCTL_setMCLKSource	(	current,
		next,
		...
	)	DL_SYSCTL_switchMCLKfrom##current##to##next(__VA_ARGS__);

Change MCLK source.

To ensure good clocking behavior, these are the recommended steps for transition. Valid sources and destinations: LFCLK, SYSOSC, HSCLK

Depending on current MCLK source, steps to switch to next MCLK source can vary. This is a macro that redirects to the different possible transitions.

Only valid for RUN modes. In low power modes, MCLK transitions are handled by hardware.

Note: Different transition APIs may require different input parameters Transitions between LFCLK and HSCLK requires going through SYSOSC.

See also: DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK; DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC; DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK; DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC

Referenced by DL_SYSCTL_setPowerPolicyRUN0SLEEP0(), DL_SYSCTL_setPowerPolicyRUN1SLEEP1(), and DL_SYSCTL_setPowerPolicyRUN2SLEEP2().

Enumeration Type Documentation

§ DL_SYSCTL_IIDX

enum DL_SYSCTL_IIDX

Enumerator
DL_SYSCTL_IIDX_LFOSC_GOOD	Low Frequency Oscillator is stabilized and ready to use.
DL_SYSCTL_IIDX_ANALOG_CLOCK_ERROR	Analog clocking consistency error.

§ DL_SYSCTL_NMI_IIDX

enum DL_SYSCTL_NMI_IIDX

Enumerator
DL_SYSCTL_NMI_IIDX_WWDT0_FAULT	NMI interrupt index for Watchdog 0 Fault.
DL_SYSCTL_NMI_IIDX_BORLVL	NMI interrupt index for early BOR.
DL_SYSCTL_NMI_IIDX_NO_INT	NMI interrupt index for no interrupt pending.

§ DL_SYSCTL_ERROR_BEHAVIOR

enum DL_SYSCTL_ERROR_BEHAVIOR

Enumerator
DL_SYSCTL_ERROR_BEHAVIOR_RESET	The error event will trigger a SYSRST.
DL_SYSCTL_ERROR_BEHAVIOR_NMI	The error event will trigger an NMI.

§ DL_SYSCTL_SYSOSC_FREQ

enum DL_SYSCTL_SYSOSC_FREQ

Enumerator
DL_SYSCTL_SYSOSC_FREQ_4M	Use 4MHz for System Oscillator (SYSOSC)
DL_SYSCTL_SYSOSC_FREQ_BASE	Use BASE (32MHz) for System Oscillator (SYSOSC)
DL_SYSCTL_SYSOSC_FREQ_USERTRIM	User will trim the System Oscillator (SYSOSC) to 16MHz or 24MHz

§ DL_SYSCTL_MCLK_SOURCE

enum DL_SYSCTL_MCLK_SOURCE

Enumerator
DL_SYSCTL_MCLK_SOURCE_SYSOSC	Use System Oscillator (SYSOSC) as MCLK source (default after reset)
DL_SYSCTL_MCLK_SOURCE_HSCLK	Use High Speed Clock (HSCLK) as MCLK source (HFCLK, PLL,...)
DL_SYSCTL_MCLK_SOURCE_LFCLK	Use the Low Frequency Clock (LFCLK) as the clock source

§ DL_SYSCTL_MCLK_DIVIDER

enum DL_SYSCTL_MCLK_DIVIDER

Enumerator
DL_SYSCTL_MCLK_DIVIDER_DISABLE	Disable MCLK divider. Change SYSOSC freq only when MDIV is disabled
DL_SYSCTL_MCLK_DIVIDER_2	Divide MCLK frequency by 2
DL_SYSCTL_MCLK_DIVIDER_3	Divide MCLK frequency by 3
DL_SYSCTL_MCLK_DIVIDER_4	Divide MCLK frequency by 4
DL_SYSCTL_MCLK_DIVIDER_5	Divide MCLK frequency by 5
DL_SYSCTL_MCLK_DIVIDER_6	Divide MCLK frequency by 6
DL_SYSCTL_MCLK_DIVIDER_7	Divide MCLK frequency by 7
DL_SYSCTL_MCLK_DIVIDER_8	Divide MCLK frequency by 8
DL_SYSCTL_MCLK_DIVIDER_9	Divide MCLK frequency by 9
DL_SYSCTL_MCLK_DIVIDER_10	Divide MCLK frequency by 10
DL_SYSCTL_MCLK_DIVIDER_11	Divide MCLK frequency by 11
DL_SYSCTL_MCLK_DIVIDER_12	Divide MCLK frequency by 12
DL_SYSCTL_MCLK_DIVIDER_13	Divide MCLK frequency by 13
DL_SYSCTL_MCLK_DIVIDER_14	Divide MCLK frequency by 14
DL_SYSCTL_MCLK_DIVIDER_15	Divide MCLK frequency by 15
DL_SYSCTL_MCLK_DIVIDER_16	Divide MCLK frequency by 16

§ DL_SYSCTL_CLK_OUT_SOURCE

enum DL_SYSCTL_CLK_OUT_SOURCE

Enumerator
DL_SYSCTL_CLK_OUT_SOURCE_SYSOSC	Use System Oscillator (SYSOSC) as CLK_OUT source
DL_SYSCTL_CLK_OUT_SOURCE_ULPCLK	Use Ultra Low Power Clock (ULPCLK) as CLK_OUT source. DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this configuration.
DL_SYSCTL_CLK_OUT_SOURCE_LFCLK	Use Low Frequency Clock (LFCLK) as CLK_OUT source
DL_SYSCTL_CLK_OUT_SOURCE_MFPCLK	Use Middle Frequency Precision Clock (MFPCLK) as CLK_OUT source. DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this configuration.
DL_SYSCTL_CLK_OUT_SOURCE_HFCLK	Use High Frequency Clock (HFCLK) as CLK_OUT source

§ DL_SYSCTL_CLK_OUT_DIVIDE

enum DL_SYSCTL_CLK_OUT_DIVIDE

Enumerator
DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE	Disable the External Clock (CLK_OUT) output divider
DL_SYSCTL_CLK_OUT_DIVIDE_2	Divide External Clock (CLK_OUT) output by 2
DL_SYSCTL_CLK_OUT_DIVIDE_4	Divide External Clock (CLK_OUT) output by 4
DL_SYSCTL_CLK_OUT_DIVIDE_6	Divide External Clock (CLK_OUT) output by 6
DL_SYSCTL_CLK_OUT_DIVIDE_8	Divide External Clock (CLK_OUT) output by 8
DL_SYSCTL_CLK_OUT_DIVIDE_10	Divide External Clock (CLK_OUT) output by 10
DL_SYSCTL_CLK_OUT_DIVIDE_12	Divide External Clock (CLK_OUT) output by 12
DL_SYSCTL_CLK_OUT_DIVIDE_14	Divide External Clock (CLK_OUT) output by 14
DL_SYSCTL_CLK_OUT_DIVIDE_16	Divide External Clock (CLK_OUT) output by 16

§ DL_SYSCTL_VBOOST

enum DL_SYSCTL_VBOOST

Enumerator
DL_SYSCTL_VBOOST_ONDEMAND	VBOOST enabled only when COMP/OPA/GPAMP is enabled
DL_SYSCTL_VBOOST_ONACTIVE	VBOOST enabled in RUN/SLEEP, and in STOP/STANDBY if COMP/OPA/GPAMP is enabled
DL_SYSCTL_VBOOST_ONALWAYS	VBOOST enabled in all power modes except SHUTDOWN for fastest startup

§ DL_SYSCTL_FCC_TRIG_TYPE

enum DL_SYSCTL_FCC_TRIG_TYPE

Enumerator
DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE	FCC trigger is rising-edge to rising-edge pulse
DL_SYSCTL_FCC_TRIG_TYPE_LEVEL	FCC trigger is active-high pulse level

§ DL_SYSCTL_FCC_TRIG_SOURCE

enum DL_SYSCTL_FCC_TRIG_SOURCE

Enumerator
DL_SYSCTL_FCC_TRIG_SOURCE_FCC_IN	FCC trigger source is FCC_IN external pin
DL_SYSCTL_FCC_TRIG_SOURCE_LFCLK	FCC trigger source is LFCLK

§ DL_SYSCTL_FCC_CLOCK_SOURCE

enum DL_SYSCTL_FCC_CLOCK_SOURCE

Enumerator
DL_SYSCTL_FCC_CLOCK_SOURCE_MCLK	FCC clock source to capture is MCLK
DL_SYSCTL_FCC_CLOCK_SOURCE_SYSOSC	FCC clock source to capture is SYSOSC
DL_SYSCTL_FCC_CLOCK_SOURCE_HFCLK	FCC clock source to capture is HFCLK
DL_SYSCTL_FCC_CLOCK_SOURCE_CLK_OUT	FCC clock source to capture is CLK_OUT
DL_SYSCTL_FCC_CLOCK_SOURCE_FCC_IN	FCC clock source to capture is FCC_IN

§ DL_SYSCTL_FCC_TRIG_CNT

enum DL_SYSCTL_FCC_TRIG_CNT

Enumerator
DL_SYSCTL_FCC_TRIG_CNT_01	One monitoring period
DL_SYSCTL_FCC_TRIG_CNT_02	Two monitoring period
DL_SYSCTL_FCC_TRIG_CNT_03	Three monitoring period
DL_SYSCTL_FCC_TRIG_CNT_04	Four monitoring period
DL_SYSCTL_FCC_TRIG_CNT_05	Five monitoring period
DL_SYSCTL_FCC_TRIG_CNT_06	Six monitoring period
DL_SYSCTL_FCC_TRIG_CNT_07	Seven monitoring period
DL_SYSCTL_FCC_TRIG_CNT_08	Eight monitoring period
DL_SYSCTL_FCC_TRIG_CNT_09	Nine monitoring period
DL_SYSCTL_FCC_TRIG_CNT_10	Ten monitoring period
DL_SYSCTL_FCC_TRIG_CNT_11	Eleven monitoring period
DL_SYSCTL_FCC_TRIG_CNT_12	Twelve monitoring period
DL_SYSCTL_FCC_TRIG_CNT_13	Thirteen monitoring period
DL_SYSCTL_FCC_TRIG_CNT_14	Fourteen monitoring period
DL_SYSCTL_FCC_TRIG_CNT_15	Fifteen monitoring period
DL_SYSCTL_FCC_TRIG_CNT_16	Sixteen monitoring period
DL_SYSCTL_FCC_TRIG_CNT_17	Seventeen monitoring period
DL_SYSCTL_FCC_TRIG_CNT_18	Eighteen monitoring period
DL_SYSCTL_FCC_TRIG_CNT_19	Nineteen monitoring period
DL_SYSCTL_FCC_TRIG_CNT_20	Twenty monitoring period
DL_SYSCTL_FCC_TRIG_CNT_21	Twenty-one monitoring period
DL_SYSCTL_FCC_TRIG_CNT_22	Twenty-two monitoring period
DL_SYSCTL_FCC_TRIG_CNT_23	Twenty-three monitoring period
DL_SYSCTL_FCC_TRIG_CNT_24	Twenty-four monitoring period
DL_SYSCTL_FCC_TRIG_CNT_25	Twenty-five monitoring period
DL_SYSCTL_FCC_TRIG_CNT_26	Twenty-six monitoring period
DL_SYSCTL_FCC_TRIG_CNT_27	Twenty-seven monitoring period
DL_SYSCTL_FCC_TRIG_CNT_28	Twenty-eight monitoring period
DL_SYSCTL_FCC_TRIG_CNT_29	Twenty-nine monitoring period
DL_SYSCTL_FCC_TRIG_CNT_30	Thirty monitoring period
DL_SYSCTL_FCC_TRIG_CNT_31	Thirty-one monitoring period
DL_SYSCTL_FCC_TRIG_CNT_32	Thirty-two monitoring period

§ DL_SYSCTL_POWER_POLICY_RUN_SLEEP

enum DL_SYSCTL_POWER_POLICY_RUN_SLEEP

Enumerator
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED	RUN/SLEEP power policy is not enabled
DL_SYSCTL_POWER_POLICY_RUN_SLEEP0	Enable RUN0/SLEEP0 power mode policy.
DL_SYSCTL_POWER_POLICY_RUN_SLEEP1	Enable the RUN1/SLEEP1 power mode policy
DL_SYSCTL_POWER_POLICY_RUN_SLEEP2	Enable the RUN2/SLEEP2 power mode policy

§ DL_SYSCTL_POWER_POLICY_STOP

enum DL_SYSCTL_POWER_POLICY_STOP

Enumerator
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED	STOP power policy is not enabled
DL_SYSCTL_POWER_POLICY_STOP0	Enable the STOP0 power mode policy
DL_SYSCTL_POWER_POLICY_STOP2	Enable the STOP2 power mode policy

§ DL_SYSCTL_POWER_POLICY_STANDBY

enum DL_SYSCTL_POWER_POLICY_STANDBY

Enumerator
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED	STANDBY power policy is not enabled
DL_SYSCTL_POWER_POLICY_STANDBY0	Enable the STANDBY0 power mode policy
DL_SYSCTL_POWER_POLICY_STANDBY1	Enable the STANDBY1 power mode policy

§ DL_SYSCTL_BOR_THRESHOLD_LEVEL

enum DL_SYSCTL_BOR_THRESHOLD_LEVEL

Enumerator
DL_SYSCTL_BOR_THRESHOLD_LEVEL_0	BOR0 threshold level. This is the minimum allowed threshold. A BOR0- violation will force a re-boot.

§ DL_SYSCTL_SHUTDOWN_STORAGE_BYTE

enum DL_SYSCTL_SHUTDOWN_STORAGE_BYTE

Enumerator
DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_0	Shutdown Storage Byte 0
DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_1	Shutdown Storage Byte 1
DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_2	Shutdown Storage Byte 2
DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_3	Shutdown Storage Byte 3

§ DL_SYSCTL_RESET_CAUSE

enum DL_SYSCTL_RESET_CAUSE

Enumerator
DL_SYSCTL_RESET_CAUSE_NO_RESET	No Reset Since Last Read
DL_SYSCTL_RESET_CAUSE_POR_HW_FAILURE	(VDD < POR- violation) or (PMU trim parity fault) or (SHUTDNSTOREx parity fault)
DL_SYSCTL_RESET_CAUSE_POR_EXTERNAL_NRST	NRST pin reset (>1s)
DL_SYSCTL_RESET_CAUSE_POR_SW_TRIGGERED	Software-triggered POR
DL_SYSCTL_RESET_CAUSE_BOR_SUPPLY_FAILURE	VDD < BOR- violation
DL_SYSCTL_RESET_CAUSE_BOR_WAKE_FROM_SHUTDOWN	Wake from SHUTDOWN
DL_SYSCTL_RESET_CAUSE_BOOTRST_NON_PMU_PARITY_FAULT	Non-PMU trim parity fault
DL_SYSCTL_RESET_CAUSE_BOOTRST_CLOCK_FAULT	Fatal clock fault
DL_SYSCTL_RESET_CAUSE_BOOTRST_SW_TRIGGERED	Software-triggered BOOTRST
DL_SYSCTL_RESET_CAUSE_BOOTRST_EXTERNAL_NRST	NRST pin reset (<1s)
DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_EXIT	BSL exit
DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_ENTRY	BSL entry
DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT0_VIOLATION	WWDT0 violation
DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT1_VIOLATION	WWDT1 violation
DL_SYSCTL_RESET_CAUSE_SYSRST_FLASH_ECC_ERROR	Uncorrectable flash ECC error
DL_SYSCTL_RESET_CAUSE_SYSRST_CPU_LOCKUP_VIOLATION	CPULOCK violation
DL_SYSCTL_RESET_CAUSE_SYSRST_DEBUG_TRIGGERED	Debug-triggered SYSRST
DL_SYSCTL_RESET_CAUSE_SYSRST_SW_TRIGGERED	Software-triggered SYSRST
DL_SYSCTL_RESET_CAUSE_CPURST_DEBUG_TRIGGERED	Debug-triggered CPURST
DL_SYSCTL_RESET_CAUSE_CPURST_SW_TRIGGERED	Software-triggered CPURST

§ DL_SYSCTL_BEEPER_FREQ

enum DL_SYSCTL_BEEPER_FREQ

Enumerator
DL_SYSCTL_BEEPER_FREQ_1KHZ	Use 1KHz for Beeper output
DL_SYSCTL_BEEPER_FREQ_2KHZ	Use 2KHz for Beeper output
DL_SYSCTL_BEEPER_FREQ_4KHZ	Use 4KHz for Beeper output
DL_SYSCTL_BEEPER_FREQ_8KHZ	Use 8KHz for Beeper output

Function Documentation

§ DL_SYSCTL_enableSleepOnExit()

__STATIC_INLINE void DL_SYSCTL_enableSleepOnExit ( void )

Enable sleep on exit.

Enables sleep on exit when the CPU moves from handler mode to thread mode. By enabling, allows an interrupt driven application to avoid returning to an empty main application.

§ DL_SYSCTL_disableSleepOnExit()

__STATIC_INLINE void DL_SYSCTL_disableSleepOnExit ( void )

Disable sleep on exit.

Disables sleep on exit when the CPU moves from handler mode to thread mode.

§ DL_SYSCTL_enableEventOnPend()

__STATIC_INLINE void DL_SYSCTL_enableEventOnPend ( void )

Enable send event on pending bit.

When enabled, any enabled event and all interrupts (including disabled interrupts) can wakeup the processor.

§ DL_SYSCTL_disableEventOnPend()

__STATIC_INLINE void DL_SYSCTL_disableEventOnPend ( void )

Disable send event on pending bit.

When disabled, only enabled interrupts or events can wake up the processor. Disabled interrupts are excluded.

§ DL_SYSCTL_isEventOnPendEnabled()

__STATIC_INLINE bool DL_SYSCTL_isEventOnPendEnabled ( void )

Check if send event on pending bit is enabled.

Returns: Returns the enabled status of the send event on pending bit

Return values

true	Send event on pending bit is enabled
false	Send event on pending bit is disabled

§ DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK()

void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK ( bool disableSYSOSC )

Change MCLK source from SYSOSC to LFCLK.

Precondition: If disabling SYSOSC, high speed oscillators (SYSPLL, HFXT...) must be disabled beforehand.

Postcondition: MCLK source is switched to LFCLK, function will busy-wait until confirmed.

Parameters

[in] disableSYSOSC Whether to leave SYSOSC running or not

§ DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC()

void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC ( void )

Change MCLK source from LFCLK to SYSOSC.

Postcondition: MCLK source is switched to SYSOSC, function will busy-wait until confirmed.

§ DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK()

void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK ( void )

Change MCLK source from SYSOSC to HSCLK.

Precondition: The desired HSCLK source is enabled beforehand (SYSPLL, HFXT, HFCLK_IN).

Postcondition: MCLK source is switched to HSCLK, function will busy-wait until confirmed.

§ DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC()

void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC ( void )

Change MCLK source from HSCLK to SYSOSC.

Precondition: MCLK is sourced from a valid, running HSCLK source (SYSPLL, HFXT, HFCLK_IN)

Postcondition: MCLK source is switched to SYSOSC, function will busy-wait until confirmed.

Note: No HSCLK sources are disabled by this function

§ DL_SYSCTL_setPowerPolicyRUN0SLEEP0()

__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN0SLEEP0 ( void )

Set the RUN/SLEEP mode power policy to RUN0/SLEEP0.

In RUN0, the MCLK and the CPUCLK run from a fast clock source (SYSOSC, HFCLK, or SYSPLL).

Setting the RUN power policy will also set the SLEEP power policy. The SLEEP mode behavior is always identical to RUN mode, just with the CPUCLK disabled. As such, the SLEEP behavior is determined by the configuration of the RUN mode. To actually enter SLEEP mode, you must call __WFI() to wait for interrupts or __WFE() to wait for ARM events. __WFI() is used in interrupt-driven applications, and __WFE() is used for interactions between the interrupt handler and main application.

There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, and RUN2/SLEEP2. Refer to the device TRM for more information on each policy

See also: DL_SYSCTL_setMCLKSource

References DL_SYSCTL_setMCLKSource.

§ DL_SYSCTL_setPowerPolicyRUN1SLEEP1()

__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN1SLEEP1 ( void )

Set the RUN/SLEEP mode power policy to RUN1/SLEEP1.

In RUN1, the MCLK and the CPUCLK run from LFCLK (at 32kHz) to reduce active power, but SYSOSC is left enabled to service analog modules such as an ADC, DAC, OPA, or COMP (in HS mode).

Setting the RUN power policy will also set the SLEEP power policy. The SLEEP mode behavior is always identical to RUN mode, just with the CPUCLK disabled. As such, the SLEEP behavior is determined by the configuration of the RUN mode. To actually enter SLEEP mode, you must call __WFI() to wait for interrupts or __WFE() to wait for ARM events. __WFI() is used in interrupt-driven applications, and __WFE() is used for interactions between the interrupt handler and main application.

There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, and RUN2/SLEEP2. Refer to the device TRM for more information on each policy

See also: DL_SYSCTL_setMCLKSource

References DL_SYSCTL_setMCLKSource.

§ DL_SYSCTL_setPowerPolicyRUN2SLEEP2()

__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN2SLEEP2 ( void )

Set the RUN/SLEEP mode power policy to RUN2/SLEEP2.

In RUN2, the MCLK and the CPUCLK run from LFCLK (at 32kHz), and SYSOSC is completely disabled to save power. This is the lowest power state with the CPU running

Setting the RUN power policy will also set the SLEEP power policy. The SLEEP mode behavior is always identical to RUN mode, just with the CPUCLK disabled. As such, the SLEEP behavior is determined by the configuration of the RUN mode. To actually enter SLEEP mode, you must call __WFI() to wait for interrupts or __WFE() to wait for ARM events. __WFI() is used in interrupt-driven applications, and __WFE() is used for interactions between the interrupt handler and main application.

There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, and RUN2/SLEEP2. Refer to the device TRM for more information on each policy

Note: Since this turns off SYSOSC, HSCLK sources MUST be disabled before calling

See also: DL_SYSCTL_setMCLKSource

References DL_SYSCTL_getPowerPolicyRUNSLEEP(), and DL_SYSCTL_setMCLKSource.

§ DL_SYSCTL_getPowerPolicyRUNSLEEP()

DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP ( void )

Get the RUN/SLEEP mode power policy.

Get which RUN/SLEEP power policy has been set.

The SLEEP mode behavior is always identical to RUN mode, just with the CPUCLK disabled. As such, the SLEEP behavior is determined by the configuration of the RUN mode.

Returns: Returns the current RUN/SLEEP mode power policy

Return values

One	of DL_SYSCTL_POWER_POLICY_RUN_SLEEP

Referenced by DL_SYSCTL_setPowerPolicyRUN2SLEEP2().

§ DL_SYSCTL_setPowerPolicySTOP0()

__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP0 ( void )

Set the STOP mode power policy to STOP0.

In STOP0, the SYSOSC is left running at the current frequency when entering STOP mode (either 32MHz, 24MHz, 16MHz, or 4MHz). ULPCLK is always limited to 4MHz automatically by hardware, but SYSOSC is not disturbed to support consistent operation of analog peripherals such as the ADC, OPA, or COMP.

There are two STOP mode policy options: STOP0 and STOP2. STOP0 should only be entered from RUN0 or SLEEP0. Refer to the device TRM for more information on each policy.

Postcondition: This API does not actually enter STOP mode. After using this API to set the power policy, to enter STOP mode you must call __WFI() to wait for interrupts or __WFE() to wait for ARM events. __WFI() is used in interrupt-driven applications, and __WFE() is used for interactions between the interrupt handler and main application.

§ DL_SYSCTL_setPowerPolicySTOP2()

__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP2 ( void )

Set the STOP mode power policy to STOP2.

In STOP2, the SYSOSC is disabled and the ULPCLK is sourced from LFCLK at 32kHz. This is the lowest power state in STOP mode.

There are two STOP mode policy options: STOP0 and STOP2. STOP2 should only be entered from RUN2 or SLEEP2. Refer to the device TRM for more information on each policy.

Postcondition: This API does not actually enter STOP mode. After using this API to set the power policy, to enter STOP mode you must call __WFI() to wait for interrupts or __WFE() to wait for ARM events. __WFI() is used in interrupt-driven applications, and __WFE() is used for interactions between the interrupt handler and main application.

References DL_SYSCTL_getPowerPolicySTOP().

§ DL_SYSCTL_getPowerPolicySTOP()

DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP ( void )

Get the STOP mode power policy.

Get which STOP power policy has been set.

Returns: Returns the current STOP mode power policy

Return values

One	of DL_SYSCTL_POWER_POLICY_STOP if a STOP power policy

Referenced by DL_SYSCTL_setPowerPolicySTOP2().

§ DL_SYSCTL_setPowerPolicySTANDBY0()

__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY0 ( void )

Set the STANDBY mode power policy to STANDBY0.

In STANDBY0, all PD0 peripherals receive the ULPCLK and LFCLK, and the RTC receives RTCCLK.

There are two STANDBY mode policy options: STANDBY0 and STANDBY1.

Postcondition: This API does not actually enter STANDBY mode. After using this API to set the power policy, to enter STANDBY mode you must call __WFI() to wait for interrupts or __WFE() to wait for ARM events. __WFI() is used in interrupt-driven applications, and __WFE() is used for interactions between the interrupt handler and main application.

§ DL_SYSCTL_setPowerPolicySTANDBY1()

__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY1 ( void )

Set the STANDBY mode power policy to STANDBY1.

In STANDBY1, only TIMG0 and TIMG1 receive ULPCLK/LFCLK. The RTC continues to receive RTCCLK. A TIMG0/1 interrupt, RTC interrupt, or ADC trigger in STANDBY1 always triggers an asynchronous fast clock request to wake the system. Other PD0 peripherals (such as UART, I2C, GPIO, and COMP) can also wake the system upon an external event through an asynchronous fast clock request, but they are not actively clocked in STANDBY1.

There are two STANDBY mode policy options: STANDBY0 and STANDBY1.

Postcondition: This API does not actually enter STANDBY mode. After using this API to set the power policy, to enter STANDBY mode you must call __WFI() to wait for interrupts or __WFE() to wait for ARM events. __WFI() is used in interrupt-driven applications, and __WFE() is used for interactions between the interrupt handler and main application.

References DL_SYSCTL_getPowerPolicySTANDBY().

§ DL_SYSCTL_getPowerPolicySTANDBY()

DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY ( void )

Get the STANDBY mode power policy.

Get which STANDBY power policy has been set.

Returns: Returns the current STANDBY mode power policy

Return values

One	of DL_SYSCTL_POWER_POLICY_STANDBY

Referenced by DL_SYSCTL_setPowerPolicySTANDBY1().

§ DL_SYSCTL_setPowerPolicySHUTDOWN()

__STATIC_INLINE void DL_SYSCTL_setPowerPolicySHUTDOWN ( void )

Set power policy to SHUTDOWN mode.

In SHUTDOWN mode, no clocks are available. The core regulator is completely disabled and all SRAM and register contents are lost, with the exception of the 4 bytes of general purpose memory in SYSCTL which may be used to store state information. The BOR and bandgap circuit are disabled. The device may wake up via a wake-up capable IO, a debug connection, or NRST. SHUTDOWN mode has the lowest current consumption of any operating mode. Exiting SHUTDOWN mode triggers a BOR.

There is only one SHUTDOWN mode policy option: SHUTDOWN.

Postcondition: This API does not actually enter SHUTDOWN mode. After using this API to enable SHUTDOWN mode, to enter SHUTDOWN mode you must call __WFI() to wait for interrupts or __WFE() to wait for ARM events. __WFI() is used in interrupt-driven applications, and __WFE() is used for interactions between the interrupt handler and main application.

§ DL_SYSCTL_setBORThreshold()

__STATIC_INLINE void DL_SYSCTL_setBORThreshold ( DL_SYSCTL_BOR_THRESHOLD_LEVEL thresholdLevel )

Set the brown-out reset (BOR) threshold level.

Note that this API does NOT activate the BOR threshold. After setting the threshold level with this API, call DL_SYSCTL_activateBORThreshold to actually activate the new threshold.

During startup, the BOR threshold defaults to BOR0 (the lowet value) to ensure the device always starts at the specified VDD minimum. After boot, the BOR threshold level can be configured to a different level. When the BOR threshold is BOR0, a BOR0- violation always generates a BOR- violation signal to SYSCTL, generating a BOR level reset. When the BOR threshold is re-configured to BOR1, BOR2, or BOR3 the BOR circuit will generate a SYSCTL interrupt rather than asserting a BOR- violation. This may be used to give the application an indication that the supply has dropped below a certain level without causing a reset. If the BOR is in interrupt mode (threshold level of BOR1-3), and VDD drops below the respective BORx- level, an interrupt will be generated and the BOR circuit will automatically switch the BOR threshold level to BOR0 to ensure that a BOR- violation is asserted if VDD drops below BOR0-.

Parameters

[in] thresholdLevel The BOR threshold level to set. One of DL_SYSCTL_BOR_THRESHOLD_LEVEL.

Postcondition: DL_SYSCTL_activateBORThreshold

§ DL_SYSCTL_getBORThreshold()

__STATIC_INLINE DL_SYSCTL_BOR_THRESHOLD_LEVEL DL_SYSCTL_getBORThreshold ( void )

Get the brown-out reset (BOR) threshold level.

Returns: Returns the current BOR threshold level.

Return values

One	of DL_SYSCTL_BOR_THRESHOLD_LEVEL

§ DL_SYSCTL_activateBORThreshold()

__STATIC_INLINE void DL_SYSCTL_activateBORThreshold ( void )

Activate the BOR threshold level.

Attempts to change the active BOR mode to the BOR threshold that was set via DL_SYSCTL_setBORThreshold.

Setting this bit also clears any prior BOR violation status indications.

After calling this API, the change can be validated by calling DL_SYSCTL_getStatus and checking the return value.

Precondition: DL_SYSCTL_setBORThreshold

§ DL_SYSCTL_resetDevice()

__STATIC_INLINE void DL_SYSCTL_resetDevice ( uint32_t resetType )

Resets the device.

Resets the device using the type of reset selected. This function does not return, the reset will happen immediately.

Parameters

[in] resetType Type of reset to perform. One of DL_SYSCTL_RESET.

§ DL_SYSCTL_enableInterrupt()

__STATIC_INLINE void DL_SYSCTL_enableInterrupt ( uint32_t interruptMask )

Enable SYSCTL interrupts.

Parameters

[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of DL_SYSCTL_INTERRUPT.

§ DL_SYSCTL_disableInterrupt()

__STATIC_INLINE void DL_SYSCTL_disableInterrupt ( uint32_t interruptMask )

Disable SYSCTL interrupts.

Parameters

[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of DL_SYSCTL_INTERRUPT.

§ DL_SYSCTL_getEnabledInterrupts()

__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterrupts ( uint32_t interruptMask )

Check which SYSCTL interrupts are enabled.

Parameters

[in] interruptMask Bit mask of interrupts to check. Bitwise OR of DL_SYSCTL_INTERRUPT.

Returns: Which of the requested SYSCTL interrupts are enabled

Return values

Bitwise OR of DL_SYSCTL_INTERRUPT values

§ DL_SYSCTL_getEnabledInterruptStatus()

__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterruptStatus ( uint32_t interruptMask )

Check interrupt flag of enabled SYSCTL interrupts.

Checks if any of the SYSCTL interrupts that were previously enabled are pending.

Parameters

[in] interruptMask Bit mask of interrupts to check. Bitwise OR of DL_SYSCTL_INTERRUPT.

Returns: Which of the requested SYSCTL interrupts are pending

Return values

Bitwise OR of DL_SYSCTL_INTERRUPT values

See also: DL_SYSCTL_enableInterrupt

§ DL_SYSCTL_getRawInterruptStatus()

__STATIC_INLINE uint32_t DL_SYSCTL_getRawInterruptStatus ( uint32_t interruptMask )

Check interrupt flag of any SYSCTL interrupt.

Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to be previously enabled.

Parameters

[in] interruptMask Bit mask of interrupts to check. Bitwise OR of DL_SYSCTL_INTERRUPT.

Returns: Which of the requested SYSCTL interrupts are pending

Return values

Bitwise OR of DL_SYSCTL_INTERRUPT values

§ DL_SYSCTL_getPendingInterrupt()

__STATIC_INLINE DL_SYSCTL_IIDX DL_SYSCTL_getPendingInterrupt ( void )

Get highest priority pending SYSCTL interrupt.

Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to be previously enabled.

Returns: The highest priority pending SYSCTL interrupt

Return values

One	of DL_SYSCTL_IIDX values

§ DL_SYSCTL_clearInterruptStatus()

__STATIC_INLINE void DL_SYSCTL_clearInterruptStatus ( uint32_t interruptMask )

Clear pending SYSCTL interrupts.

Parameters

[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of DL_SYSCTL_INTERRUPT.

§ DL_SYSCTL_getRawNonMaskableInterruptStatus()

__STATIC_INLINE uint32_t DL_SYSCTL_getRawNonMaskableInterruptStatus ( uint32_t interruptMask )

Check interrupt flag of any SYSCTL non-maskable interrupt.

Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts do not have to be previously enabled.

Parameters

[in] interruptMask Bit mask of interrupts to check. Bitwise OR of DL_SYSCTL_NMI.

Returns: Which of the requested SYSCTL non-maskable interrupts are pending

Return values

Bitwise OR of DL_SYSCTL_NMI values

§ DL_SYSCTL_getPendingNonMaskableInterrupt()

__STATIC_INLINE DL_SYSCTL_NMI_IIDX DL_SYSCTL_getPendingNonMaskableInterrupt ( void )

Get highest priority pending SYSCTL non-maskable interrupt.

Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts do not have to be previously enabled.

Returns: The highest priority pending SYSCTL non-maskable interrupt

Return values

One	of DL_SYSCTL_NMI_IIDX values

§ DL_SYSCTL_clearNonMaskableInterruptStatus()

__STATIC_INLINE void DL_SYSCTL_clearNonMaskableInterruptStatus ( uint32_t interruptMask )

Clear pending SYSCTL non-maskable interrupts.

Parameters

[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of DL_SYSCTL_NMI.

§ DL_SYSCTL_setWWDT0ErrorBehavior()

__STATIC_INLINE void DL_SYSCTL_setWWDT0ErrorBehavior ( DL_SYSCTL_ERROR_BEHAVIOR behavior )

Set the behavior when a WWDT0 error occurs.

Configures whether a WWDT0 error will trigger a BOOTRST or an NMI (non-maskable interrupt). By default, this error will trigger a BOOTRST.

Parameters

[in] behavior The behavior when a Flash ECC DED occurrs

See also: DL_SYSCTL_enableNonMaskableInterrupt

References DL_Common_updateReg().

§ DL_SYSCTL_getWWDT0ErrorBehavior()

__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT0ErrorBehavior ( void )

Get the behavior when a WWDT0 error occurs.

By default, this error will trigger a BOOTRST.

Returns: The behavior when a WWDT0 error occurs

Return values

One	of DL_SYSCTL_ERROR_BEHAVIOR

§ DL_SYSCTL_setMCLKDivider()

__STATIC_INLINE void DL_SYSCTL_setMCLKDivider ( DL_SYSCTL_MCLK_DIVIDER divider )

Set the Main Clock (MCLK) divider (MDIV)

Additionally, can use this function to disable MDIV. MDIV must be disabled before changing SYSOSC frequency.

MDIV is not valid if MCLK source is HSCLK. MDIV is not used if MCLK source if LFCLK.

Parameters

[in] divider Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is HSCLK, a don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC.

References DL_Common_updateReg().

§ DL_SYSCTL_getMCLKDivider()

__STATIC_INLINE DL_SYSCTL_MCLK_DIVIDER DL_SYSCTL_getMCLKDivider ( void )

Get the Main Clock (MCLK) divider (MDIV)

Returns: The value of the Main Clock (MCLK) divider (MDIV)

Return values

Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is HSCLK, a don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC.

§ DL_SYSCTL_getMCLKSource()

__STATIC_INLINE DL_SYSCTL_MCLK_SOURCE DL_SYSCTL_getMCLKSource ( void )

Get the source for the Main Clock (MCLK)

Returns: The source for the Main Clock (MCLK)

Return values

One	of DL_SYSCTL_MCLK_SOURCE

§ DL_SYSCTL_setSYSOSCFreq()

__STATIC_INLINE void DL_SYSCTL_setSYSOSCFreq ( DL_SYSCTL_SYSOSC_FREQ freq )

Set the target frequency of the System Oscillator (SYSOSC)

Target/desired SYSOSC frequency may be different than current/actual SYSOSC frequency during gear shift and other operations.

The System Oscillator (SYSOSC) is an on-chip, accurate, configurable oscillator with factory trimmed support for 32MHz (base frequency) and 4MHz (low frequency) operation.

SYSOSC provides a flexible high-speed clock source for the system in cases where the HFXT is either not present or not used.

MDIV must be disabled before changing SYSOSC freq. See DL_SYSCTL_setMCLKDivider.

Parameters

[in] freq Target frequency to use for the System Oscillator (SYSOSC). DL_SYSCTL_SYSOSC_FREQ_4M or DL_SYSCTL_SYSOSC_FREQ_BASE.

See also: DL_SYSCTL_setMCLKDivider

References DL_Common_updateReg().

§ DL_SYSCTL_getTargetSYSOSCFreq()

__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getTargetSYSOSCFreq ( void )

Get the target frequency of the System Oscillator (SYSOSC) Target/desired SYSOSC frequency may be different than current/actual SYSOSC frequency during gear shift and other operations. This function matches what is input by DL_SYSCTL_setSYSOSCFreq.

Returns: The target frequency of System Oscillator (SYSOSC). One of DL_SYSCTL_SYSOSC_FREQ.

§ DL_SYSCTL_getCurrentSYSOSCFreq()

__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getCurrentSYSOSCFreq ( void )

Get the current frequency of the System Oscillator (SYSOSC) Current/actual SYSOSC frequency may be different than target/desired SYSOSC frequency during gear shift and other operations.

Returns: The current frequency of System Oscillator (SYSOSC). One of DL_SYSCTL_SYSOSC_FREQ.

§ DL_SYSCTL_getClockStatus()

__STATIC_INLINE uint32_t DL_SYSCTL_getClockStatus ( void )

Returns status of the different clocks in CKM.

Returns: Full status of all clock selections

Return values

Bitwise OR of DL_SYSCTL_CLK_STATUS.

Referenced by DL_SYSCTL_isFCCDone().

§ DL_SYSCTL_getStatus()

__STATIC_INLINE uint32_t DL_SYSCTL_getStatus ( void )

Returns general status of SYSCTL.

Returns: Full status of all general conditions in SYSCTL

Return values

Bitwise OR of DL_SYSCTL_STATUS.

§ DL_SYSCTL_clearECCErrorStatus()

__STATIC_INLINE void DL_SYSCTL_clearECCErrorStatus ( void )

Clear the ECC error bits in SYSSTATUS.

The ECC error bits in SYSSTATUS are sticky (they remain set when an ECC error occurs even if future reads do not have errors), and can be cleared through this API.

§ DL_SYSCTL_setLFCLKSourceEXLF()

__STATIC_INLINE void DL_SYSCTL_setLFCLKSourceEXLF ( void )

Change LFCLK source to external digital LFCLK_IN.

LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. Once LFCLK source is changed, the change is locked, LFOSC is disabled to save power, and LFCLK source cannot be selected again without BOR.

LFCLK_IN is a low frequency digital clock input compatible with 32.768kHz typical frequency digital square wave CMOS clock inputs (typical duty cycle of 50%).

Digital clock input must be valid and GPIO/IOMUX must be configured separately on the appropriate pin before calling this function to enable LFCLK_IN.

LFCLK_IN and LFXT are mutually exclusive. This function assumes LFXT is disabled (default).

§ DL_SYSCTL_setHFCLKSourceHFCLKIN()

__STATIC_INLINE void DL_SYSCTL_setHFCLKSourceHFCLKIN ( void )

Change HFCLK source to external digital HFCLK_IN.

HFCLK_IN can be used to bypass the HFXT circuit and bring 4-48MHz typical frequency digital clock into the devce as HFCLK source instead of HFXT.

HFCLK_IN is a digital clock input compatible with digital square wave CMOS clock inputs and should have typical duty cycle of 50%.

Digital clock input must be valid and GPIO/IOMUX must be configured separately on the appropriate pin before calling this function to enable HFCLK_IN.

§ DL_SYSCTL_enableMFCLK()

__STATIC_INLINE void DL_SYSCTL_enableMFCLK ( void )

Enable the Medium Frequency Clock (MFCLK)

MFCLK provides a continuous 4MHz clock to drive certain peripherals on the system. The 4MHz rate is always derived from SYSOSC, and the divider is automatically applied to maintain the 4MHz rate regardless of SYSOSC frequency. MCLK is ideal for timers and serial interfaces which require a constant clock source in RUN/SLEEP/STOP power modes.

MFCLK can only run if 3 conditions are met:

1) Power mode must be RUN, SLEEP, or STOP. 2) USEMFTICK register bit is set, which this function does 3) MDIV must be set to DL_SYSCTL_MCLK_DIVIDER_DISABLE by DL_SYSCTL_setMCLKDivider.

If MCLK source is not SYSOSC, MCLK frequency must be >=32MHz for correct operation of MFCLK.

See also: DL_SYSCTL_setMCLKDivider; DL_SYSCTL_getMCLKSource; DL_SYSCTL_getMCLKFreq

§ DL_SYSCTL_enableExternalClock()

__STATIC_INLINE void DL_SYSCTL_enableExternalClock	(	DL_SYSCTL_CLK_OUT_SOURCE	source,
		DL_SYSCTL_CLK_OUT_DIVIDE	divider
	)

Enable the External Clock (CLK_OUT)

CLK_OUT is provided for pushing out digital clocks to external circuits, such as an external ADC which does not have its own clock source.

IOMUX setting for CLK_OUT must be configured before using this function.

CLK_OUT has a typical duty cycle of 50% if clock source is HFCLK, SYSPLLOUT1, SYSOSC, or LFCLK. If source is MCLK, ULPCLK, or MFCLK, duty cycle is not guaranteed to be 50%.

This function performs multiple operations: 1) Sets the CLK_OUT source 2) Sets the CLK_OUT divider value 3) Enables the CLK_OUT divider, which can be disabled by DL_SYSCTL_disableExternalClockDivider 4) Enables the CLK_OUT, which can be disabled by DL_SYSCTL_disableExternalClock

Parameters

[in]	source	The source of CLK_OUT. One of DL_SYSCTL_CLK_OUT_SOURCE.
[in]	divider	The divider of CLK_OUT. One of DL_SYSCTL_CLK_OUT_DIVIDE.

See also: DL_SYSCTL_disableExternalClock; DL_SYSCTL_disableExternalClockDivider

References DL_Common_updateReg().

§ DL_SYSCTL_disableExternalClock()

__STATIC_INLINE void DL_SYSCTL_disableExternalClock ( void )

Disable the External Clock (CLK_OUT)

See also: DL_SYSCTL_enableExternalClock

§ DL_SYSCTL_disableExternalClockDivider()

__STATIC_INLINE void DL_SYSCTL_disableExternalClockDivider ( void )

Disable the External Clock (CLK_OUT) Divider.

See also: DL_SYSCTL_enableExternalClock

§ DL_SYSCTL_enableMFPCLK()

__STATIC_INLINE void DL_SYSCTL_enableMFPCLK ( void )

Enable the Middle Frequency Precision Clock (MFPCLK)

MFPCLK provides a continuous fixed 4MHz clock to some analog peripherals.

See also: DL_SYSCTL_disableMFPCLK

§ DL_SYSCTL_disableMFPCLK()

__STATIC_INLINE void DL_SYSCTL_disableMFPCLK ( void )

Disable the Middle Frequency Precision Clock (MFPCLK)

See also: DL_SYSCTL_enableMFPCLK

§ DL_SYSCTL_blockAllAsyncFastClockRequests()

__STATIC_INLINE void DL_SYSCTL_blockAllAsyncFastClockRequests ( void )

Blocks all asynchronous fast clock requests.

To block specific async fast clock requests on certain IP, refer to their individual driverlib. Examples include: RTC, UART, SPI, I2C.

§ DL_SYSCTL_allowAllAsyncFastClockRequests()

__STATIC_INLINE void DL_SYSCTL_allowAllAsyncFastClockRequests ( void )

Allows all asynchronous fast clock requests.

Although this allows all async fast clock requests, individual IPs may still be blocking theirs.

To allow specific async fast clock requests on certain IP, refer to their individual driverlib. Examples include: RTC, UART, SPI, I2C, GPIO.

§ DL_SYSCTL_enableFastCPUEventHandling()

__STATIC_INLINE void DL_SYSCTL_enableFastCPUEventHandling ( void )

Generates an asynchronous fast clock request upon any IRQ request to CPU.

Provides lowest latency interrupt handling regardless of system clock speed. Blockable by DL_SYSCTL_blockAllAsyncFastClockRequests

See also: DL_SYSCTL_blockAllAsyncFastClockRequests

§ DL_SYSCTL_disableFastCPUEventHandling()

__STATIC_INLINE void DL_SYSCTL_disableFastCPUEventHandling ( void )

Maintains current system clock speed for IRQ request to CPU.

Latency for interrupt handling will be higher at lower system clock speeds.

§ DL_SYSCTL_setSRAMBoundaryAddress()

__STATIC_INLINE void DL_SYSCTL_setSRAMBoundaryAddress ( uint32_t address )

Set the SRAM boundary address to act as partition for read-execute permission.

Specify the SRAM partition address to protect the code region of SRAM from being written to, and prevent the RW ("data") region of SRAM from being used for code execution. The SRAM partition address creates lower and higher partitions:

Lower partition is Read-Write only, no execute
Upper partition is Read-Execute only, no write A partition address of 0x0 is a special case and indicates that all SRAM is configured with RWX (read-write-execute) permissions. This is the default value.

The address is set with a 32-byte resolution. The address written is the system memory map address of the partition (0x200X_XXXX).

Parameters

[in] address Address to act as the SRAM partition address. Value is a valid 32-bit SRAM address. Only address bits [19:5] i.e. bit 5 to bit 19 are used for the boundary address

§ DL_SYSCTL_getSRAMBoundaryAddress()

__STATIC_INLINE uint32_t DL_SYSCTL_getSRAMBoundaryAddress ( void )

Get the SRAM boundary address.

Get the SRAM partition address The SRAM partition address creates lower and higher partitions:

Lower partition is Read-Write only, no execute
Upper partition is Read-Execute only, no write A partition address of 0x0 is a special case and indicates that all SRAM is configured with RWX (read-write-execute) permissions.

The address is set with a 32-byte granularity. The address written is the system memory map address of the partition (0x200X_XXXX).

Returns: The SRAM partition address offset from the SRAM base address

Return values

Value is range in [0x0, 0x000FFFE0]

§ DL_SYSCTL_readFCC()

__STATIC_INLINE uint32_t DL_SYSCTL_readFCC ( void )

Read Frequency Clock Counter (FCC)

Returns: 22-bit value of Frequency Clock Counter (FCC)

§ DL_SYSCTL_startFCC()

__STATIC_INLINE void DL_SYSCTL_startFCC ( void )

Start Frequency Clock Counter (FCC)

If FCC_IN is already logic high, counting starts immediately. When using level trigger, FCC_IN should be low when GO is set, and trigger pulse should be sent to FCC_IN after starting FCC.

§ DL_SYSCTL_isFCCDone()

__STATIC_INLINE bool DL_SYSCTL_isFCCDone ( void )

Returns whether FCC is done capturing.

When capture completes, FCCDONE is set by hardware. FCCDONE is read-only and is automatically cleared by hardware when a new capture is started.

Returns: Whether FCC is done or not

Return values

true	or false (boolean)

References DL_SYSCTL_configFCC(), and DL_SYSCTL_getClockStatus().

§ DL_SYSCTL_configFCC()

void DL_SYSCTL_configFCC	(	DL_SYSCTL_FCC_TRIG_TYPE	trigLvl,
		DL_SYSCTL_FCC_TRIG_SOURCE	trigSrc,
		DL_SYSCTL_FCC_CLOCK_SOURCE	clkSrc
	)

Configure the Frequency Clock Counter (FCC)

FCC enables flexible in-system testing and calibration of a variety of oscillators and clocks on the device. The FCC counts the number of clock periods seen on the selected clock source within a known fixed trigger period (derived from a secondary reference source) to provide an estimation of the frequency of the source clock.

Parameters

[in]	trigLvl	Determines if active high level trigger or rising-edge to rising-edge. One of DL_SYSCTL_FCC_TRIG_TYPE .
[in]	trigSrc	Determines which clock source to trigger FCC from. One of DL_SYSCTL_FCC_TRIG_SOURCE.
[in]	clkSrc	Which clock source to capture and measure frequency of. One of DL_SYSCTL_FCC_CLOCK_SOURCE.

Referenced by DL_SYSCTL_isFCCDone().

§ DL_SYSCTL_setFCCPeriods()

__STATIC_INLINE void DL_SYSCTL_setFCCPeriods ( DL_SYSCTL_FCC_TRIG_CNT periods )

Sets number of rising-edge to rising-edge period for Frequency Clock Counter (FCC)

Set the number of rising-edge to rising-edge period for Frequency Clock Counter (FCC)

Parameters

[in] periods One of DL_SYSCTL_FCC_TRIG_CNT

References DL_Common_updateReg().

§ DL_SYSCTL_getFCCPeriods()

__STATIC_INLINE DL_SYSCTL_FCC_TRIG_CNT DL_SYSCTL_getFCCPeriods ( void )

Gets number of rising-edge to rising-edge period for Frequency Clock Counter (FCC)

Returns: One of DL_SYSCTL_FCC_TRIG_CNT

§ DL_SYSCTL_enableSYSOSCFCL()

__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL ( void )

Enable Frequency Correction Loop (FCL) in Internal Resistor mode.

Once FCL is enable, it cannot be disabled by software. A BOOTRST is required.

§ DL_SYSCTL_enableWriteLock()

__STATIC_INLINE void DL_SYSCTL_enableWriteLock ( void )

Enable write protection of selected SYSCTL registers.

Protecting writes to configuration registers in SYSCTL can add a layer of robustness against unintended changes during runtime.

Note: Does not protect all SYSCTL registers, see TRM for more detail.

§ DL_SYSCTL_disableWriteLock()

__STATIC_INLINE void DL_SYSCTL_disableWriteLock ( void )

Disable write protection of selected SYSCTL registers.

Protecting writes to configuration registers in SYSCTL can add a layer of robustness against unintended changes during runtime.

Note: Does not protect all SYSCTL registers, see TRM for more detail.

§ DL_SYSCTL_setVBOOSTConfig()

__STATIC_INLINE void DL_SYSCTL_setVBOOSTConfig ( DL_SYSCTL_VBOOST setting )

Sets operating mode of VBOOST (analog charge pump)

Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). VBOOST has a startup time, so consider power consumption versus desired startup time.

Note: Although VBOOST clock source is automatically managed, it is up to application software to ensure certain cases, or else ANACLKERR occurs. See VBOOST section of TRM for more details.

Parameters

[in] setting One of DL_SYSCTL_VBOOST.

References DL_Common_updateReg().

§ DL_SYSCTL_getVBOOSTConfig()

__STATIC_INLINE DL_SYSCTL_VBOOST DL_SYSCTL_getVBOOSTConfig ( void )

Gets operating mode of VBOOST (analog charge pump)

Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). VBOOST has a startup time, so consider power consumption versus desired startup time.

Note: Although VBOOST clock source is automatically managed, it is up to application software to ensure certain cases, or else ANACLKERR occurs. See VBOOST section of TRM for more details.

Returns: One of DL_SYSCTL_VBOOST.

§ DL_SYSCTL_getShutdownStorageByte()

__STATIC_INLINE uint8_t DL_SYSCTL_getShutdownStorageByte ( DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index )

Return byte that was saved through SHUTDOWN.

Shutdown memory persists beyond BOR, BOOTRST, and SYSRST.

Note: Parity bits and parity fault checking is done by hardware.

Parameters

[in] index One of DL_SYSCTL_SHUTDOWN_STORAGE_BYTE.

Returns: 8-bit value of Shutdown Storage Byte.

§ DL_SYSCTL_setShutdownStorageByte()

__STATIC_INLINE void DL_SYSCTL_setShutdownStorageByte	(	DL_SYSCTL_SHUTDOWN_STORAGE_BYTE	index,
		uint8_t	data
	)

Save a byte to SHUTDOWN memory.

Shutdown memory persists beyond BOR, BOOTRST, and SYSRST.

Note: Parity bits and parity fault checking is done by hardware.

Parameters

[in]	index	One of DL_SYSCTL_SHUTDOWN_STORAGE_BYTE.
[in]	data	8-bit data to save in memory

References DL_Common_updateReg().

§ DL_SYSCTL_releaseShutdownIO()

__STATIC_INLINE void DL_SYSCTL_releaseShutdownIO ( void )

Enable SHUTDOWN IO Release.

After shutdown, IO is locked in previous state.

Note: Release IO after re-configuring IO to their proper state.

§ DL_SYSCTL_disableNRSTPin()

__STATIC_INLINE void DL_SYSCTL_disableNRSTPin ( void )

Disable the reset functionality of the NRST pin.

Disabling the NRST pin allows the pin to be configured as a GPIO. Once disabled, the reset functionality can only be re-enabled by a POR.

Note: The register is write-only, so the EXRSTPIN register will always appear as "Disabled" in the debugger

§ DL_SYSCTL_disableSWD()

__STATIC_INLINE void DL_SYSCTL_disableSWD ( void )

Disable Serial Wire Debug (SWD) functionality.

SWD pins are enabled by default after cold start to allow a debug connection. It is possible to disable SWD on these pins to use for other functionality.

Postcondition: SWD is disabled, but pins must be re-configured separately.

Note: Cannot debug the device after disabling SWD. Only re-enabled by POR.

§ DL_SYSCTL_getResetCause()

__STATIC_INLINE DL_SYSCTL_RESET_CAUSE DL_SYSCTL_getResetCause ( void )

Return byte that is stored in RSTCAUSE.

Returns: The cause of reset. One of DL_SYSCTL_RESET_CAUSE

§ DL_SYSCTL_getTempCalibrationConstant()

__STATIC_INLINE uint32_t DL_SYSCTL_getTempCalibrationConstant ( void )

Retrieves the calibration constant of the temperature sensor to be used in temperature calculation.

Return values

Temperature sensor calibration data

References DL_FactoryRegion_getTemperatureVoltage().

§ DL_SYSCTL_enableBeeperOutput()

__STATIC_INLINE void DL_SYSCTL_enableBeeperOutput ( void )

Enable Beeper output.

The Beeper function can be used to generate a square wave output to external beepers. The frequency of the Beeper output can be configued by calling DL_SYSCTL_setBeeperFreq

§ DL_SYSCTL_setBeeperFreq()

__STATIC_INLINE void DL_SYSCTL_setBeeperFreq ( DL_SYSCTL_BEEPER_FREQ freq )

Set the target frequency of the Beeper output.

Parameters

[in] freq Target frequency to use for the Beeper output. One of DL_SYSCTL_BEEPER_FREQ.

References DL_Common_updateReg().

§ DL_SYSCTL_getBeeperFreq()

__STATIC_INLINE DL_SYSCTL_BEEPER_FREQ DL_SYSCTL_getBeeperFreq ( void )

Get the target frequency of the the Beeper output.

Returns: Returns the target frequency of the Beeper output.

Return values

One	of DL_SYSCTL_BEEPER_FREQ.

§ DL_SYSCTL_isBeeperEnabled()

__STATIC_INLINE bool DL_SYSCTL_isBeeperEnabled ( void )

Check if Beeper is enabled.

Returns: Returns the enabled status of the Beeper output

Return values

true	The Beeper output is enabled
false	The Beeper output is disabled

§ DL_SYSCTL_isFlashBankSwapEnabled()

__STATIC_INLINE bool DL_SYSCTL_isFlashBankSwapEnabled ( void )

Checks if Flash Bank swapping is enabled.

Returns: Whether Flash Bank swap is enabled

Return values

false This is not a multi-bank device

§ DL_SYSCTL_isExecuteFromUpperFlashBank()

__STATIC_INLINE bool DL_SYSCTL_isExecuteFromUpperFlashBank ( void )

Checks if executing from upper flash bank.

Returns: Whether executing from upper flash bank

Return values

false This is not a multi-bank device.

Modules

Macros

Enumerations

Functions

Detailed Description

Overview

Macro Definition Documentation

§ DL_SYSCTL_setMCLKSource

Enumeration Type Documentation

§ DL_SYSCTL_IIDX

§ DL_SYSCTL_NMI_IIDX

§ DL_SYSCTL_ERROR_BEHAVIOR

§ DL_SYSCTL_SYSOSC_FREQ

§ DL_SYSCTL_MCLK_SOURCE

§ DL_SYSCTL_MCLK_DIVIDER

§ DL_SYSCTL_CLK_OUT_SOURCE

§ DL_SYSCTL_CLK_OUT_DIVIDE

§ DL_SYSCTL_VBOOST

§ DL_SYSCTL_FCC_TRIG_TYPE

§ DL_SYSCTL_FCC_TRIG_SOURCE

§ DL_SYSCTL_FCC_CLOCK_SOURCE

§ DL_SYSCTL_FCC_TRIG_CNT

§ DL_SYSCTL_POWER_POLICY_RUN_SLEEP

§ DL_SYSCTL_POWER_POLICY_STOP

§ DL_SYSCTL_POWER_POLICY_STANDBY

§ DL_SYSCTL_BOR_THRESHOLD_LEVEL

§ DL_SYSCTL_SHUTDOWN_STORAGE_BYTE

§ DL_SYSCTL_RESET_CAUSE

§ DL_SYSCTL_BEEPER_FREQ

Function Documentation

§ DL_SYSCTL_enableSleepOnExit()

§ DL_SYSCTL_disableSleepOnExit()

§ DL_SYSCTL_enableEventOnPend()

§ DL_SYSCTL_disableEventOnPend()

§ DL_SYSCTL_isEventOnPendEnabled()

§ DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK()

§ DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC()

§ DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK()

§ DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC()

§ DL_SYSCTL_setPowerPolicyRUN0SLEEP0()

§ DL_SYSCTL_setPowerPolicyRUN1SLEEP1()

§ DL_SYSCTL_setPowerPolicyRUN2SLEEP2()

§ DL_SYSCTL_getPowerPolicyRUNSLEEP()

§ DL_SYSCTL_setPowerPolicySTOP0()

§ DL_SYSCTL_setPowerPolicySTOP2()

§ DL_SYSCTL_getPowerPolicySTOP()

§ DL_SYSCTL_setPowerPolicySTANDBY0()

§ DL_SYSCTL_setPowerPolicySTANDBY1()

§ DL_SYSCTL_getPowerPolicySTANDBY()

§ DL_SYSCTL_setPowerPolicySHUTDOWN()

§ DL_SYSCTL_setBORThreshold()

§ DL_SYSCTL_getBORThreshold()

§ DL_SYSCTL_activateBORThreshold()

§ DL_SYSCTL_resetDevice()

§ DL_SYSCTL_enableInterrupt()

§ DL_SYSCTL_disableInterrupt()

§ DL_SYSCTL_getEnabledInterrupts()

§ DL_SYSCTL_getEnabledInterruptStatus()

§ DL_SYSCTL_getRawInterruptStatus()

§ DL_SYSCTL_getPendingInterrupt()

§ DL_SYSCTL_clearInterruptStatus()

§ DL_SYSCTL_getRawNonMaskableInterruptStatus()

§ DL_SYSCTL_getPendingNonMaskableInterrupt()

§ DL_SYSCTL_clearNonMaskableInterruptStatus()

§ DL_SYSCTL_setWWDT0ErrorBehavior()

§ DL_SYSCTL_getWWDT0ErrorBehavior()

§ DL_SYSCTL_setMCLKDivider()

§ DL_SYSCTL_getMCLKDivider()

§ DL_SYSCTL_getMCLKSource()

§ DL_SYSCTL_setSYSOSCFreq()

§ DL_SYSCTL_getTargetSYSOSCFreq()

§ DL_SYSCTL_getCurrentSYSOSCFreq()

§ DL_SYSCTL_getClockStatus()

§ DL_SYSCTL_getStatus()

§ DL_SYSCTL_clearECCErrorStatus()

§ DL_SYSCTL_setLFCLKSourceEXLF()

§ DL_SYSCTL_setHFCLKSourceHFCLKIN()

§ DL_SYSCTL_enableMFCLK()

§ DL_SYSCTL_enableExternalClock()

§ DL_SYSCTL_disableExternalClock()