[sys_ctrl.h] System Control

Functions
static uint32_t	SysCtrlClockGet (void)
	Get the CPU core clock frequency. More...
static void	SysCtrlAonSync (void)
	Sync all accesses to the AON register interface. More...
static void	SysCtrlAonUpdate (void)
	Update all interfaces to AON. More...
void	SysCtrlSetRechargeBeforePowerDown (uint32_t xoscPowerMode)
	Set Recharge values before entering Power Down. More...
void	SysCtrlAdjustRechargeAfterPowerDown (uint32_t vddrRechargeMargin)
	Adjust Recharge calculations to be used next. More...
void	SysCtrl_DCDC_VoltageConditionalControl (void)
	Turns DCDC on or off depending of what is considered to be optimal usage. More...
uint32_t	SysCtrlResetSourceGet (void)
	Returns the reset source (including "wakeup from shutdown"). More...
static void	SysCtrlSystemReset (void)
	Perform a full system reset. More...
static void	SysCtrlClockLossResetEnable (void)
	Enables reset if OSC clock loss event is asserted. More...
static void	SysCtrlClockLossResetDisable (void)
	Disables reset due to OSC clock loss event. More...
#define	RSTSRC_PWR_ON   (( AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_PIN_RESET   (( AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_VDDS_LOSS   (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_VDDR_LOSS   (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_CLK_LOSS   (( AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_SYSRESET   (( AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_WARMRESET   (( AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_WAKEUP_FROM_SHUTDOWN   ((( AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) + 1 )

Detailed Description

Function Documentation

void SysCtrl_DCDC_VoltageConditionalControl

(

void

)

Turns DCDC on or off depending of what is considered to be optimal usage.

This function controls the DCDC only if both the following CCFG settings are true:

• DCDC is configured to be used.
• Alternative DCDC settings are defined and enabled.

The DCDC is configured in accordance to the CCFG settings when turned on.

This function should be called periodically.

Returns

None

{
   uint32_t batThreshold     ;  // Fractional format with 8 fractional bits.
   uint32_t aonBatmonBat     ;  // Fractional format with 8 fractional bits.
   uint32_t ccfg_ModeConfReg ;  // Holds a copy of the CCFG_O_MODE_CONF register.
   uint32_t aonSysctlPwrctl  ;  // Reflect whats read/written to the AON_SYSCTL_O_PWRCTL register.

   // We could potentially call this function before any battery voltage measurement
   // is made/available. In that case we must make sure that we do not turn off the DCDC.
   // This can be done by doing nothing as long as the battery voltage is 0 (Since the
   // reset value of the battery voltage register is 0).
   aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT );
   if ( aonBatmonBat != 0 ) {
      // Check if Voltage Conditional Control is enabled
      // It is enabled if all the following are true:
      // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero).
      // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 )
      // - Not in external regulator mode ( EXT_REG_MODE == 0 )
      ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );

      if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0                                            ) ||
           (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M   ) == 0                                            )    ) &&
          (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE )               == 0      ) &&
          (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0      )    )
      {
         aonSysctlPwrctl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL );
         batThreshold    = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) &
            CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >>
            CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 );

         if ( aonSysctlPwrctl & ( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M )) {
            // DCDC is ON, check if it should be switched off
            if ( aonBatmonBat < batThreshold ) {
               aonSysctlPwrctl &= ~( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M );

               HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl;
            }
         } else {
            // DCDC is OFF, check if it should be switched on
            if ( aonBatmonBat > batThreshold ) {
               if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_EN_M     ;
               if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M   ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ;

               HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl;
            }
         }
      }
   }
}

void SysCtrlAdjustRechargeAfterPowerDown

(

uint32_t

vddrRechargeMargin

)

Adjust Recharge calculations to be used next.

This function shall be called just after returning from Power Down.

Reads the results from the adaptive recharge controller and current chip temperature. This is used as additional information when calculating optimal recharge controller settings next time (When SysCtrlSetRechargeBeforePowerDown() is called next time).

Parameters

vddrRechargeMargin

margin in SCLK_LF periods to subtract from previous longest recharge period experienced while in standby.

Note

Special care must be taken to make sure that the AON registers read are updated after the wakeup. Writing to an AON register and then calling SysCtrlAonSync() will handle this.

Returns

None

{
   int32_t     curTemp                 ;
   uint32_t    longestRechargePeriod   ;
   uint32_t    deltaTime               ;
   uint32_t    newRechargePeriod       ;

   //--- Spec. point 2 ---
   longestRechargePeriod = ( HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) &
      AON_WUC_RECHARGESTAT_MAX_USED_PER_M ) >>
      AON_WUC_RECHARGESTAT_MAX_USED_PER_S ;

   if ( longestRechargePeriod != 0 ) {
      //--- Spec. changed (originally point 1) ---
      curTemp = AONBatMonTemperatureGetDegC();
      if ( curTemp < powerQualGlobals.pdTemp ) {
         if ( curTemp < -128 ) {
            curTemp = -128;
         }
         powerQualGlobals.pdTemp = curTemp;
      }

      // Add some margin between the longest previous recharge period and the
      // next initial recharge period. Since it is a fixed margin, it will have a
      // higher impact as a fraction of the converged recharge period at higher temperatures
      // where it is needed more due to higher leakage.
      if (longestRechargePeriod > vddrRechargeMargin) {
         longestRechargePeriod -= vddrRechargeMargin;
      }
      else {
         longestRechargePeriod = 1;
      }

      //--- Spec. point 4 ---
      if ( longestRechargePeriod < powerQualGlobals.pdRechargePeriod ) {
         powerQualGlobals.pdRechargePeriod = longestRechargePeriod;
      } else {
         //--- Spec. point 5 ---
         deltaTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ) - powerQualGlobals.pdTime + 2;
         if ( deltaTime > 31 ) {
            deltaTime = 31;
         }
         newRechargePeriod = powerQualGlobals.pdRechargePeriod + (( longestRechargePeriod - powerQualGlobals.pdRechargePeriod ) >> (deltaTime>>1));
         if ( newRechargePeriod > 0xFFFF ) {
            newRechargePeriod = 0xFFFF;
         }
         powerQualGlobals.pdRechargePeriod = newRechargePeriod;
      }
   }
}

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static void SysCtrlAonSync ( void  )

inlinestatic

Sync all accesses to the AON register interface.

When this function returns, all writes to the AON register interface are guaranteed to have propagated to hardware. The function will return immediately if no AON writes are pending; otherwise, it will wait for the next AON clock before returning.

Returns

None

See also

SysCtrlAonUpdate()

Referenced by SetupAfterColdResetWakeupFromShutDownCfg3().

{
    // Sync the AON interface
    HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
}

static void SysCtrlAonUpdate ( void  )

inlinestatic

Update all interfaces to AON.

When this function returns, at least 1 clock cycle has progressed on the AON domain, so that any outstanding updates to and from the AON interface is guaranteed to be in sync.

Note

This function should primarily be used after wakeup from sleep modes, as it will guarantee that all shadow registers on the AON interface are updated before reading any AON registers from the MCU domain. If a write has been done to the AON interface it is sufficient to call the SysCtrlAonSync().

Returns

None

See also

SysCtrlAonSync()

{
    // Force a clock cycle on the AON interface to guarantee all registers are
    // in sync.
    HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1;
    HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
}

static uint32_t SysCtrlClockGet ( void  )

inlinestatic

Get the CPU core clock frequency.

Use this function to get the current clock frequency for the CPU.

The CPU can run from 48 MHz and down to 750kHz. The frequency is defined by the combined division factor of the SYSBUS and the CPU clock divider.

Returns

Returns the current CPU core clock frequency.

{
    // Return fixed clock speed
    return( GET_MCU_CLOCK );
}

static void SysCtrlClockLossResetDisable ( void  )

inlinestatic

Disables reset due to OSC clock loss event.

Note

This function shall typically not be called because the clock loss reset functionality is controlled by the boot code (a factory configuration defines whether it is set or not).

Returns

None

See also

SysCtrlClockLossResetEnable()

{
    // Clear clock loss enable bit in AON_SYSCTRL using bit banding
    HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0;
}

static void SysCtrlClockLossResetEnable ( void  )

inlinestatic

Enables reset if OSC clock loss event is asserted.

Clock loss circuit in analog domain must be enabled as well in order to actually enable for a clock loss reset to occur OSCClockLossEventEnable().

Note

This function shall typically not be called because the clock loss reset functionality is controlled by the boot code (a factory configuration defines whether it is set or not).

Returns

None

See also

SysCtrlClockLossResetDisable(), OSCClockLossEventEnable()

{
    // Set clock loss enable bit in AON_SYSCTRL using bit banding
    HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1;
}

uint32_t SysCtrlResetSourceGet

(

void

)

Returns the reset source (including "wakeup from shutdown").

In case of RSTSRC_WAKEUP_FROM_SHUTDOWN the application is responsible for unlatching the outputs (disable pad sleep). See PowerCtrlPadSleepDisable() for more information.

Returns

Returns the reset source.

• RSTSRC_PWR_ON
• RSTSRC_PIN_RESET
• RSTSRC_VDDS_LOSS
• RSTSRC_VDDR_LOSS
• RSTSRC_CLK_LOSS
• RSTSRC_SYSRESET
• RSTSRC_WARMRESET
• RSTSRC_WAKEUP_FROM_SHUTDOWN

{
   uint32_t aonSysctlResetCtl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL );

   if ( aonSysctlResetCtl & AON_SYSCTL_RESETCTL_WU_FROM_SD_M ) {
      return ( RSTSRC_WAKEUP_FROM_SHUTDOWN );
   } else {
      return (( aonSysctlResetCtl & AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> AON_SYSCTL_RESETCTL_RESET_SRC_S ) ;
   }
}

void SysCtrlSetRechargeBeforePowerDown

(

uint32_t

xoscPowerMode

)

Set Recharge values before entering Power Down.

This function shall be called just before entering Power Down. It calculates an optimal and safe recharge setting of the adaptive recharge controller. The results of previous setting are also taken into account.

Note

In order to make sure that the register writes are completed, SysCtrlAonSync() must be called before entering standby/power down. This is not done internally in this function due to two reasons:

• 1) There might be other register writes that must be synchronized as well.
• 2) It is possible to save some time by doing other things before calling SysCtrlAonSync() since this call will not return before there are no outstanding write requests between MCU and AON.

Parameters

xoscPowerMode

(typically running in XOSC_IN_HIGH_POWER_MODE all the time). XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC. XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC.

Returns

None

{
   int32_t           curTemp                 ;
   int32_t           shiftedTemp             ;
   int32_t           deltaVddrSleepTrim      ;
   int32_t           vddrTrimSleep           ;
   int32_t           vddrTrimActve           ;
   int32_t           diffVddrActiveSleep     ;
   uint32_t          ccfg_ModeConfReg        ;
   uint32_t          curState                ;
   uint32_t          prcmRamRetention        ;
   uint32_t          di                      ;
   uint32_t          dii                     ;
   uint32_t          ti                      ;
   uint32_t          cd                      ;
   uint32_t          cl                      ;
   uint32_t          load                    ;
   uint32_t          k                       ;
   uint32_t          vddrCap                 ;
   uint32_t          newRechargePeriod       ;
   uint32_t          perE                    ;
   uint32_t          perM                    ;
   const uint32_t  * pLookupTable            ;

   // If external regulator mode we shall:
   // - Disable adaptive recharge (bit[31]=0) in AON_WUC_O_RECHARGECFG
   // - Set recharge period to approximately 500 mS (perM=31, perE=5 => 0xFD)
   // - Make sure you get a recalculation if leaving external regulator mode by setting powerQualGlobals.pdState accordingly
   if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) {
      powerQualGlobals.pdState = PD_STATE_EXT_REG_MODE;
      HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG  ) = 0x00A4FDFD;
      return;
   }

   //--- Spec. point 1 ---
   curTemp  = AONBatMonTemperatureGetDegC();
   curState = 0;

   // read the MODE_CONF register in CCFG
   ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
   // Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended)
   deltaVddrSleepTrim = ((((int32_t) ccfg_ModeConfReg )
      << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ))
      >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1;
   // Do temperature compensation if enabled
   if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) {
      int32_t tcDelta = ( 62 - curTemp ) >> 3;
      if ( tcDelta > 8 ) tcDelta = 8;
      if ( tcDelta > deltaVddrSleepTrim ) deltaVddrSleepTrim = tcDelta;
   }
   if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD  ) == 0 ) &&
       (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 )    )
   {
      vddrTrimSleep = SetupSignExtendVddrTrimValue((
         HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
         FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M ) >>
         FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S ) ;
      vddrTrimActve = SetupSignExtendVddrTrimValue((
         HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
         FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >>
         FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ;
   } else
   {
      vddrTrimSleep = SetupSignExtendVddrTrimValue((
         HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) &
         FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >>
         FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ;
      vddrTrimActve = SetupSignExtendVddrTrimValue((
         HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM ) &
         FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >>
         FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ;
   }
   vddrTrimSleep += deltaVddrSleepTrim;
   if ( vddrTrimSleep >  21 ) vddrTrimSleep =  21;
   if ( vddrTrimSleep < -10 ) vddrTrimSleep = -10;
   // Write adjusted value using MASKED write (MASK8)
   HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) |
      (( vddrTrimSleep << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M ));

   prcmRamRetention = HWREG( PRCM_BASE + PRCM_O_RAMRETEN );
   if ( prcmRamRetention & PRCM_RAMRETEN_VIMS_M ) {
      curState |= PD_STATE_CACHE_RET;
   }
   if ( prcmRamRetention & PRCM_RAMRETEN_RFC ) {
      curState |= PD_STATE_RFMEM_RET;
   }
   if ( xoscPowerMode != XOSC_IN_HIGH_POWER_MODE ) {
      curState |= PD_STATE_XOSC_LPM;
   }

   //--- Spec. point 2 ---
   if ((( curTemp - powerQualGlobals.pdTemp ) >= 5 ) || ( curState != powerQualGlobals.pdState )) {
      //--- Spec. point 3 ---
      shiftedTemp = curTemp - 15;

      //--- Spec point 4 ---
      //4. Check for external VDDR load option (may not be supported): ext_load = (VDDR_EXT_LOAD=0 in CCFG)
      // Currently not implementing external load handling
      // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) {
      // }

      pLookupTable = (uint32_t *)( FCFG1_BASE + FCFG1_O_PWD_CURR_20C );

      //--- Spec point 5 ---
      di    = 0;
      ti    = 0;
      if ( shiftedTemp >= 0 ) {
         //--- Spec point 5.a ---
         shiftedTemp += ( shiftedTemp << 4 );

         //--- Spec point 5.b ---
         ti = ( shiftedTemp >> 8 );
         if ( ti > 7 ) {
            ti = 7;
         }
         dii = ti;
         if ( dii > 6 ) {
            dii = 6;
         }

         //--- Spec point 5.c ---
         cd = pLookupTable[ dii + 1 ] - pLookupTable[ dii ];

         //--- Spec point 5.d ---
         di = cd & 0xFF;

         //--- Spec point 5.e ---
         if ( curState & PD_STATE_XOSC_LPM ) {
            di += (( cd >> 8 ) & 0xFF );
         }
         if ( curState & PD_STATE_RFMEM_RET ) {
            di += (( cd >> 16 ) & 0xFF );
         }
         if ( curState & PD_STATE_CACHE_RET ) {
            di += (( cd >> 24 ) & 0xFF );
         }

         //--- Spec point 5.f ---
         // Currently not implementing external load handling
      }

      //--- Spec. point 6 ---
      cl = pLookupTable[ ti ];

      //--- Spec. point 7 ---
      load = cl & 0xFF;

      //--- Spec. point 8 ---
      if ( curState & PD_STATE_XOSC_LPM ) {
         load += (( cl >> 8 ) & 0xFF );
      }
      if ( curState & PD_STATE_RFMEM_RET ) {
         load += (( cl >> 16 ) & 0xFF );
      }
      if ( curState & PD_STATE_CACHE_RET ) {
         load += (( cl >> 24 ) & 0xFF );
      }

      //--- Spec. point 9 ---
      load += ((( di * ( shiftedTemp - ( ti << 8 ))) + 128 ) >> 8 );

      // Currently not implementing external load handling
      // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) {
         //--- Spec. point 10 ---
      // } else {
         //--- Spec. point 11 ---
         diffVddrActiveSleep = ( vddrTrimActve - vddrTrimSleep );
         if ( diffVddrActiveSleep < 1 ) diffVddrActiveSleep = 1;
         k = ( diffVddrActiveSleep * 52 );
      // }

      //--- Spec. point 12 ---

      vddrCap = ( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_CAP_M ) >> CCFG_MODE_CONF_VDDR_CAP_S;
      newRechargePeriod = ( vddrCap * k ) / load;
      if ( newRechargePeriod > 0xFFFF ) {
         newRechargePeriod = 0xFFFF;
      }
      powerQualGlobals.pdRechargePeriod = newRechargePeriod;

      //--- Spec. point 13 ---
      if ( curTemp >  127 ) curTemp =  127;
      if ( curTemp < -128 ) curTemp = -128;
      powerQualGlobals.pdTemp    = curTemp;
      powerQualGlobals.pdState   = curState;
   }

   powerQualGlobals.pdTime    = HWREG( AON_RTC_BASE + AON_RTC_O_SEC );

   // Calculate PER_E and PER_M (based on powerQualGlobals.pdRechargePeriod)
   // Round downwards but make sure PER_E=0 and PER_M=1 is the minimum possible setting.
   // (assuming that powerQualGlobals.pdRechargePeriod always are <= 0xFFFF)
   perE = 0;
   perM = powerQualGlobals.pdRechargePeriod;
   if ( perM < 31 ) {
      perM = 31;
      powerQualGlobals.pdRechargePeriod = 31;
   }
   while ( perM > 511 ) {
      perM >>= 1;
      perE  += 1;
   }
   perM = ( perM - 15 ) >> 4;

   HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) =
      ( 0x80A4E700                          ) |
      ( perM << AON_WUC_RECHARGECFG_PER_M_S ) |
      ( perE << AON_WUC_RECHARGECFG_PER_E_S ) ;
   HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) = 0;
}

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static void SysCtrlSystemReset ( void  )

inlinestatic

Perform a full system reset.

Returns

The chip will reset and hence never return from this call.

{
   // Disable CPU interrupts
   CPUcpsid();
   // Write reset register
   HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_SYSRESET_BITN ) = 1;
   // Finally, wait until the above write propagates
   while ( 1 ) {
      // Do nothing, just wait for the reset (and never return from here)
   }
}

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Macro Definition Documentation

#define CPU_DEEP_SLEEP   0x00000002

#define CPU_RUN   0x00000000

#define CPU_SLEEP   0x00000001

#define RSTSRC_CLK_LOSS   (( AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))

#define RSTSRC_PIN_RESET   (( AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))

#define RSTSRC_PWR_ON   (( AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))

#define RSTSRC_SYSRESET   (( AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))

#define RSTSRC_VDDR_LOSS   (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))

#define RSTSRC_VDDS_LOSS   (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))

#define RSTSRC_WAKEUP_FROM_SHUTDOWN   ((( AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) + 1 )

Referenced by SysCtrlResetSourceGet().

#define RSTSRC_WARMRESET   (( AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S ))

#define SYSCTRL_SYSBUS_OFF   0x00000000

#define SYSCTRL_SYSBUS_ON   0x00000001

#define XOSC_IN_HIGH_POWER_MODE   0

Referenced by SysCtrlSetRechargeBeforePowerDown().

#define XOSC_IN_LOW_POWER_MODE   1