Memory Map

The devices supported by the SimpleLink CC13xx/CC26xx SDK each contains several memory regions including RAM, ROM, and Flash. This section aims to show how these memory regions are utilized by the stack and user application. The stack library configuration memory map can be seen below.

CC13x2x1 or CC26x2x1 Memory Map

The following table contains the memory map for the CC13x2x1 or CC26x2x1.

Memory Section	Starting Address	Size (bytes)	Description
Flash	0x00000000	60	Cortex Interrupt Vecs
	0x00001000	816	TI RTOS ROM Jump Table
	Application / Stack Code
	NV	2-5 pages	Non-Volatile Storage
	Last Flash Page*	88	CCFG
ROM	0x10000000	ROM_SIZE	TI-RTOS7, IEEE 802.15.4 MAC, Crypto, Driverlib, Boot
RAM	0x20000000	RAMVEC_SIZE	Interrupt Vector Table in RAM for dynamic Hwi creation
	0x20000100	RTOSRAM_SIZE	Reserved for pointers for TI-RTOS7 in ROM
	.bss and .data
	TI-RTOS7 kernel system stack (CSTACK)
AUX RAM	0x400E0000	AUXRAM_SIZE	Memory area belonging to the Sensor Controller

CC13x2x7 or CC26x2x7 Memory Map

The following table contains the memory map for the CC13x2x7 or CC26x2x7.

Memory Section	Starting Address	Size (bytes)	Description
Flash	0x00000000	60	Cortex Interrupt Vecs
	0x00001000	816	TI RTOS ROM Jump Table
	Application / Stack Code
	NV	2-5 pages	Non-Volatile Storage
	Last Flash Page*	88	CCFG
ROM	0x10000000	ROM_SIZE	TI-RTOS7, IEEE 802.15.4 MAC, Crypto, Driverlib, Boot
RAM	0x20000000	RAMVEC_SIZE	Interrupt Vector Table in RAM for dynamic Hwi creation
	0x20000100	RTOSRAM_SIZE	Reserved for pointers for TI-RTOS7 in ROM
	.bss and .data
	TI-RTOS7 kernel system stack (CSTACK)
AUX RAM	0x400E0000	AUXRAM_SIZE	Memory area belonging to the Sensor Controller

CC13x1x3 or CC26x1x3 Memory Map

The following table contains the Memory Map for the CC13x1x3 or CC26x1x3.

Memory Section	Starting Address	Size (bytes)	Description
Flash	0x00000000	60	Cortex Interrupt Vecs
	Application / Stack Code
	NV	2-5 pages	Non-Volatile Storage
	Last Flash Page*	88	CCFG
RAM	0x20000000	RAMVEC_SIZE	Interrupt Vector Table in RAM for dynamic Hwi creation
	.bss and .data
	TI-RTOS7 kernel system stack (CSTACK)

Memory Map Variables

At the tables above, the following variables are platform dependent.

• Last Flash Page: top of the Flash subtracted by its page size

  • CC13x2x1 or CC26x2x1 : 344 kB or 0x56000 (0x58000 - 0x2000)

  • CC13x2x7 or CC26x2x7 : 696 kB or 0xAE000 (0xB0000 - 0x2000)

  • CC13x1x3 or CC26x1x3 : 344 kB or 0x56000 (0x58000 - 0x2000)

• ROM_SIZE :

  • CC13x2x1 or CC26x2x1 : 256 kB

  • CC13x2x7 or CC26x2x7 : 256 kB

  • CC13x1x3 or CC26x1x3 : N/A. ROM not used on device for TI-RTOS7

• RAMVEC_SIZE :

  • CC13x2x1 or CC26x2x1 : 216 B

  • CC13x2x7 or CC26x2x7 : 216 B

  • CC13x1x3 or CC26x1x3 : 216 B

• RTOSRAM_SIZE :

  • CC13x2x1 or CC26x2x1 : 24 B

  • CC13x2x7 or CC26x2x7 : 24 B

  • CC13x1x3 or CC26x1x3 : N/A. No reserved for pointers for TI-RTOS7 in ROM, due to no ROM used for TI-RTOS7

• AUXRAM_SIZE :

  • CC13x2x1 or CC26x2x1 : 4 kB

  • CC13x2x7 or CC26x2x7 : 4 kB

  • CC13x1x3 or CC26x1x3 : N/A. No AUX RAM present on device

TI-RTOS7 ROM Jump Table

The TI-RTOS7 ROM Jump Table can be relocated to any address. To do that, open the .syscfg file text editor of your project and add the following lines after the ROM declaration:

Note

There is no TI-RTOS7 ROM Jump Table on CC13x1x3 or CC26x1x3

var ROM = xdc.useModule('ti.sysbios.rom.ROM');
if (Program.cpu.deviceName.match(/CC26/)) {
ROM.romName = ROM.CC26X2V2;
}
else if (Program.cpu.deviceName.match(/CC13/)) {
ROM.romName = ROM.CC13X2V2;
}
ROM.constStructAddr       = 0x4000;  // replace 0x4000 with any address in FLASH
ROM.externFuncStructAddr  = 0x43C0;  // replace 0x43C0 with any address in FLASH
ROM.dataStructAddr        = 0x20001080;  // replace 0x20001080 with any address in RAM

The .map file for a given project can be consulted to see exactly what sections of the stack reside in ROM.

Note

The NV region can be configured to be two to five pages long using the NVOCMP_NVPAGES define. Refer to Flash for more information.

Determining Project Build Size

Project options such as device type (ZC, ZR, ZED, ZNP), features (OTA, UART, etc), and the network configurations provided above will affect the flash and RAM space required to build the application. In order to understand this dependency, it is possible to refer to the MAP file generated after building a Z-Stack project. For CCS this is the MEMORY CONFIGURATION section at the top of the MAP file located inside the default folder, where total Flash is equivalent to the total of the FLASH, FLASH_NV, and FLASH_LAST used rows. With IAR it is the Grand Total at the bottom of the MAP file found within the Output folder by adding the code, ro data, and rw data columns.