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| #define CPU_DWT_O_CTRL 0x00000000 |
| #define CPU_DWT_O_CYCCNT 0x00000004 |
| #define CPU_DWT_O_CPICNT 0x00000008 |
| #define CPU_DWT_O_EXCCNT 0x0000000C |
| #define CPU_DWT_O_SLEEPCNT 0x00000010 |
| #define CPU_DWT_O_LSUCNT 0x00000014 |
| #define CPU_DWT_O_FOLDCNT 0x00000018 |
| #define CPU_DWT_O_PCSR 0x0000001C |
| #define CPU_DWT_O_COMP0 0x00000020 |
| #define CPU_DWT_O_MASK0 0x00000024 |
| #define CPU_DWT_O_FUNCTION0 0x00000028 |
| #define CPU_DWT_O_COMP1 0x00000030 |
| #define CPU_DWT_O_MASK1 0x00000034 |
| #define CPU_DWT_O_FUNCTION1 0x00000038 |
| #define CPU_DWT_O_COMP2 0x00000040 |
| #define CPU_DWT_O_MASK2 0x00000044 |
| #define CPU_DWT_O_FUNCTION2 0x00000048 |
| #define CPU_DWT_O_COMP3 0x00000050 |
| #define CPU_DWT_O_MASK3 0x00000054 |
| #define CPU_DWT_O_FUNCTION3 0x00000058 |
| #define CPU_DWT_O_LAR 0x00000FB0 |
| #define CPU_DWT_CTRL_NUMCOMP 0xF0000000 |
| #define CPU_DWT_CTRL_NUMCOMP_BITN 28 |
| #define CPU_DWT_CTRL_NUMCOMP_M 0xF0000000 |
| #define CPU_DWT_CTRL_NUMCOMP_S 28 |
| #define CPU_DWT_CTRL_NOCYCCNT 0x02000000 |
| #define CPU_DWT_CTRL_NOCYCCNT_BITN 25 |
| #define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 |
| #define CPU_DWT_CTRL_NOCYCCNT_S 25 |
| #define CPU_DWT_CTRL_NOPRFCNT 0x01000000 |
| #define CPU_DWT_CTRL_NOPRFCNT_BITN 24 |
| #define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 |
| #define CPU_DWT_CTRL_NOPRFCNT_S 24 |
| #define CPU_DWT_CTRL_CYCEVTENA 0x00400000 |
| #define CPU_DWT_CTRL_CYCEVTENA_BITN 22 |
| #define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 |
| #define CPU_DWT_CTRL_CYCEVTENA_S 22 |
| #define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 |
| #define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 |
| #define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 |
| #define CPU_DWT_CTRL_FOLDEVTENA_S 21 |
| #define CPU_DWT_CTRL_LSUEVTENA 0x00100000 |
| #define CPU_DWT_CTRL_LSUEVTENA_BITN 20 |
| #define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 |
| #define CPU_DWT_CTRL_LSUEVTENA_S 20 |
| #define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 |
| #define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 |
| #define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 |
| #define CPU_DWT_CTRL_SLEEPEVTENA_S 19 |
| #define CPU_DWT_CTRL_EXCEVTENA 0x00040000 |
| #define CPU_DWT_CTRL_EXCEVTENA_BITN 18 |
| #define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 |
| #define CPU_DWT_CTRL_EXCEVTENA_S 18 |
| #define CPU_DWT_CTRL_CPIEVTENA 0x00020000 |
| #define CPU_DWT_CTRL_CPIEVTENA_BITN 17 |
| #define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 |
| #define CPU_DWT_CTRL_CPIEVTENA_S 17 |
| #define CPU_DWT_CTRL_EXCTRCENA 0x00010000 |
| #define CPU_DWT_CTRL_EXCTRCENA_BITN 16 |
| #define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 |
| #define CPU_DWT_CTRL_EXCTRCENA_S 16 |
| #define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 |
| #define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 |
| #define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 |
| #define CPU_DWT_CTRL_PCSAMPLEENA_S 12 |
| #define CPU_DWT_CTRL_SYNCTAP_W 2 |
| #define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 |
| #define CPU_DWT_CTRL_SYNCTAP_S 10 |
| #define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 |
| #define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 |
| #define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 |
| #define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 |
| #define CPU_DWT_CTRL_CYCTAP 0x00000200 |
| #define CPU_DWT_CTRL_CYCTAP_BITN 9 |
| #define CPU_DWT_CTRL_CYCTAP_M 0x00000200 |
| #define CPU_DWT_CTRL_CYCTAP_S 9 |
| #define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 |
| #define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 |
| #define CPU_DWT_CTRL_POSTCNT_W 4 |
| #define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 |
| #define CPU_DWT_CTRL_POSTCNT_S 5 |
| #define CPU_DWT_CTRL_POSTPRESET_W 4 |
| #define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E |
| #define CPU_DWT_CTRL_POSTPRESET_S 1 |
| #define CPU_DWT_CTRL_CYCCNTENA 0x00000001 |
| #define CPU_DWT_CTRL_CYCCNTENA_BITN 0 |
| #define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 |
| #define CPU_DWT_CTRL_CYCCNTENA_S 0 |
| #define CPU_DWT_CYCCNT_CYCCNT_W 32 |
| #define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF |
| #define CPU_DWT_CYCCNT_CYCCNT_S 0 |
| #define CPU_DWT_CPICNT_CPICNT_W 8 |
| #define CPU_DWT_CPICNT_CPICNT_M 0x000000FF |
| #define CPU_DWT_CPICNT_CPICNT_S 0 |
| #define CPU_DWT_EXCCNT_EXCCNT_W 8 |
| #define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF |
| #define CPU_DWT_EXCCNT_EXCCNT_S 0 |
| #define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 |
| #define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF |
| #define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 |
| #define CPU_DWT_LSUCNT_LSUCNT_W 8 |
| #define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF |
| #define CPU_DWT_LSUCNT_LSUCNT_S 0 |
| #define CPU_DWT_FOLDCNT_FOLDCNT_W 8 |
| #define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF |
| #define CPU_DWT_FOLDCNT_FOLDCNT_S 0 |
| #define CPU_DWT_PCSR_EIASAMPLE_W 32 |
| #define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF |
| #define CPU_DWT_PCSR_EIASAMPLE_S 0 |
| #define CPU_DWT_COMP0_COMP_W 32 |
| #define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF |
| #define CPU_DWT_COMP0_COMP_S 0 |
| #define CPU_DWT_MASK0_MASK_W 4 |
| #define CPU_DWT_MASK0_MASK_M 0x0000000F |
| #define CPU_DWT_MASK0_MASK_S 0 |
| #define CPU_DWT_FUNCTION0_MATCHED 0x01000000 |
| #define CPU_DWT_FUNCTION0_MATCHED_BITN 24 |
| #define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 |
| #define CPU_DWT_FUNCTION0_MATCHED_S 24 |
| #define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 |
| #define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 |
| #define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 |
| #define CPU_DWT_FUNCTION0_CYCMATCH_S 7 |
| #define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 |
| #define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 |
| #define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 |
| #define CPU_DWT_FUNCTION0_EMITRANGE_S 5 |
| #define CPU_DWT_FUNCTION0_FUNCTION_W 4 |
| #define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F |
| #define CPU_DWT_FUNCTION0_FUNCTION_S 0 |
| #define CPU_DWT_COMP1_COMP_W 32 |
| #define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF |
| #define CPU_DWT_COMP1_COMP_S 0 |
| #define CPU_DWT_MASK1_MASK_W 4 |
| #define CPU_DWT_MASK1_MASK_M 0x0000000F |
| #define CPU_DWT_MASK1_MASK_S 0 |
| #define CPU_DWT_FUNCTION1_MATCHED 0x01000000 |
| #define CPU_DWT_FUNCTION1_MATCHED_BITN 24 |
| #define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 |
| #define CPU_DWT_FUNCTION1_MATCHED_S 24 |
| #define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 |
| #define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 |
| #define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 |
| #define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 |
| #define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 |
| #define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 |
| #define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 |
| #define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 |
| #define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 |
| #define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 |
| #define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 |
| #define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 |
| #define CPU_DWT_FUNCTION1_LNK1ENA_S 9 |
| #define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 |
| #define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 |
| #define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 |
| #define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 |
| #define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 |
| #define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 |
| #define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 |
| #define CPU_DWT_FUNCTION1_EMITRANGE_S 5 |
| #define CPU_DWT_FUNCTION1_FUNCTION_W 4 |
| #define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F |
| #define CPU_DWT_FUNCTION1_FUNCTION_S 0 |
| #define CPU_DWT_COMP2_COMP_W 32 |
| #define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF |
| #define CPU_DWT_COMP2_COMP_S 0 |
| #define CPU_DWT_MASK2_MASK_W 4 |
| #define CPU_DWT_MASK2_MASK_M 0x0000000F |
| #define CPU_DWT_MASK2_MASK_S 0 |
| #define CPU_DWT_FUNCTION2_MATCHED 0x01000000 |
| #define CPU_DWT_FUNCTION2_MATCHED_BITN 24 |
| #define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 |
| #define CPU_DWT_FUNCTION2_MATCHED_S 24 |
| #define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 |
| #define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 |
| #define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 |
| #define CPU_DWT_FUNCTION2_EMITRANGE_S 5 |
| #define CPU_DWT_FUNCTION2_FUNCTION_W 4 |
| #define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F |
| #define CPU_DWT_FUNCTION2_FUNCTION_S 0 |
| #define CPU_DWT_COMP3_COMP_W 32 |
| #define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF |
| #define CPU_DWT_COMP3_COMP_S 0 |
| #define CPU_DWT_MASK3_MASK_W 4 |
| #define CPU_DWT_MASK3_MASK_M 0x0000000F |
| #define CPU_DWT_MASK3_MASK_S 0 |
| #define CPU_DWT_FUNCTION3_MATCHED 0x01000000 |
| #define CPU_DWT_FUNCTION3_MATCHED_BITN 24 |
| #define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 |
| #define CPU_DWT_FUNCTION3_MATCHED_S 24 |
| #define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 |
| #define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 |
| #define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 |
| #define CPU_DWT_FUNCTION3_EMITRANGE_S 5 |
| #define CPU_DWT_FUNCTION3_FUNCTION_W 4 |
| #define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F |
| #define CPU_DWT_FUNCTION3_FUNCTION_S 0 |