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Go to the source code of this file.
| #define CPU_SCS_O_ICTR 0x00000004 |
| #define CPU_SCS_O_ACTLR 0x00000008 |
| #define CPU_SCS_O_STCSR 0x00000010 |
| #define CPU_SCS_O_STRVR 0x00000014 |
| #define CPU_SCS_O_STCVR 0x00000018 |
| #define CPU_SCS_O_STCR 0x0000001C |
| #define CPU_SCS_O_NVIC_ISER0 0x00000100 |
| #define CPU_SCS_O_NVIC_ISER1 0x00000104 |
| #define CPU_SCS_O_NVIC_ICER0 0x00000180 |
| #define CPU_SCS_O_NVIC_ICER1 0x00000184 |
| #define CPU_SCS_O_NVIC_ISPR0 0x00000200 |
| #define CPU_SCS_O_NVIC_ISPR1 0x00000204 |
| #define CPU_SCS_O_NVIC_ICPR0 0x00000280 |
| #define CPU_SCS_O_NVIC_ICPR1 0x00000284 |
| #define CPU_SCS_O_NVIC_IABR0 0x00000300 |
| #define CPU_SCS_O_NVIC_IABR1 0x00000304 |
| #define CPU_SCS_O_NVIC_IPR0 0x00000400 |
| #define CPU_SCS_O_NVIC_IPR1 0x00000404 |
| #define CPU_SCS_O_NVIC_IPR2 0x00000408 |
| #define CPU_SCS_O_NVIC_IPR3 0x0000040C |
| #define CPU_SCS_O_NVIC_IPR4 0x00000410 |
| #define CPU_SCS_O_NVIC_IPR5 0x00000414 |
| #define CPU_SCS_O_NVIC_IPR6 0x00000418 |
| #define CPU_SCS_O_NVIC_IPR7 0x0000041C |
| #define CPU_SCS_O_NVIC_IPR8 0x00000420 |
| #define CPU_SCS_O_NVIC_IPR9 0x00000424 |
| #define CPU_SCS_O_CPUID 0x00000D00 |
| #define CPU_SCS_O_ICSR 0x00000D04 |
| #define CPU_SCS_O_VTOR 0x00000D08 |
| #define CPU_SCS_O_AIRCR 0x00000D0C |
| #define CPU_SCS_O_SCR 0x00000D10 |
| #define CPU_SCS_O_CCR 0x00000D14 |
| #define CPU_SCS_O_SHPR1 0x00000D18 |
| #define CPU_SCS_O_SHPR2 0x00000D1C |
| #define CPU_SCS_O_SHPR3 0x00000D20 |
| #define CPU_SCS_O_SHCSR 0x00000D24 |
| #define CPU_SCS_O_CFSR 0x00000D28 |
| #define CPU_SCS_O_HFSR 0x00000D2C |
| #define CPU_SCS_O_DFSR 0x00000D30 |
| #define CPU_SCS_O_MMFAR 0x00000D34 |
| #define CPU_SCS_O_BFAR 0x00000D38 |
| #define CPU_SCS_O_AFSR 0x00000D3C |
| #define CPU_SCS_O_ID_PFR0 0x00000D40 |
| #define CPU_SCS_O_ID_PFR1 0x00000D44 |
| #define CPU_SCS_O_ID_DFR0 0x00000D48 |
| #define CPU_SCS_O_ID_AFR0 0x00000D4C |
| #define CPU_SCS_O_ID_MMFR0 0x00000D50 |
| #define CPU_SCS_O_ID_MMFR1 0x00000D54 |
| #define CPU_SCS_O_ID_MMFR2 0x00000D58 |
| #define CPU_SCS_O_ID_MMFR3 0x00000D5C |
| #define CPU_SCS_O_ID_ISAR0 0x00000D60 |
| #define CPU_SCS_O_ID_ISAR1 0x00000D64 |
| #define CPU_SCS_O_ID_ISAR2 0x00000D68 |
| #define CPU_SCS_O_ID_ISAR3 0x00000D6C |
| #define CPU_SCS_O_ID_ISAR4 0x00000D70 |
| #define CPU_SCS_O_CPACR 0x00000D88 |
| #define CPU_SCS_O_MPU_TYPE 0x00000D90 |
| #define CPU_SCS_O_MPU_CTRL 0x00000D94 |
| #define CPU_SCS_O_MPU_RNR 0x00000D98 |
| #define CPU_SCS_O_MPU_RBAR 0x00000D9C |
| #define CPU_SCS_O_MPU_RASR 0x00000DA0 |
| #define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 |
| #define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 |
| #define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC |
| #define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 |
| #define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 |
| #define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 |
| #define CPU_SCS_O_DHCSR 0x00000DF0 |
| #define CPU_SCS_O_DCRSR 0x00000DF4 |
| #define CPU_SCS_O_DCRDR 0x00000DF8 |
| #define CPU_SCS_O_DEMCR 0x00000DFC |
| #define CPU_SCS_O_STIR 0x00000F00 |
| #define CPU_SCS_O_FPCCR 0x00000F34 |
| #define CPU_SCS_O_FPCAR 0x00000F38 |
| #define CPU_SCS_O_FPDSCR 0x00000F3C |
| #define CPU_SCS_O_MVFR0 0x00000F40 |
| #define CPU_SCS_O_MVFR1 0x00000F44 |
| #define CPU_SCS_ICTR_INTLINESNUM_W 3 |
| #define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 |
| #define CPU_SCS_ICTR_INTLINESNUM_S 0 |
| #define CPU_SCS_ACTLR_DISOOFP 0x00000200 |
| #define CPU_SCS_ACTLR_DISOOFP_BITN 9 |
| #define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 |
| #define CPU_SCS_ACTLR_DISOOFP_S 9 |
| #define CPU_SCS_ACTLR_DISFPCA 0x00000100 |
| #define CPU_SCS_ACTLR_DISFPCA_BITN 8 |
| #define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 |
| #define CPU_SCS_ACTLR_DISFPCA_S 8 |
| #define CPU_SCS_ACTLR_DISFOLD 0x00000004 |
| #define CPU_SCS_ACTLR_DISFOLD_BITN 2 |
| #define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 |
| #define CPU_SCS_ACTLR_DISFOLD_S 2 |
| #define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 |
| #define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 |
| #define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 |
| #define CPU_SCS_ACTLR_DISDEFWBUF_S 1 |
| #define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 |
| #define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 |
| #define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 |
| #define CPU_SCS_ACTLR_DISMCYCINT_S 0 |
| #define CPU_SCS_STCSR_COUNTFLAG 0x00010000 |
| #define CPU_SCS_STCSR_COUNTFLAG_BITN 16 |
| #define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 |
| #define CPU_SCS_STCSR_COUNTFLAG_S 16 |
| #define CPU_SCS_STCSR_CLKSOURCE 0x00000004 |
| #define CPU_SCS_STCSR_CLKSOURCE_BITN 2 |
| #define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 |
| #define CPU_SCS_STCSR_CLKSOURCE_S 2 |
| #define CPU_SCS_STCSR_TICKINT 0x00000002 |
| #define CPU_SCS_STCSR_TICKINT_BITN 1 |
| #define CPU_SCS_STCSR_TICKINT_M 0x00000002 |
| #define CPU_SCS_STCSR_TICKINT_S 1 |
| #define CPU_SCS_STCSR_ENABLE 0x00000001 |
| #define CPU_SCS_STCSR_ENABLE_BITN 0 |
| #define CPU_SCS_STCSR_ENABLE_M 0x00000001 |
| #define CPU_SCS_STCSR_ENABLE_S 0 |
| #define CPU_SCS_STRVR_RELOAD_W 24 |
| #define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF |
| #define CPU_SCS_STRVR_RELOAD_S 0 |
| #define CPU_SCS_STCVR_CURRENT_W 24 |
| #define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF |
| #define CPU_SCS_STCVR_CURRENT_S 0 |
| #define CPU_SCS_STCR_NOREF 0x80000000 |
| #define CPU_SCS_STCR_NOREF_BITN 31 |
| #define CPU_SCS_STCR_NOREF_M 0x80000000 |
| #define CPU_SCS_STCR_NOREF_S 31 |
| #define CPU_SCS_STCR_SKEW 0x40000000 |
| #define CPU_SCS_STCR_SKEW_BITN 30 |
| #define CPU_SCS_STCR_SKEW_M 0x40000000 |
| #define CPU_SCS_STCR_SKEW_S 30 |
| #define CPU_SCS_STCR_TENMS_W 24 |
| #define CPU_SCS_STCR_TENMS_M 0x00FFFFFF |
| #define CPU_SCS_STCR_TENMS_S 0 |
| #define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 |
| #define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA31_S 31 |
| #define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 |
| #define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA30_S 30 |
| #define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 |
| #define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA29_S 29 |
| #define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 |
| #define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA28_S 28 |
| #define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 |
| #define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA27_S 27 |
| #define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 |
| #define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA26_S 26 |
| #define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 |
| #define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA25_S 25 |
| #define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 |
| #define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 |
| #define CPU_SCS_NVIC_ISER0_SETENA24_S 24 |
| #define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 |
| #define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 |
| #define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 |
| #define CPU_SCS_NVIC_ISER0_SETENA23_S 23 |
| #define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 |
| #define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 |
| #define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 |
| #define CPU_SCS_NVIC_ISER0_SETENA22_S 22 |
| #define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 |
| #define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 |
| #define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 |
| #define CPU_SCS_NVIC_ISER0_SETENA21_S 21 |
| #define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 |
| #define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 |
| #define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 |
| #define CPU_SCS_NVIC_ISER0_SETENA20_S 20 |
| #define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 |
| #define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 |
| #define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 |
| #define CPU_SCS_NVIC_ISER0_SETENA19_S 19 |
| #define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 |
| #define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 |
| #define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 |
| #define CPU_SCS_NVIC_ISER0_SETENA18_S 18 |
| #define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 |
| #define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 |
| #define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 |
| #define CPU_SCS_NVIC_ISER0_SETENA17_S 17 |
| #define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 |
| #define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 |
| #define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 |
| #define CPU_SCS_NVIC_ISER0_SETENA16_S 16 |
| #define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 |
| #define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 |
| #define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 |
| #define CPU_SCS_NVIC_ISER0_SETENA15_S 15 |
| #define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 |
| #define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 |
| #define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 |
| #define CPU_SCS_NVIC_ISER0_SETENA14_S 14 |
| #define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 |
| #define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 |
| #define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 |
| #define CPU_SCS_NVIC_ISER0_SETENA13_S 13 |
| #define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 |
| #define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 |
| #define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 |
| #define CPU_SCS_NVIC_ISER0_SETENA12_S 12 |
| #define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 |
| #define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 |
| #define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 |
| #define CPU_SCS_NVIC_ISER0_SETENA11_S 11 |
| #define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 |
| #define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 |
| #define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 |
| #define CPU_SCS_NVIC_ISER0_SETENA10_S 10 |
| #define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 |
| #define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 |
| #define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 |
| #define CPU_SCS_NVIC_ISER0_SETENA9_S 9 |
| #define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 |
| #define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 |
| #define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 |
| #define CPU_SCS_NVIC_ISER0_SETENA8_S 8 |
| #define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 |
| #define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 |
| #define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 |
| #define CPU_SCS_NVIC_ISER0_SETENA7_S 7 |
| #define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 |
| #define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 |
| #define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 |
| #define CPU_SCS_NVIC_ISER0_SETENA6_S 6 |
| #define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 |
| #define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 |
| #define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 |
| #define CPU_SCS_NVIC_ISER0_SETENA5_S 5 |
| #define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 |
| #define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 |
| #define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 |
| #define CPU_SCS_NVIC_ISER0_SETENA4_S 4 |
| #define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 |
| #define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 |
| #define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 |
| #define CPU_SCS_NVIC_ISER0_SETENA3_S 3 |
| #define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 |
| #define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 |
| #define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 |
| #define CPU_SCS_NVIC_ISER0_SETENA2_S 2 |
| #define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 |
| #define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 |
| #define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 |
| #define CPU_SCS_NVIC_ISER0_SETENA1_S 1 |
| #define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 |
| #define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 |
| #define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 |
| #define CPU_SCS_NVIC_ISER0_SETENA0_S 0 |
| #define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 |
| #define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 |
| #define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 |
| #define CPU_SCS_NVIC_ISER1_SETENA37_S 5 |
| #define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 |
| #define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 |
| #define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 |
| #define CPU_SCS_NVIC_ISER1_SETENA36_S 4 |
| #define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 |
| #define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 |
| #define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 |
| #define CPU_SCS_NVIC_ISER1_SETENA35_S 3 |
| #define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 |
| #define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 |
| #define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 |
| #define CPU_SCS_NVIC_ISER1_SETENA34_S 2 |
| #define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 |
| #define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 |
| #define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 |
| #define CPU_SCS_NVIC_ISER1_SETENA33_S 1 |
| #define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 |
| #define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 |
| #define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 |
| #define CPU_SCS_NVIC_ISER1_SETENA32_S 0 |
| #define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 |
| #define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 |
| #define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 |
| #define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 |
| #define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 |
| #define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 |
| #define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 |
| #define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 |
| #define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 |
| #define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 |
| #define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 |
| #define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 |
| #define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 |
| #define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 |
| #define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 |
| #define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 |
| #define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 |
| #define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 |
| #define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 |
| #define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 |
| #define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 |
| #define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 |
| #define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 |
| #define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 |
| #define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 |
| #define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 |
| #define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 |
| #define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 |
| #define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 |
| #define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 |
| #define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 |
| #define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 |
| #define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 |
| #define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 |
| #define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 |
| #define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 |
| #define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 |
| #define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 |
| #define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 |
| #define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 |
| #define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 |
| #define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 |
| #define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 |
| #define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 |
| #define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 |
| #define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 |
| #define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 |
| #define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 |
| #define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 |
| #define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 |
| #define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 |
| #define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 |
| #define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 |
| #define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 |
| #define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 |
| #define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 |
| #define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 |
| #define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 |
| #define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 |
| #define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 |
| #define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 |
| #define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 |
| #define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 |
| #define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 |
| #define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 |
| #define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 |
| #define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 |
| #define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 |
| #define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 |
| #define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 |
| #define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 |
| #define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 |
| #define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 |
| #define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 |
| #define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 |
| #define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 |
| #define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 |
| #define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 |
| #define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 |
| #define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 |
| #define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 |
| #define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 |
| #define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 |
| #define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 |
| #define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 |
| #define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 |
| #define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 |
| #define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 |
| #define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 |
| #define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 |
| #define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 |
| #define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 |
| #define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 |
| #define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 |
| #define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 |
| #define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 |
| #define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 |
| #define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 |
| #define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 |
| #define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 |
| #define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 |
| #define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 |
| #define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 |
| #define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 |
| #define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 |
| #define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 |
| #define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 |
| #define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 |
| #define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 |
| #define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 |
| #define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 |
| #define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 |
| #define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 |
| #define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 |
| #define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 |
| #define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 |
| #define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 |
| #define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 |
| #define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 |
| #define CPU_SCS_NVIC_IPR0_PRI_3_W 8 |
| #define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR0_PRI_3_S 24 |
| #define CPU_SCS_NVIC_IPR0_PRI_2_W 8 |
| #define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR0_PRI_2_S 16 |
| #define CPU_SCS_NVIC_IPR0_PRI_1_W 8 |
| #define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR0_PRI_1_S 8 |
| #define CPU_SCS_NVIC_IPR0_PRI_0_W 8 |
| #define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR0_PRI_0_S 0 |
| #define CPU_SCS_NVIC_IPR1_PRI_7_W 8 |
| #define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR1_PRI_7_S 24 |
| #define CPU_SCS_NVIC_IPR1_PRI_6_W 8 |
| #define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR1_PRI_6_S 16 |
| #define CPU_SCS_NVIC_IPR1_PRI_5_W 8 |
| #define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR1_PRI_5_S 8 |
| #define CPU_SCS_NVIC_IPR1_PRI_4_W 8 |
| #define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR1_PRI_4_S 0 |
| #define CPU_SCS_NVIC_IPR2_PRI_11_W 8 |
| #define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR2_PRI_11_S 24 |
| #define CPU_SCS_NVIC_IPR2_PRI_10_W 8 |
| #define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR2_PRI_10_S 16 |
| #define CPU_SCS_NVIC_IPR2_PRI_9_W 8 |
| #define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR2_PRI_9_S 8 |
| #define CPU_SCS_NVIC_IPR2_PRI_8_W 8 |
| #define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR2_PRI_8_S 0 |
| #define CPU_SCS_NVIC_IPR3_PRI_15_W 8 |
| #define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR3_PRI_15_S 24 |
| #define CPU_SCS_NVIC_IPR3_PRI_14_W 8 |
| #define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR3_PRI_14_S 16 |
| #define CPU_SCS_NVIC_IPR3_PRI_13_W 8 |
| #define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR3_PRI_13_S 8 |
| #define CPU_SCS_NVIC_IPR3_PRI_12_W 8 |
| #define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR3_PRI_12_S 0 |
| #define CPU_SCS_NVIC_IPR4_PRI_19_W 8 |
| #define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR4_PRI_19_S 24 |
| #define CPU_SCS_NVIC_IPR4_PRI_18_W 8 |
| #define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR4_PRI_18_S 16 |
| #define CPU_SCS_NVIC_IPR4_PRI_17_W 8 |
| #define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR4_PRI_17_S 8 |
| #define CPU_SCS_NVIC_IPR4_PRI_16_W 8 |
| #define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR4_PRI_16_S 0 |
| #define CPU_SCS_NVIC_IPR5_PRI_23_W 8 |
| #define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR5_PRI_23_S 24 |
| #define CPU_SCS_NVIC_IPR5_PRI_22_W 8 |
| #define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR5_PRI_22_S 16 |
| #define CPU_SCS_NVIC_IPR5_PRI_21_W 8 |
| #define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR5_PRI_21_S 8 |
| #define CPU_SCS_NVIC_IPR5_PRI_20_W 8 |
| #define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR5_PRI_20_S 0 |
| #define CPU_SCS_NVIC_IPR6_PRI_27_W 8 |
| #define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR6_PRI_27_S 24 |
| #define CPU_SCS_NVIC_IPR6_PRI_26_W 8 |
| #define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR6_PRI_26_S 16 |
| #define CPU_SCS_NVIC_IPR6_PRI_25_W 8 |
| #define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR6_PRI_25_S 8 |
| #define CPU_SCS_NVIC_IPR6_PRI_24_W 8 |
| #define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR6_PRI_24_S 0 |
| #define CPU_SCS_NVIC_IPR7_PRI_31_W 8 |
| #define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR7_PRI_31_S 24 |
| #define CPU_SCS_NVIC_IPR7_PRI_30_W 8 |
| #define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR7_PRI_30_S 16 |
| #define CPU_SCS_NVIC_IPR7_PRI_29_W 8 |
| #define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR7_PRI_29_S 8 |
| #define CPU_SCS_NVIC_IPR7_PRI_28_W 8 |
| #define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR7_PRI_28_S 0 |
| #define CPU_SCS_NVIC_IPR8_PRI_35_W 8 |
| #define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 |
| #define CPU_SCS_NVIC_IPR8_PRI_35_S 24 |
| #define CPU_SCS_NVIC_IPR8_PRI_34_W 8 |
| #define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 |
| #define CPU_SCS_NVIC_IPR8_PRI_34_S 16 |
| #define CPU_SCS_NVIC_IPR8_PRI_33_W 8 |
| #define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR8_PRI_33_S 8 |
| #define CPU_SCS_NVIC_IPR8_PRI_32_W 8 |
| #define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR8_PRI_32_S 0 |
| #define CPU_SCS_NVIC_IPR9_PRI_37_W 8 |
| #define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 |
| #define CPU_SCS_NVIC_IPR9_PRI_37_S 8 |
| #define CPU_SCS_NVIC_IPR9_PRI_36_W 8 |
| #define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF |
| #define CPU_SCS_NVIC_IPR9_PRI_36_S 0 |
| #define CPU_SCS_CPUID_IMPLEMENTER_W 8 |
| #define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 |
| #define CPU_SCS_CPUID_IMPLEMENTER_S 24 |
| #define CPU_SCS_CPUID_VARIANT_W 4 |
| #define CPU_SCS_CPUID_VARIANT_M 0x00F00000 |
| #define CPU_SCS_CPUID_VARIANT_S 20 |
| #define CPU_SCS_CPUID_CONSTANT_W 4 |
| #define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 |
| #define CPU_SCS_CPUID_CONSTANT_S 16 |
| #define CPU_SCS_CPUID_PARTNO_W 12 |
| #define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 |
| #define CPU_SCS_CPUID_PARTNO_S 4 |
| #define CPU_SCS_CPUID_REVISION_W 4 |
| #define CPU_SCS_CPUID_REVISION_M 0x0000000F |
| #define CPU_SCS_CPUID_REVISION_S 0 |
| #define CPU_SCS_ICSR_NMIPENDSET 0x80000000 |
| #define CPU_SCS_ICSR_NMIPENDSET_BITN 31 |
| #define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 |
| #define CPU_SCS_ICSR_NMIPENDSET_S 31 |
| #define CPU_SCS_ICSR_PENDSVSET 0x10000000 |
| #define CPU_SCS_ICSR_PENDSVSET_BITN 28 |
| #define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 |
| #define CPU_SCS_ICSR_PENDSVSET_S 28 |
| #define CPU_SCS_ICSR_PENDSVCLR 0x08000000 |
| #define CPU_SCS_ICSR_PENDSVCLR_BITN 27 |
| #define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 |
| #define CPU_SCS_ICSR_PENDSVCLR_S 27 |
| #define CPU_SCS_ICSR_PENDSTSET 0x04000000 |
| #define CPU_SCS_ICSR_PENDSTSET_BITN 26 |
| #define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 |
| #define CPU_SCS_ICSR_PENDSTSET_S 26 |
| #define CPU_SCS_ICSR_PENDSTCLR 0x02000000 |
| #define CPU_SCS_ICSR_PENDSTCLR_BITN 25 |
| #define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 |
| #define CPU_SCS_ICSR_PENDSTCLR_S 25 |
| #define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 |
| #define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 |
| #define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 |
| #define CPU_SCS_ICSR_ISRPREEMPT_S 23 |
| #define CPU_SCS_ICSR_ISRPENDING 0x00400000 |
| #define CPU_SCS_ICSR_ISRPENDING_BITN 22 |
| #define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 |
| #define CPU_SCS_ICSR_ISRPENDING_S 22 |
| #define CPU_SCS_ICSR_VECTPENDING_W 6 |
| #define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 |
| #define CPU_SCS_ICSR_VECTPENDING_S 12 |
| #define CPU_SCS_ICSR_RETTOBASE 0x00000800 |
| #define CPU_SCS_ICSR_RETTOBASE_BITN 11 |
| #define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 |
| #define CPU_SCS_ICSR_RETTOBASE_S 11 |
| #define CPU_SCS_ICSR_VECTACTIVE_W 9 |
| #define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF |
| #define CPU_SCS_ICSR_VECTACTIVE_S 0 |
| #define CPU_SCS_VTOR_TBLOFF_W 23 |
| #define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 |
| #define CPU_SCS_VTOR_TBLOFF_S 7 |
| #define CPU_SCS_AIRCR_VECTKEY_W 16 |
| #define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 |
| #define CPU_SCS_AIRCR_VECTKEY_S 16 |
| #define CPU_SCS_AIRCR_ENDIANESS 0x00008000 |
| #define CPU_SCS_AIRCR_ENDIANESS_BITN 15 |
| #define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 |
| #define CPU_SCS_AIRCR_ENDIANESS_S 15 |
| #define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 |
| #define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 |
| #define CPU_SCS_AIRCR_PRIGROUP_W 3 |
| #define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 |
| #define CPU_SCS_AIRCR_PRIGROUP_S 8 |
| #define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 |
| #define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 |
| #define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 |
| #define CPU_SCS_AIRCR_SYSRESETREQ_S 2 |
| #define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 |
| #define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 |
| #define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 |
| #define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 |
| #define CPU_SCS_AIRCR_VECTRESET 0x00000001 |
| #define CPU_SCS_AIRCR_VECTRESET_BITN 0 |
| #define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 |
| #define CPU_SCS_AIRCR_VECTRESET_S 0 |
| #define CPU_SCS_SCR_SEVONPEND 0x00000010 |
| #define CPU_SCS_SCR_SEVONPEND_BITN 4 |
| #define CPU_SCS_SCR_SEVONPEND_M 0x00000010 |
| #define CPU_SCS_SCR_SEVONPEND_S 4 |
| #define CPU_SCS_SCR_SLEEPDEEP 0x00000004 |
| #define CPU_SCS_SCR_SLEEPDEEP_BITN 2 |
| #define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 |
| #define CPU_SCS_SCR_SLEEPDEEP_S 2 |
| #define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 |
| #define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 |
| #define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 |
| #define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 |
| #define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 |
| #define CPU_SCS_SCR_SLEEPONEXIT_S 1 |
| #define CPU_SCS_CCR_STKALIGN 0x00000200 |
| #define CPU_SCS_CCR_STKALIGN_BITN 9 |
| #define CPU_SCS_CCR_STKALIGN_M 0x00000200 |
| #define CPU_SCS_CCR_STKALIGN_S 9 |
| #define CPU_SCS_CCR_BFHFNMIGN 0x00000100 |
| #define CPU_SCS_CCR_BFHFNMIGN_BITN 8 |
| #define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 |
| #define CPU_SCS_CCR_BFHFNMIGN_S 8 |
| #define CPU_SCS_CCR_DIV_0_TRP 0x00000010 |
| #define CPU_SCS_CCR_DIV_0_TRP_BITN 4 |
| #define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 |
| #define CPU_SCS_CCR_DIV_0_TRP_S 4 |
| #define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 |
| #define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 |
| #define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 |
| #define CPU_SCS_CCR_UNALIGN_TRP_S 3 |
| #define CPU_SCS_CCR_USERSETMPEND 0x00000002 |
| #define CPU_SCS_CCR_USERSETMPEND_BITN 1 |
| #define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 |
| #define CPU_SCS_CCR_USERSETMPEND_S 1 |
| #define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 |
| #define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 |
| #define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 |
| #define CPU_SCS_CCR_NONBASETHREDENA_S 0 |
| #define CPU_SCS_SHPR1_PRI_6_W 8 |
| #define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 |
| #define CPU_SCS_SHPR1_PRI_6_S 16 |
| #define CPU_SCS_SHPR1_PRI_5_W 8 |
| #define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 |
| #define CPU_SCS_SHPR1_PRI_5_S 8 |
| #define CPU_SCS_SHPR1_PRI_4_W 8 |
| #define CPU_SCS_SHPR1_PRI_4_M 0x000000FF |
| #define CPU_SCS_SHPR1_PRI_4_S 0 |
| #define CPU_SCS_SHPR2_PRI_11_W 8 |
| #define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 |
| #define CPU_SCS_SHPR2_PRI_11_S 24 |
| #define CPU_SCS_SHPR3_PRI_15_W 8 |
| #define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 |
| #define CPU_SCS_SHPR3_PRI_15_S 24 |
| #define CPU_SCS_SHPR3_PRI_14_W 8 |
| #define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 |
| #define CPU_SCS_SHPR3_PRI_14_S 16 |
| #define CPU_SCS_SHPR3_PRI_12_W 8 |
| #define CPU_SCS_SHPR3_PRI_12_M 0x000000FF |
| #define CPU_SCS_SHPR3_PRI_12_S 0 |
| #define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 |
| #define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 |
| #define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 |
| #define CPU_SCS_SHCSR_USGFAULTENA_S 18 |
| #define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 |
| #define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 |
| #define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 |
| #define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 |
| #define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 |
| #define CPU_SCS_SHCSR_BUSFAULTENA_S 17 |
| #define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 |
| #define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 |
| #define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 |
| #define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 |
| #define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 |
| #define CPU_SCS_SHCSR_MEMFAULTENA_S 16 |
| #define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 |
| #define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 |
| #define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 |
| #define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 |
| #define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 |
| #define CPU_SCS_SHCSR_SVCALLPENDED_S 15 |
| #define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 |
| #define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 |
| #define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 |
| #define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 |
| #define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 |
| #define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 |
| #define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 |
| #define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 |
| #define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 |
| #define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 |
| #define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 |
| #define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 |
| #define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 |
| #define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 |
| #define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 |
| #define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 |
| #define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 |
| #define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 |
| #define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 |
| #define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 |
| #define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 |
| #define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 |
| #define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 |
| #define CPU_SCS_SHCSR_SYSTICKACT_S 11 |
| #define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 |
| #define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 |
| #define CPU_SCS_SHCSR_PENDSVACT 0x00000400 |
| #define CPU_SCS_SHCSR_PENDSVACT_BITN 10 |
| #define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 |
| #define CPU_SCS_SHCSR_PENDSVACT_S 10 |
| #define CPU_SCS_SHCSR_MONITORACT 0x00000100 |
| #define CPU_SCS_SHCSR_MONITORACT_BITN 8 |
| #define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 |
| #define CPU_SCS_SHCSR_MONITORACT_S 8 |
| #define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 |
| #define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 |
| #define CPU_SCS_SHCSR_SVCALLACT 0x00000080 |
| #define CPU_SCS_SHCSR_SVCALLACT_BITN 7 |
| #define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 |
| #define CPU_SCS_SHCSR_SVCALLACT_S 7 |
| #define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 |
| #define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 |
| #define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 |
| #define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 |
| #define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 |
| #define CPU_SCS_SHCSR_USGFAULTACT_S 3 |
| #define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 |
| #define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 |
| #define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 |
| #define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 |
| #define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 |
| #define CPU_SCS_SHCSR_BUSFAULTACT_S 1 |
| #define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 |
| #define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 |
| #define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 |
| #define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 |
| #define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 |
| #define CPU_SCS_SHCSR_MEMFAULTACT_S 0 |
| #define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 |
| #define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 |
| #define CPU_SCS_CFSR_DIVBYZERO 0x02000000 |
| #define CPU_SCS_CFSR_DIVBYZERO_BITN 25 |
| #define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 |
| #define CPU_SCS_CFSR_DIVBYZERO_S 25 |
| #define CPU_SCS_CFSR_UNALIGNED 0x01000000 |
| #define CPU_SCS_CFSR_UNALIGNED_BITN 24 |
| #define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 |
| #define CPU_SCS_CFSR_UNALIGNED_S 24 |
| #define CPU_SCS_CFSR_NOCP 0x00080000 |
| #define CPU_SCS_CFSR_NOCP_BITN 19 |
| #define CPU_SCS_CFSR_NOCP_M 0x00080000 |
| #define CPU_SCS_CFSR_NOCP_S 19 |
| #define CPU_SCS_CFSR_INVPC 0x00040000 |
| #define CPU_SCS_CFSR_INVPC_BITN 18 |
| #define CPU_SCS_CFSR_INVPC_M 0x00040000 |
| #define CPU_SCS_CFSR_INVPC_S 18 |
| #define CPU_SCS_CFSR_INVSTATE 0x00020000 |
| #define CPU_SCS_CFSR_INVSTATE_BITN 17 |
| #define CPU_SCS_CFSR_INVSTATE_M 0x00020000 |
| #define CPU_SCS_CFSR_INVSTATE_S 17 |
| #define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 |
| #define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 |
| #define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 |
| #define CPU_SCS_CFSR_UNDEFINSTR_S 16 |
| #define CPU_SCS_CFSR_BFARVALID 0x00008000 |
| #define CPU_SCS_CFSR_BFARVALID_BITN 15 |
| #define CPU_SCS_CFSR_BFARVALID_M 0x00008000 |
| #define CPU_SCS_CFSR_BFARVALID_S 15 |
| #define CPU_SCS_CFSR_STKERR 0x00001000 |
| #define CPU_SCS_CFSR_STKERR_BITN 12 |
| #define CPU_SCS_CFSR_STKERR_M 0x00001000 |
| #define CPU_SCS_CFSR_STKERR_S 12 |
| #define CPU_SCS_CFSR_UNSTKERR 0x00000800 |
| #define CPU_SCS_CFSR_UNSTKERR_BITN 11 |
| #define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 |
| #define CPU_SCS_CFSR_UNSTKERR_S 11 |
| #define CPU_SCS_CFSR_IMPRECISERR 0x00000400 |
| #define CPU_SCS_CFSR_IMPRECISERR_BITN 10 |
| #define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 |
| #define CPU_SCS_CFSR_IMPRECISERR_S 10 |
| #define CPU_SCS_CFSR_PRECISERR 0x00000200 |
| #define CPU_SCS_CFSR_PRECISERR_BITN 9 |
| #define CPU_SCS_CFSR_PRECISERR_M 0x00000200 |
| #define CPU_SCS_CFSR_PRECISERR_S 9 |
| #define CPU_SCS_CFSR_IBUSERR 0x00000100 |
| #define CPU_SCS_CFSR_IBUSERR_BITN 8 |
| #define CPU_SCS_CFSR_IBUSERR_M 0x00000100 |
| #define CPU_SCS_CFSR_IBUSERR_S 8 |
| #define CPU_SCS_CFSR_MMARVALID 0x00000080 |
| #define CPU_SCS_CFSR_MMARVALID_BITN 7 |
| #define CPU_SCS_CFSR_MMARVALID_M 0x00000080 |
| #define CPU_SCS_CFSR_MMARVALID_S 7 |
| #define CPU_SCS_CFSR_MSTKERR 0x00000010 |
| #define CPU_SCS_CFSR_MSTKERR_BITN 4 |
| #define CPU_SCS_CFSR_MSTKERR_M 0x00000010 |
| #define CPU_SCS_CFSR_MSTKERR_S 4 |
| #define CPU_SCS_CFSR_MUNSTKERR 0x00000008 |
| #define CPU_SCS_CFSR_MUNSTKERR_BITN 3 |
| #define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 |
| #define CPU_SCS_CFSR_MUNSTKERR_S 3 |
| #define CPU_SCS_CFSR_DACCVIOL 0x00000002 |
| #define CPU_SCS_CFSR_DACCVIOL_BITN 1 |
| #define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 |
| #define CPU_SCS_CFSR_DACCVIOL_S 1 |
| #define CPU_SCS_CFSR_IACCVIOL 0x00000001 |
| #define CPU_SCS_CFSR_IACCVIOL_BITN 0 |
| #define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 |
| #define CPU_SCS_CFSR_IACCVIOL_S 0 |
| #define CPU_SCS_HFSR_DEBUGEVT 0x80000000 |
| #define CPU_SCS_HFSR_DEBUGEVT_BITN 31 |
| #define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 |
| #define CPU_SCS_HFSR_DEBUGEVT_S 31 |
| #define CPU_SCS_HFSR_FORCED 0x40000000 |
| #define CPU_SCS_HFSR_FORCED_BITN 30 |
| #define CPU_SCS_HFSR_FORCED_M 0x40000000 |
| #define CPU_SCS_HFSR_FORCED_S 30 |
| #define CPU_SCS_HFSR_VECTTBL 0x00000002 |
| #define CPU_SCS_HFSR_VECTTBL_BITN 1 |
| #define CPU_SCS_HFSR_VECTTBL_M 0x00000002 |
| #define CPU_SCS_HFSR_VECTTBL_S 1 |
| #define CPU_SCS_DFSR_EXTERNAL 0x00000010 |
| #define CPU_SCS_DFSR_EXTERNAL_BITN 4 |
| #define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 |
| #define CPU_SCS_DFSR_EXTERNAL_S 4 |
| #define CPU_SCS_DFSR_VCATCH 0x00000008 |
| #define CPU_SCS_DFSR_VCATCH_BITN 3 |
| #define CPU_SCS_DFSR_VCATCH_M 0x00000008 |
| #define CPU_SCS_DFSR_VCATCH_S 3 |
| #define CPU_SCS_DFSR_DWTTRAP 0x00000004 |
| #define CPU_SCS_DFSR_DWTTRAP_BITN 2 |
| #define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 |
| #define CPU_SCS_DFSR_DWTTRAP_S 2 |
| #define CPU_SCS_DFSR_BKPT 0x00000002 |
| #define CPU_SCS_DFSR_BKPT_BITN 1 |
| #define CPU_SCS_DFSR_BKPT_M 0x00000002 |
| #define CPU_SCS_DFSR_BKPT_S 1 |
| #define CPU_SCS_DFSR_HALTED 0x00000001 |
| #define CPU_SCS_DFSR_HALTED_BITN 0 |
| #define CPU_SCS_DFSR_HALTED_M 0x00000001 |
| #define CPU_SCS_DFSR_HALTED_S 0 |
| #define CPU_SCS_MMFAR_ADDRESS_W 32 |
| #define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF |
| #define CPU_SCS_MMFAR_ADDRESS_S 0 |
| #define CPU_SCS_BFAR_ADDRESS_W 32 |
| #define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF |
| #define CPU_SCS_BFAR_ADDRESS_S 0 |
| #define CPU_SCS_AFSR_IMPDEF_W 32 |
| #define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF |
| #define CPU_SCS_AFSR_IMPDEF_S 0 |
| #define CPU_SCS_ID_PFR0_STATE1_W 4 |
| #define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 |
| #define CPU_SCS_ID_PFR0_STATE1_S 4 |
| #define CPU_SCS_ID_PFR0_STATE0_W 4 |
| #define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F |
| #define CPU_SCS_ID_PFR0_STATE0_S 0 |
| #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 |
| #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 |
| #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 |
| #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 |
| #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 |
| #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 |
| #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 |
| #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 |
| #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 |
| #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 |
| #define CPU_SCS_MPU_TYPE_IREGION_W 8 |
| #define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 |
| #define CPU_SCS_MPU_TYPE_IREGION_S 16 |
| #define CPU_SCS_MPU_TYPE_DREGION_W 8 |
| #define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 |
| #define CPU_SCS_MPU_TYPE_DREGION_S 8 |
| #define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 |
| #define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 |
| #define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 |
| #define CPU_SCS_MPU_TYPE_SEPARATE_S 0 |
| #define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 |
| #define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 |
| #define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 |
| #define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 |
| #define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 |
| #define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 |
| #define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 |
| #define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 |
| #define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 |
| #define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 |
| #define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 |
| #define CPU_SCS_MPU_CTRL_ENABLE_S 0 |
| #define CPU_SCS_MPU_RNR_REGION_W 8 |
| #define CPU_SCS_MPU_RNR_REGION_M 0x000000FF |
| #define CPU_SCS_MPU_RNR_REGION_S 0 |
| #define CPU_SCS_MPU_RBAR_ADDR_W 27 |
| #define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 |
| #define CPU_SCS_MPU_RBAR_ADDR_S 5 |
| #define CPU_SCS_MPU_RBAR_VALID 0x00000010 |
| #define CPU_SCS_MPU_RBAR_VALID_BITN 4 |
| #define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 |
| #define CPU_SCS_MPU_RBAR_VALID_S 4 |
| #define CPU_SCS_MPU_RBAR_REGION_W 4 |
| #define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F |
| #define CPU_SCS_MPU_RBAR_REGION_S 0 |
| #define CPU_SCS_MPU_RASR_XN 0x10000000 |
| #define CPU_SCS_MPU_RASR_XN_BITN 28 |
| #define CPU_SCS_MPU_RASR_XN_M 0x10000000 |
| #define CPU_SCS_MPU_RASR_XN_S 28 |
| #define CPU_SCS_MPU_RASR_AP_W 3 |
| #define CPU_SCS_MPU_RASR_AP_M 0x07000000 |
| #define CPU_SCS_MPU_RASR_AP_S 24 |
| #define CPU_SCS_MPU_RASR_TEX_W 3 |
| #define CPU_SCS_MPU_RASR_TEX_M 0x00380000 |
| #define CPU_SCS_MPU_RASR_TEX_S 19 |
| #define CPU_SCS_MPU_RASR_S 0x00040000 |
| #define CPU_SCS_MPU_RASR_S_BITN 18 |
| #define CPU_SCS_MPU_RASR_S_M 0x00040000 |
| #define CPU_SCS_MPU_RASR_S_S 18 |
| #define CPU_SCS_MPU_RASR_C 0x00020000 |
| #define CPU_SCS_MPU_RASR_C_BITN 17 |
| #define CPU_SCS_MPU_RASR_C_M 0x00020000 |
| #define CPU_SCS_MPU_RASR_C_S 17 |
| #define CPU_SCS_MPU_RASR_B 0x00010000 |
| #define CPU_SCS_MPU_RASR_B_BITN 16 |
| #define CPU_SCS_MPU_RASR_B_M 0x00010000 |
| #define CPU_SCS_MPU_RASR_B_S 16 |
| #define CPU_SCS_MPU_RASR_SRD_W 8 |
| #define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 |
| #define CPU_SCS_MPU_RASR_SRD_S 8 |
| #define CPU_SCS_MPU_RASR_SIZE_W 5 |
| #define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E |
| #define CPU_SCS_MPU_RASR_SIZE_S 1 |
| #define CPU_SCS_MPU_RASR_ENABLE 0x00000001 |
| #define CPU_SCS_MPU_RASR_ENABLE_BITN 0 |
| #define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 |
| #define CPU_SCS_MPU_RASR_ENABLE_S 0 |
| #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 |
| #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF |
| #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 |
| #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 |
| #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF |
| #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 |
| #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 |
| #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF |
| #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 |
| #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 |
| #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF |
| #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 |
| #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 |
| #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF |
| #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 |
| #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 |
| #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF |
| #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 |
| #define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 |
| #define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 |
| #define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 |
| #define CPU_SCS_DHCSR_S_RESET_ST_S 25 |
| #define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 |
| #define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 |
| #define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 |
| #define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 |
| #define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 |
| #define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 |
| #define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 |
| #define CPU_SCS_DHCSR_S_LOCKUP_S 19 |
| #define CPU_SCS_DHCSR_S_SLEEP 0x00040000 |
| #define CPU_SCS_DHCSR_S_SLEEP_BITN 18 |
| #define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 |
| #define CPU_SCS_DHCSR_S_SLEEP_S 18 |
| #define CPU_SCS_DHCSR_S_HALT 0x00020000 |
| #define CPU_SCS_DHCSR_S_HALT_BITN 17 |
| #define CPU_SCS_DHCSR_S_HALT_M 0x00020000 |
| #define CPU_SCS_DHCSR_S_HALT_S 17 |
| #define CPU_SCS_DHCSR_S_REGRDY 0x00010000 |
| #define CPU_SCS_DHCSR_S_REGRDY_BITN 16 |
| #define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 |
| #define CPU_SCS_DHCSR_S_REGRDY_S 16 |
| #define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 |
| #define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 |
| #define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 |
| #define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 |
| #define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 |
| #define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 |
| #define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 |
| #define CPU_SCS_DHCSR_C_MASKINTS_S 3 |
| #define CPU_SCS_DHCSR_C_STEP 0x00000004 |
| #define CPU_SCS_DHCSR_C_STEP_BITN 2 |
| #define CPU_SCS_DHCSR_C_STEP_M 0x00000004 |
| #define CPU_SCS_DHCSR_C_STEP_S 2 |
| #define CPU_SCS_DHCSR_C_HALT 0x00000002 |
| #define CPU_SCS_DHCSR_C_HALT_BITN 1 |
| #define CPU_SCS_DHCSR_C_HALT_M 0x00000002 |
| #define CPU_SCS_DHCSR_C_HALT_S 1 |
| #define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 |
| #define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 |
| #define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 |
| #define CPU_SCS_DHCSR_C_DEBUGEN_S 0 |
| #define CPU_SCS_DCRSR_REGWNR 0x00010000 |
| #define CPU_SCS_DCRSR_REGWNR_BITN 16 |
| #define CPU_SCS_DCRSR_REGWNR_M 0x00010000 |
| #define CPU_SCS_DCRSR_REGWNR_S 16 |
| #define CPU_SCS_DCRSR_REGSEL_W 5 |
| #define CPU_SCS_DCRSR_REGSEL_M 0x0000001F |
| #define CPU_SCS_DCRSR_REGSEL_S 0 |
| #define CPU_SCS_DCRDR_DCRDR_W 32 |
| #define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF |
| #define CPU_SCS_DCRDR_DCRDR_S 0 |
| #define CPU_SCS_DEMCR_TRCENA 0x01000000 |
| #define CPU_SCS_DEMCR_TRCENA_BITN 24 |
| #define CPU_SCS_DEMCR_TRCENA_M 0x01000000 |
| #define CPU_SCS_DEMCR_TRCENA_S 24 |
| #define CPU_SCS_DEMCR_MON_REQ 0x00080000 |
| #define CPU_SCS_DEMCR_MON_REQ_BITN 19 |
| #define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 |
| #define CPU_SCS_DEMCR_MON_REQ_S 19 |
| #define CPU_SCS_DEMCR_MON_STEP 0x00040000 |
| #define CPU_SCS_DEMCR_MON_STEP_BITN 18 |
| #define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 |
| #define CPU_SCS_DEMCR_MON_STEP_S 18 |
| #define CPU_SCS_DEMCR_MON_PEND 0x00020000 |
| #define CPU_SCS_DEMCR_MON_PEND_BITN 17 |
| #define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 |
| #define CPU_SCS_DEMCR_MON_PEND_S 17 |
| #define CPU_SCS_DEMCR_MON_EN 0x00010000 |
| #define CPU_SCS_DEMCR_MON_EN_BITN 16 |
| #define CPU_SCS_DEMCR_MON_EN_M 0x00010000 |
| #define CPU_SCS_DEMCR_MON_EN_S 16 |
| #define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 |
| #define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 |
| #define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 |
| #define CPU_SCS_DEMCR_VC_HARDERR_S 10 |
| #define CPU_SCS_DEMCR_VC_INTERR 0x00000200 |
| #define CPU_SCS_DEMCR_VC_INTERR_BITN 9 |
| #define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 |
| #define CPU_SCS_DEMCR_VC_INTERR_S 9 |
| #define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 |
| #define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 |
| #define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 |
| #define CPU_SCS_DEMCR_VC_BUSERR_S 8 |
| #define CPU_SCS_DEMCR_VC_STATERR 0x00000080 |
| #define CPU_SCS_DEMCR_VC_STATERR_BITN 7 |
| #define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 |
| #define CPU_SCS_DEMCR_VC_STATERR_S 7 |
| #define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 |
| #define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 |
| #define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 |
| #define CPU_SCS_DEMCR_VC_CHKERR_S 6 |
| #define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 |
| #define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 |
| #define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 |
| #define CPU_SCS_DEMCR_VC_NOCPERR_S 5 |
| #define CPU_SCS_DEMCR_VC_MMERR 0x00000010 |
| #define CPU_SCS_DEMCR_VC_MMERR_BITN 4 |
| #define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 |
| #define CPU_SCS_DEMCR_VC_MMERR_S 4 |
| #define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 |
| #define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 |
| #define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 |
| #define CPU_SCS_DEMCR_VC_CORERESET_S 0 |
| #define CPU_SCS_STIR_INTID_W 9 |
| #define CPU_SCS_STIR_INTID_M 0x000001FF |
| #define CPU_SCS_STIR_INTID_S 0 |
| #define CPU_SCS_FPCCR_ASPEN 0x80000000 |
| #define CPU_SCS_FPCCR_ASPEN_BITN 31 |
| #define CPU_SCS_FPCCR_ASPEN_M 0x80000000 |
| #define CPU_SCS_FPCCR_ASPEN_S 31 |
| #define CPU_SCS_FPCCR_LSPEN 0x40000000 |
| #define CPU_SCS_FPCCR_LSPEN_BITN 30 |
| #define CPU_SCS_FPCCR_LSPEN_M 0x40000000 |
| #define CPU_SCS_FPCCR_LSPEN_S 30 |
| #define CPU_SCS_FPCCR_MONRDY 0x00000100 |
| #define CPU_SCS_FPCCR_MONRDY_BITN 8 |
| #define CPU_SCS_FPCCR_MONRDY_M 0x00000100 |
| #define CPU_SCS_FPCCR_MONRDY_S 8 |
| #define CPU_SCS_FPCCR_BFRDY 0x00000040 |
| #define CPU_SCS_FPCCR_BFRDY_BITN 6 |
| #define CPU_SCS_FPCCR_BFRDY_M 0x00000040 |
| #define CPU_SCS_FPCCR_BFRDY_S 6 |
| #define CPU_SCS_FPCCR_MMRDY 0x00000020 |
| #define CPU_SCS_FPCCR_MMRDY_BITN 5 |
| #define CPU_SCS_FPCCR_MMRDY_M 0x00000020 |
| #define CPU_SCS_FPCCR_MMRDY_S 5 |
| #define CPU_SCS_FPCCR_HFRDY 0x00000010 |
| #define CPU_SCS_FPCCR_HFRDY_BITN 4 |
| #define CPU_SCS_FPCCR_HFRDY_M 0x00000010 |
| #define CPU_SCS_FPCCR_HFRDY_S 4 |
| #define CPU_SCS_FPCCR_THREAD 0x00000008 |
| #define CPU_SCS_FPCCR_THREAD_BITN 3 |
| #define CPU_SCS_FPCCR_THREAD_M 0x00000008 |
| #define CPU_SCS_FPCCR_THREAD_S 3 |
| #define CPU_SCS_FPCCR_USER 0x00000002 |
| #define CPU_SCS_FPCCR_USER_BITN 1 |
| #define CPU_SCS_FPCCR_USER_M 0x00000002 |
| #define CPU_SCS_FPCCR_USER_S 1 |
| #define CPU_SCS_FPCCR_LSPACT 0x00000001 |
| #define CPU_SCS_FPCCR_LSPACT_BITN 0 |
| #define CPU_SCS_FPCCR_LSPACT_M 0x00000001 |
| #define CPU_SCS_FPCCR_LSPACT_S 0 |
| #define CPU_SCS_FPCAR_ADDRESS_W 30 |
| #define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC |
| #define CPU_SCS_FPCAR_ADDRESS_S 2 |
| #define CPU_SCS_FPDSCR_AHP 0x04000000 |
| #define CPU_SCS_FPDSCR_AHP_BITN 26 |
| #define CPU_SCS_FPDSCR_AHP_M 0x04000000 |
| #define CPU_SCS_FPDSCR_AHP_S 26 |
| #define CPU_SCS_FPDSCR_DN 0x02000000 |
| #define CPU_SCS_FPDSCR_DN_BITN 25 |
| #define CPU_SCS_FPDSCR_DN_M 0x02000000 |
| #define CPU_SCS_FPDSCR_DN_S 25 |
| #define CPU_SCS_FPDSCR_FZ 0x01000000 |
| #define CPU_SCS_FPDSCR_FZ_BITN 24 |
| #define CPU_SCS_FPDSCR_FZ_M 0x01000000 |
| #define CPU_SCS_FPDSCR_FZ_S 24 |
| #define CPU_SCS_FPDSCR_RMODE_W 2 |
| #define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 |
| #define CPU_SCS_FPDSCR_RMODE_S 22 |
| #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 |
| #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 |
| #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 |
| #define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 |
| #define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 |
| #define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 |
| #define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 |
| #define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 |
| #define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 |
| #define CPU_SCS_MVFR0_DIVIDE_W 4 |
| #define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 |
| #define CPU_SCS_MVFR0_DIVIDE_S 16 |
| #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 |
| #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 |
| #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 |
| #define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 |
| #define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 |
| #define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 |
| #define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 |
| #define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 |
| #define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 |
| #define CPU_SCS_MVFR0_A_SIMD_W 4 |
| #define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F |
| #define CPU_SCS_MVFR0_A_SIMD_S 0 |
| #define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 |
| #define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 |
| #define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 |
| #define CPU_SCS_MVFR1_FP_HPFP_W 4 |
| #define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 |
| #define CPU_SCS_MVFR1_FP_HPFP_S 24 |
| #define CPU_SCS_MVFR1_D_NAN_MODE_W 4 |
| #define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 |
| #define CPU_SCS_MVFR1_D_NAN_MODE_S 4 |
| #define CPU_SCS_MVFR1_FTZ_MODE_W 4 |
| #define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F |
| #define CPU_SCS_MVFR1_FTZ_MODE_S 0 |