cslr_soc_defines.h File Reference

Go to the source code of this file.

Macros
#define	CSL_EPWM_PER_CNT   (1U)
	Number of ePWM instances. More...
#define	SOC_ADCBUF_NUM_RX_CHANNEL   (4U)
#define	ESM_NUM_GROUP_MAX   (3U)
#define	ESM_NUM_INTR_PER_GROUP   (128U)
#define	SOC_EDMA_NUM_DMACH   (64U)
	Number of DMA Channels. More...
#define	SOC_EDMA_NUM_QDMACH   (8U)
	Number of QDMA Channels. More...
#define	SOC_EDMA_NUM_PARAMSETS   (128U)
	Number of PaRAM Sets available. More...
#define	SOC_EDMA_NUM_EVQUE   (2U)
	Number of Event Queues available. More...
#define	SOC_EDMA_CHMAPEXIST   (1U)
	Support for Channel to PaRAM Set mapping. More...
#define	SOC_EDMA_NUM_REGIONS   (8)
	Number of EDMA Regions. More...
#define	SOC_EDMA_MEMPROTECT   (1U)
	Support for Memory Protection. More...
#define	MCAN_MSG_RAM_MAX_WORD_COUNT   (4352U)
	MCAN Maximum Message RAM words. More...
#define	MCAN_MAX_RX_DMA_BUFFERS   (3U)
	Maximum number of Rx Dma buffers. More...
#define	MCAN_MAX_TX_DMA_BUFFERS   (3U)
	Maximum number of Tx Dma buffers. More...
#define	EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_RX_REQ   0
	APPSS TPCC A EVENT MAP. More...
#define	EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_TX_REQ   1
#define	EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_RX_REQ   2
#define	EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_TX_REQ   3
#define	EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_RX_REQ   4
#define	EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_TX_REQ   5
#define	EDMA_APPSS_TPCC_A_EVT_LIN_DMA_RX_REQ   6
#define	EDMA_APPSS_TPCC_A_EVT_LIN_DMA_TX_REQ   7
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_DMA_REQ0   8
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_DMA_REQ1   9
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT1   10
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT2   11
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT3   12
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT4   13
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT5   14
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT6   15
#define	EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT7   16
#define	EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ0   17
#define	EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ1   18
#define	EDMA_APPSS_TPCC_A_GIO_INT0   19
#define	EDMA_APPSS_TPCC_A_GIO_INT1   20
#define	EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ0   21
#define	EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ1   22
#define	EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ2_AND_MCAN2_FE_INT1   23
#define	EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ3_AND_MCAN2_FE_INT2   24
#define	EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ0_AND_MCAN2_FE_INT3   25
#define	EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ1   26
#define	EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ2_AND_MCAN2_FE_INT4   27
#define	EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ3_AND_MCAN2_FE_INT5   28
#define	EDMA_APPSS_TPCC_A_MCRC_DMA_REQ0   29
#define	EDMA_APPSS_TPCC_A_MCRC_DMA_REQ1   30
#define	EDMA_APPSS_TPCC_A_QSPI_DMA_REQ   31
#define	EDMA_APPSS_TPCC_A_PWM_DMA_REQ0_AND_MCAN2_FE_INT6   32
#define	EDMA_APPSS_TPCC_A_PWM_DMA_REQ1_AND_MCAN2_FE_INT7   33
#define	EDMA_APPSS_TPCC_A_SCI2_DMA_RX_REQ   34
#define	EDMA_APPSS_TPCC_A_SCI2_DMA_TX_REQ   35
#define	EDMA_APPSS_TPCC_A_FRAMETIMER_FRAME_START   36
#define	EDMA_APPSS_TPCC_A_CHIRP_AVAIL_IRQ   37
#define	EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_END   38
#define	EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_START   39
#define	EDMA_APPSS_TPCC_A_CHIRPTIMER_FRAME_END   40
#define	EDMA_APPSS_TPCC_A_ADC_VALID_START   41
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ0   42
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ1   43
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ2   44
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ3_AND_DTHE_SM3_DMA_REQ0   45
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ4_AND_DTHE_SM3_DMA_REQ1   46
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ5_AND_DTHE_SM3_DMA_REQ2   47
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ0   48
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ1   49
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ2   50
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ3   51
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ4_AND_DTHE_SM4_DMA_REQ0   52
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ5_AND_DTHE_SM4_DMA_REQ1   53
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ6_AND_DTHE_SM4_DMA_REQ2   54
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ7_AND_DTHE_SM4_DMA_REQ3   55
#define	EDMA_APPSS_TPCC_A_EVT_GPADC_IFM_DONE   56
#define	EDMA_APPSS_TPCC_A_FEC_INTR0   57
#define	EDMA_APPSS_TPCC_A_FEC_INTR1   58
#define	EDMA_APPSS_TPCC_A_FEC_INTR2   59
#define	EDMA_APPSS_TPCC_A_FEC_INTR3   60
#define	EDMA_APPSS_TPCC_A_EVT_FREE_0   61
#define	EDMA_APPSS_TPCC_A_EVT_MCAN2_DMA_REQ0   62
#define	EDMA_APPSS_TPCC_A_EVT_MCAN2_DMA_REQ1   63
#define	EDMA_DSS_TPCC_A_FRAMETIMER_FRAME_START   0
	DSP TPCC A EVENT MAP. More...
#define	EDMA_DSS_TPCC_A_CHIRP_AVAIL_IRQ   1
#define	EDMA_DSS_TPCC_A_CHIRPTIMER_CHIRP_END   2
#define	EDMA_DSS_TPCC_A_CHIRPTIMER_CHIRP_START   3
#define	EDMA_DSS_TPCC_A_CHIRPTIMER_FRAME_END   4
#define	EDMA_DSS_TPCC_A_EVT_ADC_VALID_START   5
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_0   6
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_1   7
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_2   8
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_3   9
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_4   10
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_5   11
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_6   12
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_7   13
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_8   14
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_9   15
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_10   16
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_11   17
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_12   18
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_13   19
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_14   20
#define	EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_15   21
#define	EDMA_DSS_TPCC_A_EVT_HWA_LOOP_INT   22
#define	EDMA_DSS_TPCC_A_EVT_HWA_PARAMDONE_INT   23
#define	EDMA_DSS_TPCC_A_EVT_SPI1_DMA_RX_REQ   24
#define	EDMA_DSS_TPCC_A_EVT_SPI1_DMA_TX_REQ   25
#define	EDMA_DSS_TPCC_A_EVT_SPI2_DMA_RX_REQ   26
#define	EDMA_DSS_TPCC_A_EVT_SPI2_DMA_TX_REQ   27
#define	EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ0   28
#define	EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ1   29
#define	EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ2   30
#define	EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ3   31
#define	EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ4   32
#define	EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ5   33
#define	EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ6   34
#define	EDMA_DSS_TPCC_A_EVT_DSS_SCIA_RX_DMA_REQ   35
#define	EDMA_DSS_TPCC_A_EVT_DSS_SCIA_TX_DMA_REQ   36
#define	EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ0   37
#define	EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ1   38
#define	EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ2   39
#define	EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ3   40
#define	EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ0   41
#define	EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ1   42
#define	EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ2   43
#define	EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ3   44
#define	EDMA_DSS_TPCC_A_EVT_DSS_MCRC_DMA_REQ0   45
#define	EDMA_DSS_TPCC_A_EVT_DSS_MCRC_DMA_REQ1   46
#define	EDMA_DSS_TPCC_A_EVT_FREE_0   47
#define	EDMA_DSS_TPCC_A_EVT_FREE_1   48
#define	EDMA_DSS_TPCC_A_EVT_FREE_2   49
#define	EDMA_DSS_TPCC_A_EVT_FREE_3   50
#define	EDMA_DSS_TPCC_A_EVT_FREE_4   51
#define	EDMA_DSS_TPCC_A_EVT_FREE_5   52
#define	EDMA_DSS_TPCC_A_EVT_FREE_6   53
#define	EDMA_DSS_TPCC_A_EVT_FREE_7   54
#define	EDMA_DSS_TPCC_A_EVT_FREE_8   55
#define	EDMA_DSS_TPCC_A_EVT_FREE_9   56
#define	EDMA_DSS_TPCC_A_EVT_FREE_10   57
#define	EDMA_DSS_TPCC_A_EVT_FREE_11   58
#define	EDMA_DSS_TPCC_A_EVT_FREE_12   59
#define	EDMA_DSS_TPCC_A_EVT_FREE_13   60
#define	EDMA_DSS_TPCC_A_EVT_FREE_14   61
#define	EDMA_DSS_TPCC_A_EVT_FREE_15   62
#define	EDMA_DSS_TPCC_A_EVT_FREE_16   63
#define	EDMA_DSS_TPCC_B_FRAMETIMER_FRAME_START   0
	DSP TPCC B EVENT MAP. More...
#define	EDMA_DSS_TPCC_B_CHIRP_AVAIL_IRQ   1
#define	EDMA_DSS_TPCC_B_CHIRPTIMER_CHIRP_END   2
#define	EDMA_DSS_TPCC_B_CHIRPTIMER_CHIRP_START   3
#define	EDMA_DSS_TPCC_B_CHIRPTIMER_FRAME_END   4
#define	EDMA_DSS_TPCC_B_EVT_ADC_VALID_START   5
#define	EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_0   6
#define	EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_1   7
#define	EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_2   8
#define	EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_3   9
#define	EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_4   10
#define	EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_5   11
#define	EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_6   12
#define	EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_7   13
#define	EDMA_DSS_TPCC_B_EVT_HWA_LOOP_INT   14
#define	EDMA_DSS_TPCC_B_EVT_HWA_PARAMDONE_INT   15
#define	EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ0   16
#define	EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ1   17
#define	EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ2   18
#define	EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ3   19
#define	EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ4   20
#define	EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ5   21
#define	EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ6   22
#define	EDMA_DSS_TPCC_B_EVT_DSS_SCIA_RX_DMA_REQ   23
#define	EDMA_DSS_TPCC_B_EVT_DSS_SCIA_TX_DMA_REQ   24
#define	EDMA_DSS_TPCC_B_EVT_DSS_RTIA_DMA_REQ0   25
#define	EDMA_DSS_TPCC_B_EVT_DSS_RTIA_DMA_REQ1   26
#define	EDMA_DSS_TPCC_B_EVT_DSS_WDT_DMA_REQ0   27
#define	EDMA_DSS_TPCC_B_EVT_DSS_WDT_DMA_REQ1   28
#define	EDMA_DSS_TPCC_B_EVT_DSS_MCRC_DMA_REQ0   29
#define	EDMA_DSS_TPCC_B_EVT_DSS_MCRC_DMA_REQ1   30
#define	EDMA_DSS_TPCC_B_EVT_FREE_0   31
#define	EDMA_DSS_TPCC_B_EVT_FREE_1   32
#define	EDMA_DSS_TPCC_B_EVT_FREE_2   33
#define	EDMA_DSS_TPCC_B_EVT_FREE_3   34
#define	EDMA_DSS_TPCC_B_EVT_FREE_4   35
#define	EDMA_DSS_TPCC_B_EVT_FREE_5   36
#define	EDMA_DSS_TPCC_B_EVT_FREE_6   37
#define	EDMA_DSS_TPCC_B_EVT_FREE_7   38
#define	EDMA_DSS_TPCC_B_EVT_FREE_8   39
#define	EDMA_DSS_TPCC_B_EVT_FREE_9   40
#define	EDMA_DSS_TPCC_B_EVT_FREE_10   41
#define	EDMA_DSS_TPCC_B_EVT_FREE_11   42
#define	EDMA_DSS_TPCC_B_EVT_FREE_12   43
#define	EDMA_DSS_TPCC_B_EVT_FREE_13   44
#define	EDMA_DSS_TPCC_B_EVT_FREE_14   45
#define	EDMA_DSS_TPCC_B_EVT_FREE_15   46
#define	EDMA_DSS_TPCC_B_EVT_FREE_16   47
#define	EDMA_DSS_TPCC_B_EVT_FREE_17   48
#define	EDMA_DSS_TPCC_B_EVT_FREE_18   49
#define	EDMA_DSS_TPCC_B_EVT_FREE_19   50
#define	EDMA_DSS_TPCC_B_EVT_FREE_20   51
#define	EDMA_DSS_TPCC_B_EVT_FREE_21   52
#define	EDMA_DSS_TPCC_B_EVT_FREE_22   53
#define	EDMA_DSS_TPCC_B_EVT_FREE_23   54
#define	EDMA_DSS_TPCC_B_EVT_FREE_24   55
#define	EDMA_DSS_TPCC_B_EVT_FREE_25   56
#define	EDMA_DSS_TPCC_B_EVT_FREE_26   57
#define	EDMA_DSS_TPCC_B_EVT_FREE_27   58
#define	EDMA_DSS_TPCC_B_EVT_FREE_28   59
#define	EDMA_DSS_TPCC_B_EVT_FREE_29   60
#define	EDMA_DSS_TPCC_B_EVT_FREE_30   61
#define	EDMA_DSS_TPCC_B_EVT_FREE_31   62
#define	EDMA_DSS_TPCC_B_EVT_FREE_32   63
#define	EDMA_APPSS_TPCC_A_NUM_PARAM_SETS   (128U)
#define	EDMA_APPSS_TPCC_A_NUM_DMA_CHANS   (64U)
#define	EDMA_APPSS_TPCC_A_NUM_TC   (2U)
#define	EDMA_DSS_TPCC_A_NUM_PARAM_SETS   (128U)
#define	EDMA_DSS_TPCC_A_NUM_DMA_CHANS   (64U)
#define	EDMA_DSS_TPCC_A_NUM_TC   (3U)
#define	EDMA_DSS_TPCC_B_NUM_PARAM_SETS   (128U)
#define	EDMA_DSS_TPCC_B_NUM_DMA_CHANS   (64U)
#define	EDMA_DSS_TPCC_B_NUM_TC   (2U)
#define	EDMA_TPCC_ERRAGG_TPCC_EERINT__POS   (0U)
#define	EDMA_TPCC_INTAGG_TPCC_INTG__POS   (0U)
#define	EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS   (2U) /* position of the lowest TC Id, others are higher */
#define	EDMA_APPSS_NUM_CC   1
#define	EDMA_APPSS_MAX_NUM_TC   EDMA_APPSS_TPCC_A_NUM_TC
#define	EDMA_DSS_NUM_CC   2
#define	EDMA_DSS_MAX_NUM_TC
#define	HWA_NUM_INSTANCES   (1U)
#define	SOC_HWA_NUM_MEM_BANKS   (4U)
	number of HWA memory banks More...
#define	SOC_HWA_NUM_PARAM_SETS   (32U)
	number of HWA parameter sets More...
#define	SOC_HWA_NUM_DMA_CHANNEL   (16U)
	number of HWA MDA channels More...
#define	SOC_HWA_MEM_SIZE   (CSL_DSS_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS)
	number of HWA memory size in bytes More...
#define	CSL_ARM_R5_CLUSTER_GROUP_ID_0   ((uint32_t) 0x00U)
	R5 Cluster Group ID0. More...
Core IDs of cores or CPUs present on this SOC
#define	CSL_CORE_ID_R5FSS0_0   (0U)
#define	CSL_CORE_ID_HSM_M4   (1U)
#define	CSL_CORE_ID_C66SS0   (2U)
#define	CSL_CORE_ID_MAX   (3U)
Priv ID's of core or CPUs present on this SOC
#define	PRIV_ID_HSMM4   (1U)
#define	PRIV_ID_R5   (2U)
#define	PRIV_ID_DSS   (8U)
#define	PRIV_ID_M3   (6U)

Macro Definition Documentation

CSL_CORE_ID_R5FSS0_0

#define CSL_CORE_ID_R5FSS0_0   (0U)

CSL_CORE_ID_HSM_M4

#define CSL_CORE_ID_HSM_M4   (1U)

CSL_CORE_ID_C66SS0

#define CSL_CORE_ID_C66SS0   (2U)

CSL_CORE_ID_MAX

#define CSL_CORE_ID_MAX   (3U)

PRIV_ID_HSMM4

#define PRIV_ID_HSMM4   (1U)

PRIV_ID_R5

#define PRIV_ID_R5   (2U)

PRIV_ID_DSS

#define PRIV_ID_DSS   (8U)

PRIV_ID_M3

#define PRIV_ID_M3   (6U)

CSL_EPWM_PER_CNT

#define CSL_EPWM_PER_CNT   (1U)

Number of ePWM instances.

SOC_ADCBUF_NUM_RX_CHANNEL

#define SOC_ADCBUF_NUM_RX_CHANNEL   (4U)

ESM_NUM_GROUP_MAX

#define ESM_NUM_GROUP_MAX   (3U)

ESM_NUM_INTR_PER_GROUP

#define ESM_NUM_INTR_PER_GROUP   (128U)

SOC_EDMA_NUM_DMACH

#define SOC_EDMA_NUM_DMACH   (64U)

Number of DMA Channels.

SOC_EDMA_NUM_QDMACH

#define SOC_EDMA_NUM_QDMACH   (8U)

Number of QDMA Channels.

SOC_EDMA_NUM_PARAMSETS

#define SOC_EDMA_NUM_PARAMSETS   (128U)

Number of PaRAM Sets available.

SOC_EDMA_NUM_EVQUE

#define SOC_EDMA_NUM_EVQUE   (2U)

Number of Event Queues available.

SOC_EDMA_CHMAPEXIST

#define SOC_EDMA_CHMAPEXIST   (1U)

Support for Channel to PaRAM Set mapping.

SOC_EDMA_NUM_REGIONS

#define SOC_EDMA_NUM_REGIONS   (8)

Number of EDMA Regions.

SOC_EDMA_MEMPROTECT

#define SOC_EDMA_MEMPROTECT   (1U)

Support for Memory Protection.

MCAN_MSG_RAM_MAX_WORD_COUNT

#define MCAN_MSG_RAM_MAX_WORD_COUNT   (4352U)

MCAN Maximum Message RAM words.

MCAN_MAX_RX_DMA_BUFFERS

#define MCAN_MAX_RX_DMA_BUFFERS   (3U)

Maximum number of Rx Dma buffers.

MCAN_MAX_TX_DMA_BUFFERS

#define MCAN_MAX_TX_DMA_BUFFERS   (3U)

Maximum number of Tx Dma buffers.

EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_RX_REQ   0

APPSS TPCC A EVENT MAP.

EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_TX_REQ   1

EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_RX_REQ   2

EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_TX_REQ   3

EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_RX_REQ   4

EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_TX_REQ   5

EDMA_APPSS_TPCC_A_EVT_LIN_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_EVT_LIN_DMA_RX_REQ   6

EDMA_APPSS_TPCC_A_EVT_LIN_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_EVT_LIN_DMA_TX_REQ   7

EDMA_APPSS_TPCC_A_EVT_MCAN1_DMA_REQ0

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_DMA_REQ0   8

EDMA_APPSS_TPCC_A_EVT_MCAN1_DMA_REQ1

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_DMA_REQ1   9

EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT1

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT1   10

EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT2

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT2   11

EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT3

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT3   12

EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT4

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT4   13

EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT5

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT5   14

EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT6

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT6   15

EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT7

#define EDMA_APPSS_TPCC_A_EVT_MCAN1_FE_INT7   16

EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ0

#define EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ0   17

EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ1

#define EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ1   18

EDMA_APPSS_TPCC_A_GIO_INT0

#define EDMA_APPSS_TPCC_A_GIO_INT0   19

EDMA_APPSS_TPCC_A_GIO_INT1

#define EDMA_APPSS_TPCC_A_GIO_INT1   20

EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ0

#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ0   21

EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ1

#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ1   22

EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ2_AND_MCAN2_FE_INT1

#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ2_AND_MCAN2_FE_INT1   23

EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ3_AND_MCAN2_FE_INT2

#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ3_AND_MCAN2_FE_INT2   24

EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ0_AND_MCAN2_FE_INT3

#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ0_AND_MCAN2_FE_INT3   25

EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ1

#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ1   26

EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ2_AND_MCAN2_FE_INT4

#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ2_AND_MCAN2_FE_INT4   27

EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ3_AND_MCAN2_FE_INT5

#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ3_AND_MCAN2_FE_INT5   28

EDMA_APPSS_TPCC_A_MCRC_DMA_REQ0

#define EDMA_APPSS_TPCC_A_MCRC_DMA_REQ0   29

EDMA_APPSS_TPCC_A_MCRC_DMA_REQ1

#define EDMA_APPSS_TPCC_A_MCRC_DMA_REQ1   30

EDMA_APPSS_TPCC_A_QSPI_DMA_REQ

#define EDMA_APPSS_TPCC_A_QSPI_DMA_REQ   31

EDMA_APPSS_TPCC_A_PWM_DMA_REQ0_AND_MCAN2_FE_INT6

#define EDMA_APPSS_TPCC_A_PWM_DMA_REQ0_AND_MCAN2_FE_INT6   32

EDMA_APPSS_TPCC_A_PWM_DMA_REQ1_AND_MCAN2_FE_INT7

#define EDMA_APPSS_TPCC_A_PWM_DMA_REQ1_AND_MCAN2_FE_INT7   33

EDMA_APPSS_TPCC_A_SCI2_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_SCI2_DMA_RX_REQ   34

EDMA_APPSS_TPCC_A_SCI2_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_SCI2_DMA_TX_REQ   35

EDMA_APPSS_TPCC_A_FRAMETIMER_FRAME_START

#define EDMA_APPSS_TPCC_A_FRAMETIMER_FRAME_START   36

EDMA_APPSS_TPCC_A_CHIRP_AVAIL_IRQ

#define EDMA_APPSS_TPCC_A_CHIRP_AVAIL_IRQ   37

EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_END

#define EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_END   38

EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_START

#define EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_START   39

EDMA_APPSS_TPCC_A_CHIRPTIMER_FRAME_END

#define EDMA_APPSS_TPCC_A_CHIRPTIMER_FRAME_END   40

EDMA_APPSS_TPCC_A_ADC_VALID_START

#define EDMA_APPSS_TPCC_A_ADC_VALID_START   41

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ0

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ0   42

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ1

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ1   43

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ2

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ2   44

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ3_AND_DTHE_SM3_DMA_REQ0

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ3_AND_DTHE_SM3_DMA_REQ0   45

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ4_AND_DTHE_SM3_DMA_REQ1

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ4_AND_DTHE_SM3_DMA_REQ1   46

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ5_AND_DTHE_SM3_DMA_REQ2

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ5_AND_DTHE_SM3_DMA_REQ2   47

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ0

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ0   48

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ1

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ1   49

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ2

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ2   50

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ3

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ3   51

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ4_AND_DTHE_SM4_DMA_REQ0

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ4_AND_DTHE_SM4_DMA_REQ0   52

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ5_AND_DTHE_SM4_DMA_REQ1

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ5_AND_DTHE_SM4_DMA_REQ1   53

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ6_AND_DTHE_SM4_DMA_REQ2

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ6_AND_DTHE_SM4_DMA_REQ2   54

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ7_AND_DTHE_SM4_DMA_REQ3

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ7_AND_DTHE_SM4_DMA_REQ3   55

EDMA_APPSS_TPCC_A_EVT_GPADC_IFM_DONE

#define EDMA_APPSS_TPCC_A_EVT_GPADC_IFM_DONE   56

EDMA_APPSS_TPCC_A_FEC_INTR0

#define EDMA_APPSS_TPCC_A_FEC_INTR0   57

EDMA_APPSS_TPCC_A_FEC_INTR1

#define EDMA_APPSS_TPCC_A_FEC_INTR1   58

EDMA_APPSS_TPCC_A_FEC_INTR2

#define EDMA_APPSS_TPCC_A_FEC_INTR2   59

EDMA_APPSS_TPCC_A_FEC_INTR3

#define EDMA_APPSS_TPCC_A_FEC_INTR3   60

EDMA_APPSS_TPCC_A_EVT_FREE_0

#define EDMA_APPSS_TPCC_A_EVT_FREE_0   61

EDMA_APPSS_TPCC_A_EVT_MCAN2_DMA_REQ0

#define EDMA_APPSS_TPCC_A_EVT_MCAN2_DMA_REQ0   62

EDMA_APPSS_TPCC_A_EVT_MCAN2_DMA_REQ1

#define EDMA_APPSS_TPCC_A_EVT_MCAN2_DMA_REQ1   63

EDMA_DSS_TPCC_A_FRAMETIMER_FRAME_START

#define EDMA_DSS_TPCC_A_FRAMETIMER_FRAME_START   0

DSP TPCC A EVENT MAP.

EDMA_DSS_TPCC_A_CHIRP_AVAIL_IRQ

#define EDMA_DSS_TPCC_A_CHIRP_AVAIL_IRQ   1

EDMA_DSS_TPCC_A_CHIRPTIMER_CHIRP_END

#define EDMA_DSS_TPCC_A_CHIRPTIMER_CHIRP_END   2

EDMA_DSS_TPCC_A_CHIRPTIMER_CHIRP_START

#define EDMA_DSS_TPCC_A_CHIRPTIMER_CHIRP_START   3

EDMA_DSS_TPCC_A_CHIRPTIMER_FRAME_END

#define EDMA_DSS_TPCC_A_CHIRPTIMER_FRAME_END   4

EDMA_DSS_TPCC_A_EVT_ADC_VALID_START

#define EDMA_DSS_TPCC_A_EVT_ADC_VALID_START   5

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_0

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_0   6

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_1

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_1   7

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_2

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_2   8

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_3

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_3   9

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_4

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_4   10

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_5

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_5   11

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_6

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_6   12

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_7

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_7   13

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_8

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_8   14

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_9

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_9   15

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_10

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_10   16

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_11

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_11   17

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_12

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_12   18

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_13

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_13   19

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_14

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_14   20

EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_15

#define EDMA_DSS_TPCC_A_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_15   21

EDMA_DSS_TPCC_A_EVT_HWA_LOOP_INT

#define EDMA_DSS_TPCC_A_EVT_HWA_LOOP_INT   22

EDMA_DSS_TPCC_A_EVT_HWA_PARAMDONE_INT

#define EDMA_DSS_TPCC_A_EVT_HWA_PARAMDONE_INT   23

EDMA_DSS_TPCC_A_EVT_SPI1_DMA_RX_REQ

#define EDMA_DSS_TPCC_A_EVT_SPI1_DMA_RX_REQ   24

EDMA_DSS_TPCC_A_EVT_SPI1_DMA_TX_REQ

#define EDMA_DSS_TPCC_A_EVT_SPI1_DMA_TX_REQ   25

EDMA_DSS_TPCC_A_EVT_SPI2_DMA_RX_REQ

#define EDMA_DSS_TPCC_A_EVT_SPI2_DMA_RX_REQ   26

EDMA_DSS_TPCC_A_EVT_SPI2_DMA_TX_REQ

#define EDMA_DSS_TPCC_A_EVT_SPI2_DMA_TX_REQ   27

EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ0   28

EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ1   29

EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ2

#define EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ2   30

EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ3

#define EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ3   31

EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ4

#define EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ4   32

EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ5

#define EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ5   33

EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ6

#define EDMA_DSS_TPCC_A_EVT_DSS_CBUFF_DMA_REQ6   34

EDMA_DSS_TPCC_A_EVT_DSS_SCIA_RX_DMA_REQ

#define EDMA_DSS_TPCC_A_EVT_DSS_SCIA_RX_DMA_REQ   35

EDMA_DSS_TPCC_A_EVT_DSS_SCIA_TX_DMA_REQ

#define EDMA_DSS_TPCC_A_EVT_DSS_SCIA_TX_DMA_REQ   36

EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ0   37

EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ1   38

EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ2

#define EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ2   39

EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ3

#define EDMA_DSS_TPCC_A_EVT_DSS_RTIA_DMA_REQ3   40

EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ0   41

EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ1   42

EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ2

#define EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ2   43

EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ3

#define EDMA_DSS_TPCC_A_EVT_DSS_WDT_DMA_REQ3   44

EDMA_DSS_TPCC_A_EVT_DSS_MCRC_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_DSS_MCRC_DMA_REQ0   45

EDMA_DSS_TPCC_A_EVT_DSS_MCRC_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_DSS_MCRC_DMA_REQ1   46

EDMA_DSS_TPCC_A_EVT_FREE_0

#define EDMA_DSS_TPCC_A_EVT_FREE_0   47

EDMA_DSS_TPCC_A_EVT_FREE_1

#define EDMA_DSS_TPCC_A_EVT_FREE_1   48

EDMA_DSS_TPCC_A_EVT_FREE_2

#define EDMA_DSS_TPCC_A_EVT_FREE_2   49

EDMA_DSS_TPCC_A_EVT_FREE_3

#define EDMA_DSS_TPCC_A_EVT_FREE_3   50

EDMA_DSS_TPCC_A_EVT_FREE_4

#define EDMA_DSS_TPCC_A_EVT_FREE_4   51

EDMA_DSS_TPCC_A_EVT_FREE_5

#define EDMA_DSS_TPCC_A_EVT_FREE_5   52

EDMA_DSS_TPCC_A_EVT_FREE_6

#define EDMA_DSS_TPCC_A_EVT_FREE_6   53

EDMA_DSS_TPCC_A_EVT_FREE_7

#define EDMA_DSS_TPCC_A_EVT_FREE_7   54

EDMA_DSS_TPCC_A_EVT_FREE_8

#define EDMA_DSS_TPCC_A_EVT_FREE_8   55

EDMA_DSS_TPCC_A_EVT_FREE_9

#define EDMA_DSS_TPCC_A_EVT_FREE_9   56

EDMA_DSS_TPCC_A_EVT_FREE_10

#define EDMA_DSS_TPCC_A_EVT_FREE_10   57

EDMA_DSS_TPCC_A_EVT_FREE_11

#define EDMA_DSS_TPCC_A_EVT_FREE_11   58

EDMA_DSS_TPCC_A_EVT_FREE_12

#define EDMA_DSS_TPCC_A_EVT_FREE_12   59

EDMA_DSS_TPCC_A_EVT_FREE_13

#define EDMA_DSS_TPCC_A_EVT_FREE_13   60

EDMA_DSS_TPCC_A_EVT_FREE_14

#define EDMA_DSS_TPCC_A_EVT_FREE_14   61

EDMA_DSS_TPCC_A_EVT_FREE_15

#define EDMA_DSS_TPCC_A_EVT_FREE_15   62

EDMA_DSS_TPCC_A_EVT_FREE_16

#define EDMA_DSS_TPCC_A_EVT_FREE_16   63

EDMA_DSS_TPCC_B_FRAMETIMER_FRAME_START

#define EDMA_DSS_TPCC_B_FRAMETIMER_FRAME_START   0

DSP TPCC B EVENT MAP.

EDMA_DSS_TPCC_B_CHIRP_AVAIL_IRQ

#define EDMA_DSS_TPCC_B_CHIRP_AVAIL_IRQ   1

EDMA_DSS_TPCC_B_CHIRPTIMER_CHIRP_END

#define EDMA_DSS_TPCC_B_CHIRPTIMER_CHIRP_END   2

EDMA_DSS_TPCC_B_CHIRPTIMER_CHIRP_START

#define EDMA_DSS_TPCC_B_CHIRPTIMER_CHIRP_START   3

EDMA_DSS_TPCC_B_CHIRPTIMER_FRAME_END

#define EDMA_DSS_TPCC_B_CHIRPTIMER_FRAME_END   4

EDMA_DSS_TPCC_B_EVT_ADC_VALID_START

#define EDMA_DSS_TPCC_B_EVT_ADC_VALID_START   5

EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_0

#define EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_0   6

EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_1

#define EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_1   7

EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_2

#define EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_2   8

EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_3

#define EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_3   9

EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_4

#define EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_4   10

EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_5

#define EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_5   11

EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_6

#define EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_6   12

EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_7

#define EDMA_DSS_TPCC_B_EVT_DSS_HW_ACC_CHANNEL_TRIGGER_7   13

EDMA_DSS_TPCC_B_EVT_HWA_LOOP_INT

#define EDMA_DSS_TPCC_B_EVT_HWA_LOOP_INT   14

EDMA_DSS_TPCC_B_EVT_HWA_PARAMDONE_INT

#define EDMA_DSS_TPCC_B_EVT_HWA_PARAMDONE_INT   15

EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ0   16

EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ1   17

EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ2

#define EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ2   18

EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ3

#define EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ3   19

EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ4

#define EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ4   20

EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ5

#define EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ5   21

EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ6

#define EDMA_DSS_TPCC_B_EVT_DSS_CBUFF_DMA_REQ6   22

EDMA_DSS_TPCC_B_EVT_DSS_SCIA_RX_DMA_REQ

#define EDMA_DSS_TPCC_B_EVT_DSS_SCIA_RX_DMA_REQ   23

EDMA_DSS_TPCC_B_EVT_DSS_SCIA_TX_DMA_REQ

#define EDMA_DSS_TPCC_B_EVT_DSS_SCIA_TX_DMA_REQ   24

EDMA_DSS_TPCC_B_EVT_DSS_RTIA_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_DSS_RTIA_DMA_REQ0   25

EDMA_DSS_TPCC_B_EVT_DSS_RTIA_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_DSS_RTIA_DMA_REQ1   26

EDMA_DSS_TPCC_B_EVT_DSS_WDT_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_DSS_WDT_DMA_REQ0   27

EDMA_DSS_TPCC_B_EVT_DSS_WDT_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_DSS_WDT_DMA_REQ1   28

EDMA_DSS_TPCC_B_EVT_DSS_MCRC_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_DSS_MCRC_DMA_REQ0   29

EDMA_DSS_TPCC_B_EVT_DSS_MCRC_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_DSS_MCRC_DMA_REQ1   30

EDMA_DSS_TPCC_B_EVT_FREE_0

#define EDMA_DSS_TPCC_B_EVT_FREE_0   31

EDMA_DSS_TPCC_B_EVT_FREE_1

#define EDMA_DSS_TPCC_B_EVT_FREE_1   32

EDMA_DSS_TPCC_B_EVT_FREE_2

#define EDMA_DSS_TPCC_B_EVT_FREE_2   33

EDMA_DSS_TPCC_B_EVT_FREE_3

#define EDMA_DSS_TPCC_B_EVT_FREE_3   34

EDMA_DSS_TPCC_B_EVT_FREE_4

#define EDMA_DSS_TPCC_B_EVT_FREE_4   35

EDMA_DSS_TPCC_B_EVT_FREE_5

#define EDMA_DSS_TPCC_B_EVT_FREE_5   36

EDMA_DSS_TPCC_B_EVT_FREE_6

#define EDMA_DSS_TPCC_B_EVT_FREE_6   37

EDMA_DSS_TPCC_B_EVT_FREE_7

#define EDMA_DSS_TPCC_B_EVT_FREE_7   38

EDMA_DSS_TPCC_B_EVT_FREE_8

#define EDMA_DSS_TPCC_B_EVT_FREE_8   39

EDMA_DSS_TPCC_B_EVT_FREE_9

#define EDMA_DSS_TPCC_B_EVT_FREE_9   40

EDMA_DSS_TPCC_B_EVT_FREE_10

#define EDMA_DSS_TPCC_B_EVT_FREE_10   41

EDMA_DSS_TPCC_B_EVT_FREE_11

#define EDMA_DSS_TPCC_B_EVT_FREE_11   42

EDMA_DSS_TPCC_B_EVT_FREE_12

#define EDMA_DSS_TPCC_B_EVT_FREE_12   43

EDMA_DSS_TPCC_B_EVT_FREE_13

#define EDMA_DSS_TPCC_B_EVT_FREE_13   44

EDMA_DSS_TPCC_B_EVT_FREE_14

#define EDMA_DSS_TPCC_B_EVT_FREE_14   45

EDMA_DSS_TPCC_B_EVT_FREE_15

#define EDMA_DSS_TPCC_B_EVT_FREE_15   46

EDMA_DSS_TPCC_B_EVT_FREE_16

#define EDMA_DSS_TPCC_B_EVT_FREE_16   47

EDMA_DSS_TPCC_B_EVT_FREE_17

#define EDMA_DSS_TPCC_B_EVT_FREE_17   48

EDMA_DSS_TPCC_B_EVT_FREE_18

#define EDMA_DSS_TPCC_B_EVT_FREE_18   49

EDMA_DSS_TPCC_B_EVT_FREE_19

#define EDMA_DSS_TPCC_B_EVT_FREE_19   50

EDMA_DSS_TPCC_B_EVT_FREE_20

#define EDMA_DSS_TPCC_B_EVT_FREE_20   51

EDMA_DSS_TPCC_B_EVT_FREE_21

#define EDMA_DSS_TPCC_B_EVT_FREE_21   52

EDMA_DSS_TPCC_B_EVT_FREE_22

#define EDMA_DSS_TPCC_B_EVT_FREE_22   53

EDMA_DSS_TPCC_B_EVT_FREE_23

#define EDMA_DSS_TPCC_B_EVT_FREE_23   54

EDMA_DSS_TPCC_B_EVT_FREE_24

#define EDMA_DSS_TPCC_B_EVT_FREE_24   55

EDMA_DSS_TPCC_B_EVT_FREE_25

#define EDMA_DSS_TPCC_B_EVT_FREE_25   56

EDMA_DSS_TPCC_B_EVT_FREE_26

#define EDMA_DSS_TPCC_B_EVT_FREE_26   57

EDMA_DSS_TPCC_B_EVT_FREE_27

#define EDMA_DSS_TPCC_B_EVT_FREE_27   58

EDMA_DSS_TPCC_B_EVT_FREE_28

#define EDMA_DSS_TPCC_B_EVT_FREE_28   59

EDMA_DSS_TPCC_B_EVT_FREE_29

#define EDMA_DSS_TPCC_B_EVT_FREE_29   60

EDMA_DSS_TPCC_B_EVT_FREE_30

#define EDMA_DSS_TPCC_B_EVT_FREE_30   61

EDMA_DSS_TPCC_B_EVT_FREE_31

#define EDMA_DSS_TPCC_B_EVT_FREE_31   62

EDMA_DSS_TPCC_B_EVT_FREE_32

#define EDMA_DSS_TPCC_B_EVT_FREE_32   63

EDMA_APPSS_TPCC_A_NUM_PARAM_SETS

#define EDMA_APPSS_TPCC_A_NUM_PARAM_SETS   (128U)

EDMA_APPSS_TPCC_A_NUM_DMA_CHANS

#define EDMA_APPSS_TPCC_A_NUM_DMA_CHANS   (64U)

EDMA_APPSS_TPCC_A_NUM_TC

#define EDMA_APPSS_TPCC_A_NUM_TC   (2U)

EDMA_DSS_TPCC_A_NUM_PARAM_SETS

#define EDMA_DSS_TPCC_A_NUM_PARAM_SETS   (128U)

EDMA_DSS_TPCC_A_NUM_DMA_CHANS

#define EDMA_DSS_TPCC_A_NUM_DMA_CHANS   (64U)

EDMA_DSS_TPCC_A_NUM_TC

#define EDMA_DSS_TPCC_A_NUM_TC   (3U)

EDMA_DSS_TPCC_B_NUM_PARAM_SETS

#define EDMA_DSS_TPCC_B_NUM_PARAM_SETS   (128U)

EDMA_DSS_TPCC_B_NUM_DMA_CHANS

#define EDMA_DSS_TPCC_B_NUM_DMA_CHANS   (64U)

EDMA_DSS_TPCC_B_NUM_TC

#define EDMA_DSS_TPCC_B_NUM_TC   (2U)

EDMA_TPCC_ERRAGG_TPCC_EERINT__POS

#define EDMA_TPCC_ERRAGG_TPCC_EERINT__POS   (0U)

EDMA_TPCC_INTAGG_TPCC_INTG__POS

#define EDMA_TPCC_INTAGG_TPCC_INTG__POS   (0U)

EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS

#define EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS   (2U) /* position of the lowest TC Id, others are higher */

EDMA_APPSS_NUM_CC

#define EDMA_APPSS_NUM_CC   1

EDMA_APPSS_MAX_NUM_TC

#define EDMA_APPSS_MAX_NUM_TC   EDMA_APPSS_TPCC_A_NUM_TC

EDMA_DSS_NUM_CC

#define EDMA_DSS_NUM_CC   2

EDMA_DSS_MAX_NUM_TC

#define EDMA_DSS_MAX_NUM_TC

Value:

                                CSL_MAX(EDMA_DSS_TPCC_A_NUM_TC, \
                                EDMA_DSS_TPCC_B_NUM_TC)

HWA_NUM_INSTANCES

#define HWA_NUM_INSTANCES   (1U)

SOC_HWA_NUM_MEM_BANKS

#define SOC_HWA_NUM_MEM_BANKS   (4U)

number of HWA memory banks

SOC_HWA_NUM_PARAM_SETS

#define SOC_HWA_NUM_PARAM_SETS   (32U)

number of HWA parameter sets

SOC_HWA_NUM_DMA_CHANNEL

#define SOC_HWA_NUM_DMA_CHANNEL   (16U)

number of HWA MDA channels

SOC_HWA_MEM_SIZE

#define SOC_HWA_MEM_SIZE   (CSL_DSS_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS)

number of HWA memory size in bytes

CSL_ARM_R5_CLUSTER_GROUP_ID_0

#define CSL_ARM_R5_CLUSTER_GROUP_ID_0   ((uint32_t) 0x00U)

R5 Cluster Group ID0.