Collaboration diagram for Direct Memory Access (DMA):

Modules
	DL_DMA_INTERRUPT

	DL_DMA_EVENT

Data Structures
struct	DL_DMA_Config
	Configuration struct for DL_DMA_initChannel. More...

Macros
#define	DEVICE_HAS_DMA_FULL_CHANNEL
	Device has support for DMA FULL channels.

Enumerations
enum	DL_DMA_TRANSFER_MODE { DL_DMA_SINGLE_TRANSFER_MODE = DMA_DMACTL_DMATM_SINGLE, DL_DMA_SINGLE_BLOCK_TRANSFER_MODE = DMA_DMACTL_DMATM_BLOCK, DL_DMA_FULL_CH_REPEAT_SINGLE_TRANSFER_MODE = DMA_DMACTL_DMATM_RPTSNGL, DL_DMA_FULL_CH_REPEAT_BLOCK_TRANSFER_MODE = DMA_DMACTL_DMATM_RPTBLCK }

enum	DL_DMA_EXTENDED_MODE { DL_DMA_NORMAL_MODE = DMA_DMACTL_DMAEM_NORMAL, DL_DMA_FULL_CH_FILL_MODE = DMA_DMACTL_DMAEM_FILLMODE, DL_DMA_FULL_CH_TABLE_MODE = DMA_DMACTL_DMAEM_TABLEMODE }

enum	DL_DMA_INCREMENT { DL_DMA_ADDR_UNCHANGED = DMA_DMACTL_DMASRCINCR_UNCHANGED, DL_DMA_ADDR_DECREMENT = DMA_DMACTL_DMASRCINCR_DECREMENT, DL_DMA_ADDR_INCREMENT = DMA_DMACTL_DMASRCINCR_INCREMENT, DL_DMA_ADDR_STRIDE_2 = DMA_DMACTL_DMASRCINCR_STRIDE_2, DL_DMA_ADDR_STRIDE_3 = DMA_DMACTL_DMASRCINCR_STRIDE_3, DL_DMA_ADDR_STRIDE_4 = DMA_DMACTL_DMASRCINCR_STRIDE_4, DL_DMA_ADDR_STRIDE_5 = DMA_DMACTL_DMASRCINCR_STRIDE_5, DL_DMA_ADDR_STRIDE_6 = DMA_DMACTL_DMASRCINCR_STRIDE_6, DL_DMA_ADDR_STRIDE_7 = DMA_DMACTL_DMASRCINCR_STRIDE_7, DL_DMA_ADDR_STRIDE_8 = DMA_DMACTL_DMASRCINCR_STRIDE_8, DL_DMA_ADDR_STRIDE_9 = DMA_DMACTL_DMASRCINCR_STRIDE_9 }

enum	DL_DMA_EARLY_INTERRUPT_THRESHOLD { DL_DMA_EARLY_INTERRUPT_THRESHOLD_DISABLED = DMA_DMACTL_DMAPREIRQ_PREIRQ_DISABLE, DL_DMA_EARLY_INTERRUPT_THRESHOLD_1 = DMA_DMACTL_DMAPREIRQ_PREIRQ_1, DL_DMA_EARLY_INTERRUPT_THRESHOLD_2 = DMA_DMACTL_DMAPREIRQ_PREIRQ_2, DL_DMA_EARLY_INTERRUPT_THRESHOLD_4 = DMA_DMACTL_DMAPREIRQ_PREIRQ_4, DL_DMA_EARLY_INTERRUPT_THRESHOLD_8 = DMA_DMACTL_DMAPREIRQ_PREIRQ_8, DL_DMA_EARLY_INTERRUPT_THRESHOLD_32 = DMA_DMACTL_DMAPREIRQ_PREIRQ_32, DL_DMA_EARLY_INTERRUPT_THRESHOLD_64 = DMA_DMACTL_DMAPREIRQ_PREIRQ_64, DL_DMA_EARLY_INTERRUPT_THRESHOLD_HALF = DMA_DMACTL_DMAPREIRQ_PREIRQ_HALF }

enum	DL_DMA_BURST_SIZE { DL_DMA_BURST_SIZE_INFINITY = DMA_DMAPRIO_BURSTSZ_INFINITI, DL_DMA_BURST_SIZE_8 = DMA_DMAPRIO_BURSTSZ_BURST_8, DL_DMA_BURST_SIZE_16 = DMA_DMAPRIO_BURSTSZ_BUSRT_16, DL_DMA_BURST_SIZE_32 = DMA_DMAPRIO_BURSTSZ_BURST_32 }

enum	DL_DMA_TRIGGER_TYPE { DL_DMA_TRIGGER_TYPE_INTERNAL = DMA_DMATCTL_DMATINT_INTERNAL, DL_DMA_TRIGGER_TYPE_EXTERNAL = DMA_DMATCTL_DMATINT_EXTERNAL }

enum	DL_DMA_WIDTH { DL_DMA_WIDTH_BYTE = DMA_DMACTL_DMASRCWDTH_BYTE, DL_DMA_WIDTH_HALF_WORD = DMA_DMACTL_DMASRCWDTH_HALF, DL_DMA_WIDTH_WORD = DMA_DMACTL_DMASRCWDTH_WORD, DL_DMA_WIDTH_LONG = DMA_DMACTL_DMASRCWDTH_LONG }

enum	DL_DMA_EVENT_IIDX { DL_DMA_EVENT_IIDX_NO_INTR = DMA_GEN_EVENT_IIDX_STAT_NO_INTR, DL_DMA_EVENT_IIDX_DMACH0 = DMA_GEN_EVENT_IIDX_STAT_DMACH0, DL_DMA_EVENT_IIDX_DMACH1 = DMA_GEN_EVENT_IIDX_STAT_DMACH1, DL_DMA_EVENT_IIDX_DMACH2 = DMA_GEN_EVENT_IIDX_STAT_DMACH2, DL_DMA_EVENT_IIDX_DMACH3 = DMA_GEN_EVENT_IIDX_STAT_DMACH3, DL_DMA_EVENT_IIDX_DMACH4 = DMA_GEN_EVENT_IIDX_STAT_DMACH4, DL_DMA_EVENT_IIDX_DMACH5 = DMA_GEN_EVENT_IIDX_STAT_DMACH5, DL_DMA_EVENT_IIDX_DMACH6 = DMA_GEN_EVENT_IIDX_STAT_DMACH6, DL_DMA_EVENT_IIDX_DMACH7 = DMA_GEN_EVENT_IIDX_STAT_DMACH7, DL_DMA_EVENT_IIDX_DMACH8 = DMA_GEN_EVENT_IIDX_STAT_DMACH8, DL_DMA_EVENT_IIDX_DMACH9 = DMA_GEN_EVENT_IIDX_STAT_DMACH9, DL_DMA_EVENT_IIDX_DMACH10 = DMA_GEN_EVENT_IIDX_STAT_DMACH10, DL_DMA_EVENT_IIDX_DMACH11 = DMA_GEN_EVENT_IIDX_STAT_DMACH11, DL_DMA_EVENT_IIDX_DMACH12 = DMA_GEN_EVENT_IIDX_STAT_DMACH12, DL_DMA_EVENT_IIDX_DMACH13 = DMA_GEN_EVENT_IIDX_STAT_DMACH13, DL_DMA_EVENT_IIDX_DMACH14 = DMA_GEN_EVENT_IIDX_STAT_DMACH14, DL_DMA_EVENT_IIDX_DMACH15 = DMA_GEN_EVENT_IIDX_STAT_DMACH15, DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH0 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH0, DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH1 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH1, DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH2 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH2, DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH3 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH3, DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH4 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH4, DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH5 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH5, DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH6 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH6, DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH7 = DMA_GEN_EVENT_IIDX_STAT_PREIRQCH7, DL_DMA_EVENT_IIDX_ADDR_ERROR = DMA_GEN_EVENT_IIDX_STAT_ADDRERR, DL_DMA_EVENT_IIDX_DATA_ERROR = DMA_GEN_EVENT_IIDX_STAT_DATAERR }

enum	DL_DMA_PUBLISHER_INDEX { DL_DMA_PUBLISHER_INDEX_0 = 0 }

enum	DL_DMA_SUBSCRIBER_INDEX { DL_DMA_SUBSCRIBER_INDEX_0 = 0, DL_DMA_SUBSCRIBER_INDEX_1 = 1 }

Functions
void	DL_DMA_initChannel (DMA_Regs dma, uint8_t channelNum, DL_DMA_Config config)
	Initialize a DMA channel. More...

__STATIC_INLINE void	DL_DMA_configTransfer (DMA_Regs *dma, uint8_t channelNum, DL_DMA_TRANSFER_MODE transferMode, DL_DMA_EXTENDED_MODE extendedMode, DL_DMA_WIDTH srcWidth, DL_DMA_WIDTH destWidth, DL_DMA_INCREMENT srcIncrement, DL_DMA_INCREMENT destIncrement)
	Configure a DMA channel for a transfer. More...

__STATIC_INLINE void	DL_DMA_enableRoundRobinPriority (DMA_Regs *dma)
	Configure the DMA for round-robin priority. More...

__STATIC_INLINE void	DL_DMA_disableRoundRobinPriority (DMA_Regs *dma)
	Disable round-robin priority for the DMA. More...

__STATIC_INLINE bool	DL_DMA_isRoundRobinPriorityEnabled (DMA_Regs *dma)
	Check if round-robin priority is enabled for the DMA. More...

__STATIC_INLINE void	DL_DMA_setBurstSize (DMA_Regs *dma, DL_DMA_BURST_SIZE burstSize)
	Set the burst size for block transfers. More...

__STATIC_INLINE DL_DMA_BURST_SIZE	DL_DMA_getBurstSize (DMA_Regs *dma)
	Get the burst size for block transfers. More...

__STATIC_INLINE void	DL_DMA_enableChannel (DMA_Regs *dma, uint8_t channelNum)
	Enable a DMA channel for transfers. More...

__STATIC_INLINE void	DL_DMA_disableChannel (DMA_Regs *dma, uint8_t channelNum)
	Disable a DMA channel for transfers. More...

__STATIC_INLINE bool	DL_DMA_isChannelEnabled (DMA_Regs *dma, uint8_t channelNum)
	Check if a DMA channel is enabled for transfers. More...

__STATIC_INLINE void	DL_DMA_configMode (DMA_Regs *dma, uint8_t channelNum, DL_DMA_TRANSFER_MODE transferMode, DL_DMA_EXTENDED_MODE extendedMode)
	Configure the mode for a DMA channel. More...

__STATIC_INLINE void	DL_DMA_setTransferMode (DMA_Regs *dma, uint8_t channelNum, DL_DMA_TRANSFER_MODE transferMode)
	Set a DMA channel's transfer mode. More...

__STATIC_INLINE DL_DMA_TRANSFER_MODE	DL_DMA_getTransferMode (DMA_Regs *dma, uint8_t channelNum)
	Get a DMA channel's transfer mode. More...

__STATIC_INLINE void	DL_DMA_setExtendedMode (DMA_Regs *dma, uint8_t channelNum, DL_DMA_EXTENDED_MODE extendedMode)
	Set a DMA channel's extended mode. More...

__STATIC_INLINE DL_DMA_EXTENDED_MODE	DL_DMA_getExtendedMode (DMA_Regs *dma, uint8_t channelNum)
	Get a DMA channel's extended mode. More...

__STATIC_INLINE void	DL_DMA_startTransfer (DMA_Regs *dma, uint8_t channelNum)
	Start a DMA transfer using software. More...

__STATIC_INLINE void	DL_DMA_setTrigger (DMA_Regs *dma, uint8_t channelNum, uint8_t trigger, DL_DMA_TRIGGER_TYPE triggerType)
	Set a channel's trigger for a DMA transfer. More...

__STATIC_INLINE uint32_t	DL_DMA_getTrigger (DMA_Regs *dma, uint8_t channelNum)
	Get the current trigger for a DMA channel. More...

__STATIC_INLINE DL_DMA_TRIGGER_TYPE	DL_DMA_getTriggerType (DMA_Regs *dma, uint8_t channelNum)
	Get the current trigger type for a DMA channel. More...

__STATIC_INLINE void	DL_DMA_setSrcAddr (DMA_Regs *dma, uint8_t channelNum, uint32_t srcAddr)
	Set a DMA channel's source address. More...

__STATIC_INLINE uint32_t	DL_DMA_getSrcAddr (DMA_Regs *dma, uint8_t channelNum)
	Get a DMA channel's source address. More...

__STATIC_INLINE void	DL_DMA_setDestAddr (DMA_Regs *dma, uint8_t channelNum, uint32_t destAddr)
	Set a DMA channel's destination address. More...

__STATIC_INLINE uint32_t	DL_DMA_getDestAddr (DMA_Regs *dma, uint8_t channelNum)
	Get a DMA channel's destination address. More...

__STATIC_INLINE void	DL_DMA_setTransferSize (DMA_Regs *dma, uint8_t channelNum, uint16_t size)
	Set the size of a block for a DMA transfer. More...

__STATIC_INLINE uint16_t	DL_DMA_getTransferSize (DMA_Regs *dma, uint8_t channelNum)
	Get a channel's size of block of data for a DMA transfer. More...

__STATIC_INLINE void	DL_DMA_setSrcIncrement (DMA_Regs *dma, uint8_t channelNum, DL_DMA_INCREMENT srcIncrement)
	Set a channel's source address increment amount. More...

__STATIC_INLINE DL_DMA_INCREMENT	DL_DMA_getSrcIncrement (DMA_Regs *dma, uint8_t channelNum)
	Return a channel's source address increment amount. More...

__STATIC_INLINE void	DL_DMA_setDestIncrement (DMA_Regs *dma, uint8_t channelNum, DL_DMA_INCREMENT destIncrement)
	Set a channel's destination address increment amount. More...

__STATIC_INLINE DL_DMA_INCREMENT	DL_DMA_getDestIncrement (DMA_Regs *dma, uint8_t channelNum)
	Return a channel's destination address increment amount. More...

__STATIC_INLINE void	DL_DMA_setSrcWidth (DMA_Regs *dma, uint8_t channelNum, DL_DMA_WIDTH srcWidth)
	Set the width of the DMA source address for a channel. More...

__STATIC_INLINE DL_DMA_WIDTH	DL_DMA_getSrcWidth (DMA_Regs *dma, uint8_t channelNum)
	Get the width of the DMA source address for a channel. More...

__STATIC_INLINE void	DL_DMA_setDestWidth (DMA_Regs *dma, uint8_t channelNum, DL_DMA_WIDTH destWidth)
	Set the width of the DMA destination address for a channel. More...

__STATIC_INLINE DL_DMA_WIDTH	DL_DMA_getDestWidth (DMA_Regs *dma, uint8_t channelNum)
	Get the width of the DMA destination address for a channel. More...

__STATIC_INLINE void	DL_DMA_Full_Ch_setEarlyInterruptThreshold (DMA_Regs *dma, uint8_t channelNum, DL_DMA_EARLY_INTERRUPT_THRESHOLD threshold)
	Set the early interrupt event. More...

__STATIC_INLINE DL_DMA_EARLY_INTERRUPT_THRESHOLD	DL_DMA_Full_Ch_getEarlyInterruptThreshold (DMA_Regs *dma, uint8_t channelNum)
	Get the early interrupt event threshold. More...

__STATIC_INLINE void	DL_DMA_enableInterrupt (DMA_Regs *dma, uint32_t interruptMask)
	Enable DMA interrupts. More...

__STATIC_INLINE void	DL_DMA_disableInterrupt (DMA_Regs *dma, uint32_t interruptMask)
	Disable DMA interrupts. More...

__STATIC_INLINE uint32_t	DL_DMA_getEnabledInterrupts (DMA_Regs *dma, uint32_t interruptMask)
	Check which DMA interrupts are enabled. More...

__STATIC_INLINE uint32_t	DL_DMA_getEnabledInterruptStatus (DMA_Regs *dma, uint32_t interruptMask)
	Check interrupt flag of enabled DMA interrupts. More...

__STATIC_INLINE uint32_t	DL_DMA_getRawInterruptStatus (DMA_Regs *dma, uint32_t interruptMask)
	Check interrupt flag of any DMA interrupt. More...

__STATIC_INLINE DL_DMA_EVENT_IIDX	DL_DMA_getPendingInterrupt (DMA_Regs *dma)
	Get highest priority pending DMA interrupt. More...

__STATIC_INLINE void	DL_DMA_clearInterruptStatus (DMA_Regs *dma, uint32_t interruptMask)
	Clear pending DMA interrupts. More...

__STATIC_INLINE void	DL_DMA_setPublisherChanID (DMA_Regs *dma, DL_DMA_PUBLISHER_INDEX index, uint8_t chanID)
	Sets the event publisher channel id. More...

__STATIC_INLINE uint8_t	DL_DMA_getPublisherChanID (DMA_Regs *dma, DL_DMA_PUBLISHER_INDEX index)
	Gets the event publisher channel id. More...

__STATIC_INLINE void	DL_DMA_setSubscriberChanID (DMA_Regs *dma, DL_DMA_SUBSCRIBER_INDEX index, uint8_t chanID)
	Sets the event subscriber channel id. More...

__STATIC_INLINE uint8_t	DL_DMA_getSubscriberChanID (DMA_Regs *dma, DL_DMA_SUBSCRIBER_INDEX index)
	Gets the event subscriber channel id. More...

__STATIC_INLINE void	DL_DMA_enableEvent (DMA_Regs *dma, uint32_t eventMask)
	Enable DMA event. More...

__STATIC_INLINE void	DL_DMA_disableEvent (DMA_Regs *dma, uint32_t eventMask)
	Disable DMA event. More...

__STATIC_INLINE uint32_t	DL_DMA_getEnabledEvents (DMA_Regs *dma, uint32_t eventMask)
	Check which dma events triggers are enabled. More...

__STATIC_INLINE uint32_t	DL_DMA_getEnabledEventStatus (DMA_Regs *dma, uint32_t eventMask)
	Check event flag of enabled dma event. More...

__STATIC_INLINE uint32_t	DL_DMA_getRawEventsStatus (DMA_Regs *dma, uint32_t eventMask)
	Check event flag of any dma event. More...

__STATIC_INLINE void	DL_DMA_clearEventsStatus (DMA_Regs *dma, uint32_t eventMask)
	Clear pending dma events. More...

Detailed Description

Overview

The Direct Memory Access (DMA) Library allows full configuration of the MSPM0 DMA module. The DMA controller transfers data from one address to another, without CPU intervention, across the entire address range. DMA controllers have multiple channels that can be configured independently

Enumeration Type Documentation

§ DL_DMA_TRANSFER_MODE

enum DL_DMA_TRANSFER_MODE

Enumerator
DL_DMA_SINGLE_TRANSFER_MODE	Each DMA trigger results in a single data transfer, once
DL_DMA_SINGLE_BLOCK_TRANSFER_MODE	Each DMA trigger results in a transfer of a block of data, once
DL_DMA_FULL_CH_REPEAT_SINGLE_TRANSFER_MODE	Available for FULL-channel configuration only. Each DMA trigger results in a single data transfer, repeating
DL_DMA_FULL_CH_REPEAT_BLOCK_TRANSFER_MODE	Available for FULL-channel configuration only. Each DMA trigger results in a transfer of a block of data, repeating

§ DL_DMA_EXTENDED_MODE

enum DL_DMA_EXTENDED_MODE

Enumerator
DL_DMA_NORMAL_MODE	Normal operation
DL_DMA_FULL_CH_FILL_MODE	Available for FULL-channel configuration only. Fills the destination with a specific value
DL_DMA_FULL_CH_TABLE_MODE	Available for FULL-channel configuration only. The source data contains addresses and data

§ DL_DMA_INCREMENT

enum DL_DMA_INCREMENT

Enumerator
DL_DMA_ADDR_UNCHANGED	Do not change address after each transfer
DL_DMA_ADDR_DECREMENT	Decrement address by 1 * DL_DMA_WIDTH after each transfer
DL_DMA_ADDR_INCREMENT	Increment address by 1 * DL_DMA_WIDTH after each transfer
DL_DMA_ADDR_STRIDE_2	Stride mode 2, increment address by 2 * DL_DMA_WIDTH (skip over every other element)
DL_DMA_ADDR_STRIDE_3	Stride mode 3, increment address by 3 * DL_DMA_WIDTH (skip over two elements
DL_DMA_ADDR_STRIDE_4	Stride mode 4, increment address by 4 * DL_DMA_WIDTH (skip over three elements
DL_DMA_ADDR_STRIDE_5	Stride mode 5, increment address by 5 * DL_DMA_WIDTH (skip over four elements
DL_DMA_ADDR_STRIDE_6	Stride mode 6, increment address by 6 * DL_DMA_WIDTH (skip over five elements
DL_DMA_ADDR_STRIDE_7	Stride mode 7, increment address by 7 * DL_DMA_WIDTH (skip over six elements
DL_DMA_ADDR_STRIDE_8	Stride mode 8, increment address by 8 * DL_DMA_WIDTH (skip over seven elements
DL_DMA_ADDR_STRIDE_9	Stride mode 9, increment address by 9 * DL_DMA_WIDTH (skip over eight elements

§ DL_DMA_EARLY_INTERRUPT_THRESHOLD

enum DL_DMA_EARLY_INTERRUPT_THRESHOLD

Enumerator
DL_DMA_EARLY_INTERRUPT_THRESHOLD_DISABLED	Disable early interrupt events
DL_DMA_EARLY_INTERRUPT_THRESHOLD_1	Generate Early-IRQ event with one transfer pending (DMASZ=1)
DL_DMA_EARLY_INTERRUPT_THRESHOLD_2	Generate Early-IRQ event with two transfers pending (DMASZ=2)
DL_DMA_EARLY_INTERRUPT_THRESHOLD_4	Generate Early-IRQ event with three transfers pending (DMASZ=4)
DL_DMA_EARLY_INTERRUPT_THRESHOLD_8	Generate Early-IRQ event with eight transfers pending (DMASZ=8)
DL_DMA_EARLY_INTERRUPT_THRESHOLD_32	Generate Early-IRQ event with 32 transfers pending (DMASZ=32)
DL_DMA_EARLY_INTERRUPT_THRESHOLD_64	Generate Early-IRQ event with 64 transfers pending (DMASZ=64)
DL_DMA_EARLY_INTERRUPT_THRESHOLD_HALF	Generate Early-IRQ event when DMASZ reaches the half size point of the original transfer size

§ DL_DMA_BURST_SIZE

enum DL_DMA_BURST_SIZE

Enumerator
DL_DMA_BURST_SIZE_INFINITY	No burst interruption. The block transfer always transfers all elements defined in the DMASZ register before priority is newly evaluated
DL_DMA_BURST_SIZE_8	Burst size of a block transfer is 8
DL_DMA_BURST_SIZE_16	Burst size of a block transfer is 16
DL_DMA_BURST_SIZE_32	Burst size of a block transfer is 32

§ DL_DMA_TRIGGER_TYPE

enum DL_DMA_TRIGGER_TYPE

Enumerator
DL_DMA_TRIGGER_TYPE_INTERNAL	Internal DMA channel is selected as the DMA trigger
DL_DMA_TRIGGER_TYPE_EXTERNAL	External DMA channel is selected as the DMA trigger

§ DL_DMA_WIDTH

enum DL_DMA_WIDTH

Enumerator
DL_DMA_WIDTH_BYTE	Byte Acccess (8-bit)
DL_DMA_WIDTH_HALF_WORD	Half Word Acccess (16-bit)
DL_DMA_WIDTH_WORD	Word Acccess (32-bit)
DL_DMA_WIDTH_LONG	Long Acccess (64-bit)

§ DL_DMA_EVENT_IIDX

enum DL_DMA_EVENT_IIDX

Enumerator
DL_DMA_EVENT_IIDX_NO_INTR	Enum to indicate that no DMA event has taken place
DL_DMA_EVENT_IIDX_DMACH0	Enum to indicate that the channel 0 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH1	Enum to indicate that the channel 1 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH2	Enum to indicate that the channel 2 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH3	Enum to indicate that the channel 3 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH4	Enum to indicate that the channel 4 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH5	Enum to indicate that the channel 5 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH6	Enum to indicate that the channel 6 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH7	Enum to indicate that the channel 7 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH8	Enum to indicate that the channel 8 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH9	Enum to indicate that the channel 9 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH10	Enum to indicate that the channel 10 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH11	Enum to indicate that the channel 11 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH12	Enum to indicate that the channel 12 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH13	Enum to indicate that the channel 13 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH14	Enum to indicate that the channel 14 interrupt has fired
DL_DMA_EVENT_IIDX_DMACH15	Enum to indicate that the channel 15 interrupt has fired
DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH0	Available for FULL-channel configuration only. Enum to indicate that the early interrupt event for channel 0 interrupt has fired
DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH1	Available for FULL-channel configuration only. Enum to indicate that the early interrupt event for channel 1 interrupt has fired
DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH2	Available for FULL-channel configuration only. Enum to indicate that the early interrupt event for channel 2 interrupt has fired
DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH3	Available for FULL-channel configuration only. Enum to indicate that the early interrupt event for channel 3 interrupt has fired
DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH4	Available for FULL-channel configuration only. Enum to indicate that the early interrupt event for channel 4 interrupt has fired
DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH5	Available for FULL-channel configuration only. Enum to indicate that the early interrupt event for channel 5 interrupt has fired
DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH6	Available for FULL-channel configuration only. Enum to indicate that the early interrupt event for channel 6 interrupt has fired
DL_DMA_FULL_CH_EVENT_IIDX_EARLY_IRQ_DMACH7	Available for FULL-channel configuration only. Enum to indicate that the early interrupt event for channel 7 interrupt has fired
DL_DMA_EVENT_IIDX_ADDR_ERROR	Enum to indicate that a DMA address error has occurred
DL_DMA_EVENT_IIDX_DATA_ERROR	Enum to indicate that a DMA data error has occurred

§ DL_DMA_PUBLISHER_INDEX

enum DL_DMA_PUBLISHER_INDEX

Enumerator
DL_DMA_PUBLISHER_INDEX_0	DMA Publisher index 0

§ DL_DMA_SUBSCRIBER_INDEX

enum DL_DMA_SUBSCRIBER_INDEX

Enumerator
DL_DMA_SUBSCRIBER_INDEX_0	DMA Subscriber index 0
DL_DMA_SUBSCRIBER_INDEX_1	DMA Subscriber index 1

Function Documentation

§ DL_DMA_initChannel()

void DL_DMA_initChannel	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_Config *	config
	)

Initialize a DMA channel.

Initializes all the configurable options for a DMA channel. The DMA channel is not enabled in this API.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	config	Pointer to DMA channel configuration settings

§ DL_DMA_configTransfer()

__STATIC_INLINE void DL_DMA_configTransfer	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_TRANSFER_MODE	transferMode,
		DL_DMA_EXTENDED_MODE	extendedMode,
		DL_DMA_WIDTH	srcWidth,
		DL_DMA_WIDTH	destWidth,
		DL_DMA_INCREMENT	srcIncrement,
		DL_DMA_INCREMENT	destIncrement
	)

Configure a DMA channel for a transfer.

Configures the transfer settings for a DMA channel. The DMA channel is not enabled in this API.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	transferMode	The transfer mode to use. Refer to the device datasheet to determine which modes are supported in the selected channel. One of DL_DMA_TRANSFER_MODE.
[in]	extendedMode	The extended mode to use. One of DL_DMA_EXTENDED_MODE.
[in]	srcWidth	The width of the DMA source. One of DL_DMA_WIDTH.
[in]	destWidth	The width of the DMA destination. One of DL_DMA_WIDTH.
[in]	srcIncrement	Amount to increment/decrement the DMA source address by. One of DL_DMA_INCREMENT.
[in]	destIncrement	Amount to increment/decrement the DMA destination address by. One of DL_DMA_INCREMENT.

§ DL_DMA_enableRoundRobinPriority()

__STATIC_INLINE void DL_DMA_enableRoundRobinPriority ( DMA_Regs * dma )

Configure the DMA for round-robin priority.

When round-robin priority is enabled, the channel that completes a transfer becomes the lowest priority. If multiple triggers happen simultaneously or are pending, the channel that transferred least recently will transfer first. Once it's complete the next highest priority channel will transfer.

Parameters

[in] dma Pointer to the register overlay for the peripheral

§ DL_DMA_disableRoundRobinPriority()

__STATIC_INLINE void DL_DMA_disableRoundRobinPriority ( DMA_Regs * dma )

Disable round-robin priority for the DMA.

When round-robin priority is disabled, the channel priorities are fixed in ascending order (Channel 0 is the lowed priority). If multiple triggers happen simultaneously or are pending, the channel with the highest priority completes its transfer before the next-highest transfer can start.

Parameters

[in] dma Pointer to the register overlay for the peripheral

§ DL_DMA_isRoundRobinPriorityEnabled()

__STATIC_INLINE bool DL_DMA_isRoundRobinPriorityEnabled ( DMA_Regs * dma )

Check if round-robin priority is enabled for the DMA.

Parameters

[in] dma Pointer to the register overlay for the peripheral

Returns: The status of round-robin priority

Return values

true	Round-robin priority is enabled
false	Round-robin priority is disabled

§ DL_DMA_setBurstSize()

__STATIC_INLINE void DL_DMA_setBurstSize	(	DMA_Regs *	dma,
		DL_DMA_BURST_SIZE	burstSize
	)

Set the burst size for block transfers.

After the DMA transfers the amount of transfers defined by DL_DMA_BURST_SIZE, the ongoing block transfer is interrupted and the priority encoder has the chance to assign a higher priority channel. The previously interrupted block transfer is internally marked as pending and when no other high priority channel is pending the block transfer will continue with the next burst or until DMASZ counts down to 0.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	burstSize	The burst size to set. One of DL_DMA_BURST_SIZE.

See also: DL_DMA_configTransfer

References DL_Common_updateReg().

§ DL_DMA_getBurstSize()

__STATIC_INLINE DL_DMA_BURST_SIZE DL_DMA_getBurstSize ( DMA_Regs * dma )

Get the burst size for block transfers.

Parameters

[in] dma Pointer to the register overlay for the peripheral

Returns: The burst size for block transfers

Return values

One	of DL_DMA_BURST_SIZE

§ DL_DMA_enableChannel()

__STATIC_INLINE void DL_DMA_enableChannel	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Enable a DMA channel for transfers.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

§ DL_DMA_disableChannel()

__STATIC_INLINE void DL_DMA_disableChannel	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Disable a DMA channel for transfers.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

§ DL_DMA_isChannelEnabled()

__STATIC_INLINE bool DL_DMA_isChannelEnabled	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Check if a DMA channel is enabled for transfers.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The status of the DMA channel

Return values

true	The DMA channel is enabled
false	The DMA channel is disabled

§ DL_DMA_configMode()

__STATIC_INLINE void DL_DMA_configMode	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_TRANSFER_MODE	transferMode,
		DL_DMA_EXTENDED_MODE	extendedMode
	)

Configure the mode for a DMA channel.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	transferMode	The transfer mode to set for the channel. Refer to the device datasheet to determine which modes are supported in the selected channel. One of DL_DMA_TRANSFER_MODE.
[in]	extendedMode	The extended operation mode to set for the channel. One of DL_DMA_EXTENDED_MODE.

See also: DL_DMA_configTransfer

References DL_Common_updateReg().

§ DL_DMA_setTransferMode()

__STATIC_INLINE void DL_DMA_setTransferMode	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_TRANSFER_MODE	transferMode
	)

Set a DMA channel's transfer mode.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	transferMode	The transfer mode to use. Refer to the device datasheet to determine which modes are supported in the selected channel. One of DL_DMA_TRANSFER_MODE.

See also: DL_DMA_configMode; DL_DMA_configTransfer

References DL_Common_updateReg().

§ DL_DMA_getTransferMode()

__STATIC_INLINE DL_DMA_TRANSFER_MODE DL_DMA_getTransferMode	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get a DMA channel's transfer mode.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The channel's transfer mode

Return values

One	of DL_DMA_TRANSFER_MODE

§ DL_DMA_setExtendedMode()

__STATIC_INLINE void DL_DMA_setExtendedMode	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_EXTENDED_MODE	extendedMode
	)

Set a DMA channel's extended mode.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	extendedMode	The transfer mode to use. One of DL_DMA_EXTENDED_MODE.

See also: DL_DMA_configMode; DL_DMA_configTransfer

References DL_Common_updateReg().

§ DL_DMA_getExtendedMode()

__STATIC_INLINE DL_DMA_EXTENDED_MODE DL_DMA_getExtendedMode	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get a DMA channel's extended mode.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The channel's transfer mode

Return values

One	of DL_DMA_EXTENDED_MODE

§ DL_DMA_startTransfer()

__STATIC_INLINE void DL_DMA_startTransfer	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Start a DMA transfer using software.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

§ DL_DMA_setTrigger()

__STATIC_INLINE void DL_DMA_setTrigger	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		uint8_t	trigger,
		DL_DMA_TRIGGER_TYPE	triggerType
	)

Set a channel's trigger for a DMA transfer.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	trigger	What should trigger a DMA transfer. Refer to the datasheet of the device for which DMA trigger values map to which events.
[in]	triggerType	Whether an internal or external DMA channel is selected as the DMA trigger. Refer to the datasheet for more information on the DMA channels.

References DL_Common_updateReg().

§ DL_DMA_getTrigger()

__STATIC_INLINE uint32_t DL_DMA_getTrigger	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get the current trigger for a DMA channel.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: What is configured to trigger a DMA transfer.

Return values

Check the device datasheet for what values are mapped to on your device.

§ DL_DMA_getTriggerType()

__STATIC_INLINE DL_DMA_TRIGGER_TYPE DL_DMA_getTriggerType	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get the current trigger type for a DMA channel.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: Whether an internal or external DMA channel is selected as the DMA trigger.

Return values

One	of DL_DMA_TRIGGER_TYPE

§ DL_DMA_setSrcAddr()

__STATIC_INLINE void DL_DMA_setSrcAddr	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		uint32_t	srcAddr
	)

Set a DMA channel's source address.

Set the source address for a DMA channel for transferring data from. This address can be automatically incremented/decremented after the completion of a transfer by using the DL_DMA_setSrcIncrement function.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	srcAddr	Address to set as the DMA source

See also: DL_DMA_setSrcIncrement

§ DL_DMA_getSrcAddr()

__STATIC_INLINE uint32_t DL_DMA_getSrcAddr	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get a DMA channel's source address.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: Source address for the DMA channel

§ DL_DMA_setDestAddr()

__STATIC_INLINE void DL_DMA_setDestAddr	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		uint32_t	destAddr
	)

Set a DMA channel's destination address.

Set the destination address for a DMA channel for transferring data to. This address can be automatically incremented/decremented after the completion of a transfer by using the DL_DMA_setDestIncrement function.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	destAddr	Address to set as the DMA destination

See also: DL_DMA_setDestIncrement

§ DL_DMA_getDestAddr()

__STATIC_INLINE uint32_t DL_DMA_getDestAddr	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get a DMA channel's destination address.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: Destination address for the DMA channel

§ DL_DMA_setTransferSize()

__STATIC_INLINE void DL_DMA_setTransferSize	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		uint16_t	size
	)

Set the size of a block for a DMA transfer.

Defines the size of the block of data to transfer.

When the transfer mode DL_DMA_TRANSFER_MODE is a Block transfer mode, this is the size of the block of data transferred every trigger.

When in the transfer mode DL_DMA_TRANSFER_MODE is a Single transfer mode, this is how many triggers need to occur before the block is considered done, which then sets the interrupt status.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	size	The size of the block of data to transfer. Value between 0 - 65535.

§ DL_DMA_getTransferSize()

__STATIC_INLINE uint16_t DL_DMA_getTransferSize	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get a channel's size of block of data for a DMA transfer.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The channel's size of block of data to transfer

Return values

A	value between 0 - 65535.

§ DL_DMA_setSrcIncrement()

__STATIC_INLINE void DL_DMA_setSrcIncrement	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_INCREMENT	srcIncrement
	)

Set a channel's source address increment amount.

After each DMA transfer the channel source address, which can be set by DL_DMA_setSrcAddr, can be incremented, decremented or remain unchanged. This controls if the DMA is copying from a fixed address or a block of addresses.

The amount that is incremented/decremented is controlled by the width of the source, set by DL_DMA_setSrcWidth.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	srcIncrement	Amount to increment/decrement the DMA source address by. One of DL_DMA_INCREMENT.

See also: DL_DMA_configTransfer; DL_DMA_setSrcAddr; DL_DMA_setSrcWidth

References DL_Common_updateReg().

§ DL_DMA_getSrcIncrement()

__STATIC_INLINE DL_DMA_INCREMENT DL_DMA_getSrcIncrement	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Return a channel's source address increment amount.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The source address increment amount for selected channel

Return values

One	of DL_DMA_INCREMENT.

§ DL_DMA_setDestIncrement()

__STATIC_INLINE void DL_DMA_setDestIncrement	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_INCREMENT	destIncrement
	)

Set a channel's destination address increment amount.

After each DMA transfer the channel destination address, which can be set by DL_DMA_setDestAddr, can be incremented, decremented or remain unchanged. This controls if the DMA is copying from a fixed address or a block of addresses.

The amount that is incremented/decremented is controlled by the width of the destination, set by DL_DMA_setDestWidth.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	destIncrement	Amount to increment/decrement the DMA destination address by. One of DL_DMA_INCREMENT.

See also: DL_DMA_configTransfer; DL_DMA_setDestAddr; DL_DMA_setDestWidth

References DL_Common_updateReg().

§ DL_DMA_getDestIncrement()

__STATIC_INLINE DL_DMA_INCREMENT DL_DMA_getDestIncrement	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Return a channel's destination address increment amount.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The destination address increment amount for selected channel

Return values

One	of DL_DMA_INCREMENT.

§ DL_DMA_setSrcWidth()

__STATIC_INLINE void DL_DMA_setSrcWidth	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_WIDTH	srcWidth
	)

Set the width of the DMA source address for a channel.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	srcWidth	The width of the DMA source. One of DL_DMA_WIDTH.

See also: DL_DMA_configTransfer

References DL_Common_updateReg().

§ DL_DMA_getSrcWidth()

__STATIC_INLINE DL_DMA_WIDTH DL_DMA_getSrcWidth	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get the width of the DMA source address for a channel.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The width of the DMA source for selected channel

Return values

One	of DL_DMA_WIDTH.

§ DL_DMA_setDestWidth()

__STATIC_INLINE void DL_DMA_setDestWidth	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_WIDTH	destWidth
	)

Set the width of the DMA destination address for a channel.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	destWidth	The width of the DMA destination. One of DL_DMA_WIDTH.

See also: DL_DMA_configTransfer

References DL_Common_updateReg().

§ DL_DMA_getDestWidth()

__STATIC_INLINE DL_DMA_WIDTH DL_DMA_getDestWidth	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get the width of the DMA destination address for a channel.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The width of the DMA destination for selected channel

Return values

One	of DL_DMA_WIDTH.

§ DL_DMA_Full_Ch_setEarlyInterruptThreshold()

__STATIC_INLINE void DL_DMA_Full_Ch_setEarlyInterruptThreshold	(	DMA_Regs *	dma,
		uint8_t	channelNum,
		DL_DMA_EARLY_INTERRUPT_THRESHOLD	threshold
	)

Set the early interrupt event.

This functionality is available for FULL-channel configuration only. Please refer to the device datasheet to map which channels have FULL or BASIC capability.

The DMA has the capability to generate an early interrupt with a given amount of transfer cycles before the DMA complete-interrupt is issued. This allows to start the ISR context switch in parallel with the completion of the DMA, and compensates the latency for the task switch into the ISR.

Ideally when the ISR starts to execute and read IIDX, the IIDX will already point to the channel-complete interrupt (always higher priority than the PRE-IRQ). In this case the latency is minimal and the ISR needs to clear the PRE-IRQ interrupt flag (RIS) manually. Should for whatever reason the DMA not complete in time, the IIDX will point to the PRE-IRQ handler and the handler needs to poll for the DMAEN bit in the DMA channel control register (DMACTL) to catch the moment that the DMA transfer has completed. Then the handler needs to clear the DMA channel-complete IRQ flag manually.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on
[in]	threshold	When to generate the early interrupt. One of DL_DMA_EARLY_INTERRUPT_THRESHOLD.

References DL_Common_updateReg().

§ DL_DMA_Full_Ch_getEarlyInterruptThreshold()

__STATIC_INLINE DL_DMA_EARLY_INTERRUPT_THRESHOLD DL_DMA_Full_Ch_getEarlyInterruptThreshold	(	DMA_Regs *	dma,
		uint8_t	channelNum
	)

Get the early interrupt event threshold.

This functionality is available for FULL-channel configuration only. Please refer to the device datasheet to map which channels have FULL or BASIC capability.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	channelNum	DMA channel to operate on

Returns: The early interrupt event threshold

Return values

One	of DL_DMA_EARLY_INTERRUPT_THRESHOLD.

§ DL_DMA_enableInterrupt()

__STATIC_INLINE void DL_DMA_enableInterrupt	(	DMA_Regs *	dma,
		uint32_t	interruptMask
	)

Enable DMA interrupts.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	interruptMask	Bit mask of interrupts to enable. Bitwise OR of DL_DMA_INTERRUPT.

§ DL_DMA_disableInterrupt()

__STATIC_INLINE void DL_DMA_disableInterrupt	(	DMA_Regs *	dma,
		uint32_t	interruptMask
	)

Disable DMA interrupts.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	interruptMask	Bit mask of interrupts to disable. Bitwise OR of DL_DMA_INTERRUPT.

§ DL_DMA_getEnabledInterrupts()

__STATIC_INLINE uint32_t DL_DMA_getEnabledInterrupts	(	DMA_Regs *	dma,
		uint32_t	interruptMask
	)

Check which DMA interrupts are enabled.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	interruptMask	Bit mask of interrupts to check. Bitwise OR of DL_DMA_INTERRUPT.

Returns: Which of the requested DMA interrupts are enabled

Return values

Bitwise OR of DL_DMA_INTERRUPT values

§ DL_DMA_getEnabledInterruptStatus()

__STATIC_INLINE uint32_t DL_DMA_getEnabledInterruptStatus	(	DMA_Regs *	dma,
		uint32_t	interruptMask
	)

Check interrupt flag of enabled DMA interrupts.

Checks if any of the DMA interrupts that were previously enabled are pending.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	interruptMask	Bit mask of interrupts to check. Bitwise OR of DL_DMA_INTERRUPT.

Returns: Which of the requested DMA interrupts are pending

Return values

Bitwise OR of DL_DMA_INTERRUPT values

See also: DL_DMA_enableInterrupt

§ DL_DMA_getRawInterruptStatus()

__STATIC_INLINE uint32_t DL_DMA_getRawInterruptStatus	(	DMA_Regs *	dma,
		uint32_t	interruptMask
	)

Check interrupt flag of any DMA interrupt.

Checks if any of the DMA interrupts are pending. Interrupts do not have to be previously enabled.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	interruptMask	Bit mask of interrupts to check. Bitwise OR of DL_DMA_INTERRUPT.

Returns: Which of the requested DMA interrupts are pending

Return values

Bitwise OR of DL_DMA_INTERRUPT values

§ DL_DMA_getPendingInterrupt()

__STATIC_INLINE DL_DMA_EVENT_IIDX DL_DMA_getPendingInterrupt ( DMA_Regs * dma )

Get highest priority pending DMA interrupt.

Checks if any of the DMA interrupts are pending. Interrupts do not have to be previously enabled.

Parameters

[in] dma Pointer to the register overlay for the peripheral

Returns: The highest priority pending DMA interrupt

Return values

One	of DL_DMA_EVENT_IIDX

§ DL_DMA_clearInterruptStatus()

__STATIC_INLINE void DL_DMA_clearInterruptStatus	(	DMA_Regs *	dma,
		uint32_t	interruptMask
	)

Clear pending DMA interrupts.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	interruptMask	Bit mask of interrupts to clear. Bitwise OR of DL_DMA_INTERRUPT.

§ DL_DMA_setPublisherChanID()

__STATIC_INLINE void DL_DMA_setPublisherChanID	(	DMA_Regs *	dma,
		DL_DMA_PUBLISHER_INDEX	index,
		uint8_t	chanID
	)

Sets the event publisher channel id.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	index	Specifies the register event index to be configured
[in]	chanID	Channel ID number. Valid range 0-15. If ChanID == 0 publisher is disconnected.

§ DL_DMA_getPublisherChanID()

__STATIC_INLINE uint8_t DL_DMA_getPublisherChanID	(	DMA_Regs *	dma,
		DL_DMA_PUBLISHER_INDEX	index
	)

Gets the event publisher channel id.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	index	Specifies the register event index to be configured

Returns: Event publisher channel ID

§ DL_DMA_setSubscriberChanID()

__STATIC_INLINE void DL_DMA_setSubscriberChanID	(	DMA_Regs *	dma,
		DL_DMA_SUBSCRIBER_INDEX	index,
		uint8_t	chanID
	)

Sets the event subscriber channel id.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	index	Specifies the register event index to be configured
[in]	chanID	Channel ID number. Valid range 0-15. If ChanID == 0 subscriber is disconnected.

§ DL_DMA_getSubscriberChanID()

__STATIC_INLINE uint8_t DL_DMA_getSubscriberChanID	(	DMA_Regs *	dma,
		DL_DMA_SUBSCRIBER_INDEX	index
	)

Gets the event subscriber channel id.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	index	Specifies the register event index to be configured

Returns: Event subscriber channel ID

§ DL_DMA_enableEvent()

__STATIC_INLINE void DL_DMA_enableEvent	(	DMA_Regs *	dma,
		uint32_t	eventMask
	)

Enable DMA event.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	eventMask	Bit mask of events to enable. Bitwise OR of DL_DMA_EVENT.

§ DL_DMA_disableEvent()

__STATIC_INLINE void DL_DMA_disableEvent	(	DMA_Regs *	dma,
		uint32_t	eventMask
	)

Disable DMA event.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	eventMask	Bit mask of events to enable. Bitwise OR of DL_DMA_EVENT.

§ DL_DMA_getEnabledEvents()

__STATIC_INLINE uint32_t DL_DMA_getEnabledEvents	(	DMA_Regs *	dma,
		uint32_t	eventMask
	)

Check which dma events triggers are enabled.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	eventMask	Bit mask of events to check. Bitwise OR of DL_DMA_EVENT.

Returns: Which of the requested dma events are enabled

Return values

Bitwise OR of DL_DMA_EVENT values

§ DL_DMA_getEnabledEventStatus()

__STATIC_INLINE uint32_t DL_DMA_getEnabledEventStatus	(	DMA_Regs *	dma,
		uint32_t	eventMask
	)

Check event flag of enabled dma event.

Checks if any of the dma events that were previously enabled are pending.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	eventMask	Bit mask of events to check. Bitwise OR of DL_DMA_EVENT.

Returns: Which of the requested dma events are pending

Return values

Bitwise OR of DL_DMA_EVENT values

See also: DL_DMA_enableEvent

§ DL_DMA_getRawEventsStatus()

__STATIC_INLINE uint32_t DL_DMA_getRawEventsStatus	(	DMA_Regs *	dma,
		uint32_t	eventMask
	)

Check event flag of any dma event.

Checks if any events are pending. Events do not have to be previously enabled.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	eventMask	Bit mask of event to check. Bitwise OR of DL_DMA_EVENT.

Returns: Which of the requested dma event are pending

Return values

Bitwise OR of DL_DMA_EVENT values

§ DL_DMA_clearEventsStatus()

__STATIC_INLINE void DL_DMA_clearEventsStatus	(	DMA_Regs *	dma,
		uint32_t	eventMask
	)

Clear pending dma events.

Parameters

[in]	dma	Pointer to the register overlay for the peripheral
[in]	eventMask	Bit mask of events to clear. Bitwise OR of DL_DMA_EVENT.

Modules

Data Structures

Macros

Enumerations

Functions

Detailed Description

Overview

Enumeration Type Documentation

§ DL_DMA_TRANSFER_MODE

§ DL_DMA_EXTENDED_MODE

§ DL_DMA_INCREMENT

§ DL_DMA_EARLY_INTERRUPT_THRESHOLD

§ DL_DMA_BURST_SIZE

§ DL_DMA_TRIGGER_TYPE

§ DL_DMA_WIDTH

§ DL_DMA_EVENT_IIDX

§ DL_DMA_PUBLISHER_INDEX

§ DL_DMA_SUBSCRIBER_INDEX

Function Documentation

§ DL_DMA_initChannel()

§ DL_DMA_configTransfer()

§ DL_DMA_enableRoundRobinPriority()

§ DL_DMA_disableRoundRobinPriority()

§ DL_DMA_isRoundRobinPriorityEnabled()

§ DL_DMA_setBurstSize()

§ DL_DMA_getBurstSize()

§ DL_DMA_enableChannel()

§ DL_DMA_disableChannel()

§ DL_DMA_isChannelEnabled()

§ DL_DMA_configMode()

§ DL_DMA_setTransferMode()

§ DL_DMA_getTransferMode()

§ DL_DMA_setExtendedMode()

§ DL_DMA_getExtendedMode()

§ DL_DMA_startTransfer()

§ DL_DMA_setTrigger()

§ DL_DMA_getTrigger()

§ DL_DMA_getTriggerType()

§ DL_DMA_setSrcAddr()

§ DL_DMA_getSrcAddr()

§ DL_DMA_setDestAddr()

§ DL_DMA_getDestAddr()

§ DL_DMA_setTransferSize()

§ DL_DMA_getTransferSize()

§ DL_DMA_setSrcIncrement()

§ DL_DMA_getSrcIncrement()

§ DL_DMA_setDestIncrement()

§ DL_DMA_getDestIncrement()

§ DL_DMA_setSrcWidth()

§ DL_DMA_getSrcWidth()

§ DL_DMA_setDestWidth()

§ DL_DMA_getDestWidth()

§ DL_DMA_Full_Ch_setEarlyInterruptThreshold()

§ DL_DMA_Full_Ch_getEarlyInterruptThreshold()

§ DL_DMA_enableInterrupt()

§ DL_DMA_disableInterrupt()

§ DL_DMA_getEnabledInterrupts()

§ DL_DMA_getEnabledInterruptStatus()

§ DL_DMA_getRawInterruptStatus()

§ DL_DMA_getPendingInterrupt()

§ DL_DMA_clearInterruptStatus()

§ DL_DMA_setPublisherChanID()

§ DL_DMA_getPublisherChanID()

§ DL_DMA_setSubscriberChanID()

§ DL_DMA_getSubscriberChanID()

§ DL_DMA_enableEvent()

§ DL_DMA_disableEvent()

§ DL_DMA_getEnabledEvents()

§ DL_DMA_getEnabledEventStatus()

§ DL_DMA_getRawEventsStatus()

§ DL_DMA_clearEventsStatus()