[sys_ctrl.h] System Control

Functions
void	SysCtrlIdle (uint32_t vimsPdMode)
	Force the system into idle mode. More...
void	SysCtrlShutdownWithAbort (void)
	Try to enter shutdown but abort if wakeup event happened before shutdown. More...
void	SysCtrlShutdown (void)
	Enable shutdown of the device. More...
void	SysCtrlStandby (bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode)
	Force the system into standby mode. More...
static uint32_t	SysCtrlClockGet (void)
	Get the CPU core clock frequency. More...
static void	SysCtrlAonSync (void)
	Sync all accesses to the AON register interface. More...
static void	SysCtrlAonUpdate (void)
	Update all interfaces to AON. More...
void	SysCtrlSetRechargeBeforePowerDown (uint32_t xoscPowerMode)
	Set Recharge values before entering Power Down. More...
void	SysCtrlAdjustRechargeAfterPowerDown (uint32_t vddrRechargeMargin)
	Adjust Recharge calculations to be used next. More...
void	SysCtrl_DCDC_VoltageConditionalControl (void)
	Turns DCDC on or off depending of what is considered to be optimal usage. More...
uint32_t	SysCtrlResetSourceGet (void)
	Returns the reset source (including "wakeup from shutdown"). More...
static void	SysCtrlSystemReset (void)
	Perform a full system reset. More...
static void	SysCtrlClockLossResetEnable (void)
	Enables reset if OSC clock loss event is asserted. More...
static void	SysCtrlClockLossResetDisable (void)
	Disables reset due to OSC clock loss event. More...
#define	RSTSRC_PWR_ON   (( AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_PIN_RESET   (( AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_VDDS_LOSS   (( AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_VDDR_LOSS   (( AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_CLK_LOSS   (( AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_SYSRESET   (( AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_WARMRESET   (( AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
#define	RSTSRC_WAKEUP_FROM_SHUTDOWN   ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 1 )
#define	RSTSRC_WAKEUP_FROM_TCK_NOISE   ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 2 )

Detailed Description

Function Documentation

SysCtrl_DCDC_VoltageConditionalControl()

void SysCtrl_DCDC_VoltageConditionalControl

(

void

)

Turns DCDC on or off depending of what is considered to be optimal usage.

This function controls the DCDC only if both the following CCFG settings are true:

• DCDC is configured to be used.
• Alternative DCDC settings are defined and enabled.

The DCDC is configured in accordance to the CCFG settings when turned on.

This function should be called periodically.

Returns

None

Referenced by SysCtrlAonUpdate().

{
   uint32_t batThreshold     ;  // Fractional format with 8 fractional bits.
   uint32_t aonBatmonBat     ;  // Fractional format with 8 fractional bits.
   uint32_t ccfg_ModeConfReg ;  // Holds a copy of the CCFG_O_MODE_CONF register.
   uint32_t aonPmctlPwrctl   ;  // Reflect whats read/written to the AON_PMCTL_O_PWRCTL register.

   // We could potentially call this function before any battery voltage measurement
   // is made/available. In that case we must make sure that we do not turn off the DCDC.
   // This can be done by doing nothing as long as the battery voltage is 0 (Since the
   // reset value of the battery voltage register is 0).
   aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT );
   if ( aonBatmonBat != 0 ) {
      // Check if Voltage Conditional Control is enabled
      // It is enabled if all the following are true:
      // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero).
      // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 )
      // - Not in external regulator mode ( EXT_REG_MODE == 0 )
      ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );

      if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0                                            ) ||
           (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M   ) == 0                                            )    ) &&
          (( HWREG( AON_PMCTL_BASE  + AON_PMCTL_O_PWRCTL  ) & AON_PMCTL_PWRCTL_EXT_REG_MODE  )               == 0      ) &&
          (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0      )    )
      {
         aonPmctlPwrctl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL );
         batThreshold   = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) &
            CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >>
            CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 );

         if ( aonPmctlPwrctl & ( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M )) {
            // DCDC is ON, check if it should be switched off
            if ( aonBatmonBat < batThreshold ) {
               aonPmctlPwrctl &= ~( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M );

               HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl;
            }
         } else {
            // DCDC is OFF, check if it should be switched on
            if ( aonBatmonBat > batThreshold ) {
               if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_EN_M     ;
               if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M   ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ;

               HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl;
            }
         }
      }
   }
}

SysCtrlAdjustRechargeAfterPowerDown()

void SysCtrlAdjustRechargeAfterPowerDown

(

uint32_t

vddrRechargeMargin

)

Adjust Recharge calculations to be used next.

Nothing to be done but keeping this function for platform compatibility.

Returns

None

Referenced by SysCtrlAonUpdate().

{
   // Nothing to be done but keeping this function for platform compatibility.
}

SysCtrlAonSync()

static void SysCtrlAonSync ( void  )

inlinestatic

Sync all accesses to the AON register interface.

When this function returns, all writes to the AON register interface are guaranteed to have propagated to hardware. The function will return immediately if no AON writes are pending; otherwise, it will wait for the next AON clock before returning.

Returns

None

See also

SysCtrlAonUpdate()

Referenced by SetupAfterColdResetWakeupFromShutDownCfg3(), SysCtrlIdle(), and SysCtrlStandby().

{
    // Sync the AON interface
    HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC);
}

SysCtrlAonUpdate()

static void SysCtrlAonUpdate ( void  )

inlinestatic

Update all interfaces to AON.

When this function returns, at least 1 clock cycle has progressed on the AON domain, so that any outstanding updates to and from the AON interface is guaranteed to be in sync.

Note

This function should primarily be used after wakeup from sleep modes, as it will guarantee that all shadow registers on the AON interface are updated before reading any AON registers from the MCU domain. If a write has been done to the AON interface it is sufficient to call the SysCtrlAonSync().

Returns

None

See also

SysCtrlAonSync()

Referenced by SysCtrlShutdownWithAbort().

{
    // Force a clock cycle on the AON interface to guarantee all registers are
    // in sync.
    HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC) = 1;
    HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC);
}

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SysCtrlClockGet()

static uint32_t SysCtrlClockGet ( void  )

inlinestatic

Get the CPU core clock frequency.

Use this function to get the current clock frequency for the CPU.

The CPU can run from 48 MHz and down to 750kHz. The frequency is defined by the combined division factor of the SYSBUS and the CPU clock divider.

Returns

Returns the current CPU core clock frequency.

{
    // Return fixed clock speed
    return( GET_MCU_CLOCK );
}

SysCtrlClockLossResetDisable()

static void SysCtrlClockLossResetDisable ( void  )

inlinestatic

Disables reset due to OSC clock loss event.

Note

This function shall typically not be called because the clock loss reset functionality is controlled by the boot code (a factory configuration defines whether it is set or not).

Returns

None

See also

SysCtrlClockLossResetEnable()

{
    // Clear clock loss enable bit in AON_SYSCTRL
    HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0;
}

SysCtrlClockLossResetEnable()

static void SysCtrlClockLossResetEnable ( void  )

inlinestatic

Enables reset if OSC clock loss event is asserted.

Clock loss circuit in analog domain must be enabled as well in order to actually enable for a clock loss reset to occur OSCClockLossEventEnable().

Note

This function shall typically not be called because the clock loss reset functionality is controlled by the boot code (a factory configuration defines whether it is set or not).

Returns

None

See also

SysCtrlClockLossResetDisable(), OSCClockLossEventEnable()

{
    // Set clock loss enable bit in AON_SYSCTRL
    HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1;
}

SysCtrlIdle()

void SysCtrlIdle

(

uint32_t

vimsPdMode

)

Force the system into idle mode.

This function forces the system into IDLE mode by configuring the requested VIMS mode, enabling cache retention and powering off the CPU power domain.

Parameters

vimsPdMode

selects the requested VIMS power domain mode The parameter must be one of the following: VIMS_ON_CPU_ON_MODE VIMS_ON_BUS_ON_MODE VIMS_NO_PWR_UP_MODE

Returns

None

{
    // Configure the VIMS mode
    HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL1VIMS) = vimsPdMode;

    // Always keep cache retention ON in IDLE
    PRCMCacheRetentionEnable();

    // Turn off the CPU power domain, will take effect when PRCMDeepSleep() executes
    PRCMPowerDomainOff(PRCM_DOMAIN_CPU);

    // Ensure any possible outstanding AON writes complete
    SysCtrlAonSync();

    // Invoke deep sleep to go to IDLE
    PRCMDeepSleep();
}

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SysCtrlResetSourceGet()

uint32_t SysCtrlResetSourceGet

(

void

)

Returns the reset source (including "wakeup from shutdown").

In case of RSTSRC_WAKEUP_FROM_SHUTDOWN the application is responsible for unlatching the outputs (disable pad sleep). See PowerCtrlPadSleepDisable() for more information.

Returns

Returns the reset source.

• RSTSRC_PWR_ON
• RSTSRC_PIN_RESET
• RSTSRC_VDDS_LOSS
• RSTSRC_VDDR_LOSS
• RSTSRC_CLK_LOSS
• RSTSRC_SYSRESET
• RSTSRC_WARMRESET
• RSTSRC_WAKEUP_FROM_SHUTDOWN
• RSTSRC_WAKEUP_FROM_TCK_NOISE

{
   uint32_t aonPmctlResetCtl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL );

   if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) {
      if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M ) {
         return ( RSTSRC_WAKEUP_FROM_SHUTDOWN );
      } else {
         return ( RSTSRC_WAKEUP_FROM_TCK_NOISE );
      }
   } else {
      return (( aonPmctlResetCtl & AON_PMCTL_RESETCTL_RESET_SRC_M ) >> AON_PMCTL_RESETCTL_RESET_SRC_S );
   }
}

SysCtrlSetRechargeBeforePowerDown()

void SysCtrlSetRechargeBeforePowerDown

(

uint32_t

xoscPowerMode

)

Set Recharge values before entering Power Down.

This function shall be called just before entering Power Down. This function typically does nothing (default setting), but if temperature compensated recharge level are enabled (by setting CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC = 0) it adds temperature compensation to the recharge level.

Parameters

xoscPowerMode

(typically running in XOSC_IN_HIGH_POWER_MODE all the time). XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC. XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC.

Returns

None

Referenced by SysCtrlAonUpdate(), and SysCtrlStandby().

{
   uint32_t          ccfg_ModeConfReg        ;

   // If external regulator mode we shall:
   // - Set static recharge timing in AON_PMCTL_RECHARGECFG (MODE_STATIC)
   // - Set recharge period to approximately 500 mS (perM=31, perE=5 => 0xFD)
   if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) {
      HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG ) = ( AON_PMCTL_RECHARGECFG_MODE_STATIC | 0x000000FD );
      return;
   }

   // read the MODE_CONF register in CCFG
   ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
   // Do temperature compensation if enabled
   if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) {
      int32_t vddrSleepDelta  ;
      int32_t curTemp         ;
      int32_t tcDelta         ;
      int32_t vddrSleepTrim   ;

      // Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended) ==> vddrSleepDelta = -7..+8
      vddrSleepDelta = (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S )))
                                                     >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1 ;
      curTemp = AONBatMonTemperatureGetDegC();
      tcDelta = ( 62 - curTemp ) >> 3;
      if ( tcDelta > 7 ) {
         tcDelta = 7 ;
      }
      if ( tcDelta > vddrSleepDelta ) {
         vddrSleepDelta = tcDelta ;
      }
      vddrSleepTrim = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_TRIM ) & FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M ) >>
                                                                   FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S ) ;

      vddrSleepTrim -= vddrSleepDelta ;
      if ( vddrSleepTrim >  15 ) vddrSleepTrim =  15 ;
      if ( vddrSleepTrim <   1 ) vddrSleepTrim =   1 ;
      // Write adjusted value using MASKED write (MASK8)
      HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 * 2 )) = (( ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M << 4 ) |
        (( vddrSleepTrim << ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_S ) & ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M )   );
      // Make a dummy read in order to make sure the write above is done before going into standby
      HWREGB( ADI3_BASE + ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 );
   }
}

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SysCtrlShutdown()

void SysCtrlShutdown

(

void

)

Enable shutdown of the device.

This function puts the device in shutdown state. The device automatically latches all outputs (pads in sleep) before it turns off all internal power supplies.

JTAG must be disconnected and JTAG power domain must be off before device can enter shutdown. This function waits until the device satisfies all shutdown conditions before it enters shutdown.

Note

The application must unlatch the outputs when the device wakes up from shutdown. It is recommended that any outputs that need to be restored after a wakeup from shutdown are restored before outputs are unlatched in order to avoid glitches.

See PowerCtrlPadSleepDisable() for information about how to unlatch outputs (disable pad sleep) after wakeup from shutdown.

Note

Wakeup events are only detected after the device enters shutdown.

See IOCIOShutdownSet() for information about how to enable wakeup from shutdown.

See SysCtrlResetSourceGet() for information about how to detect wakeup from shutdown.

It is recommended to disable interrupts before calling this function. Shutdown happens immediately when the device satisfies all shutdown conditions thus interrupt routines triggered after this function is called might be aborted.

Returns

This function does not return.

Referenced by SysCtrlShutdownWithAbort().

{
    // Request shutdown mode
    HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SHUTDOWN) = AON_PMCTL_SHUTDOWN_EN;

    // Make sure System CPU does not continue beyond this point.
    // Shutdown happens when all shutdown conditions are met.
    while(1);
}

SysCtrlShutdownWithAbort()

void SysCtrlShutdownWithAbort

(

void

)

Try to enter shutdown but abort if wakeup event happened before shutdown.

This function puts the device in shutdown state if no wakeup events are detected before shutdown.

Compared to the basic SysCtrlShutdown() function this function makes sure that wakeup events that happen before actual shutdown are also detected. This function either enters shutdown with a guaranteed wakeup detection or returns to the caller function due to a pre-shutdown wakeup event.

See SysCtrlShutdown() for basic information about how to configure the device before shutdown and how to wakeup from shutdown.

This function uses IO edge detection in addition to the mandatory wakeup configuration. Additional requirements to the application for this function are:

• Before :
  • When the application configures an IO for wakeup (see IOCIOShutdownSet()) the application must also configure the same IO for edge detection (see IOCIOIntSet()).
  • Edge detection must use the same polarity as the wakeup configuration.
  • Application must enable peripheral power domain (see PRCMPowerDomainOn()) and enable GPIO module in the peripheral power domain (see PRCMPeripheralRunEnable()).
• After :
  • An edge, with same polarity as a wakeup event, was detected on a wakeup enabled IO before shutdown, and the shutdown was aborted. The application must clear the event generated by the edge detect (see GPIO_clearEventDio()) and decide what happens next.

Useful functions related to shutdown:

• IOCIOShutdownSet() : Enables wakeup from shutdown.
• IOCIOIntSet() : Enables IO edge detection.
• PRCMPowerDomainOn() : Enables peripheral power domain.
• PRCMPeripheralRunEnable() : Enables GPIO module.
• SysCtrlResetSourceGet() : Detects wakeup from shutdown.
• PowerCtrlPadSleepDisable() : Unlatches outputs (disables pad sleep) after wakeup from shutdown.
• GPIO_clearEventDio() : Clears edge detects.

It is recommended to disable interrupts before calling this function because:

• Pads are in sleep mode while this function runs.
• An interrupt routine might be terminated if it is triggered after the decision to enter shutdown.

Returns

None

{
    uint32_t wakeupDetected = 0;
    uint32_t ioIndex = 0;

    uint32_t ioCount = (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) &
            FCFG1_IOCONF_GPIO_CNT_M ) >> FCFG1_IOCONF_GPIO_CNT_S ) ;

    // Wakeup events are detected when pads are in sleep mode
    PowerCtrlPadSleepEnable();

    // Make sure all potential events have propagated before checking event flags
    SysCtrlAonUpdate();
    SysCtrlAonUpdate();

    // For all IO CFG registers check if wakeup detect is enabled
    for(ioIndex = 0; ioIndex < ioCount; ioIndex++)
    {
        // Read MSB from WU_CFG bit field
        if( HWREG(IOC_BASE + IOC_O_IOCFG0 + (ioIndex * 4) ) & (1 << (IOC_IOCFG0_WU_CFG_S + IOC_IOCFG0_WU_CFG_W - 1)) )
        {
            if (GPIO_getEventDio(ioIndex))
            {
                wakeupDetected = 1;
                break;
            }
        }
    }

    // If no edge detect flags for wakeup enabled IOs are set then shut down the device
    if( wakeupDetected == 0 )
    {
        SysCtrlShutdown();
    }
    else
    {
        PowerCtrlPadSleepDisable();
    }
}

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SysCtrlStandby()

void SysCtrlStandby	(	bool	retainCache,
		uint32_t	vimsPdMode,
		uint32_t	rechargeMode
	)

Force the system into standby mode.

This function forces all power domains (RFCORE, SERIAL, PERIPHERAL) off. The VIMS and CPU power domains are turned off by the HW when the PRCMDeepSleep() function is called. The IOs are latched (frozen) before the power domains are turned off to avoid glitches. The VIMS retention (cache) and VIMS module are turned off if requested. The deep-sleep clock for the crypto and DMA modules are turned off, as they must be off in order to enter standby. This function assumes that the LF clock has already been switched to and that the LF clock qualifiers must have been disabled/bypassed.

In internal regulator mode the adaptive recharge functionality is enabled with fixed parameter values. In external regulator mode the recharge functionality is disabled.

Note

This function is optimized to execute with TI-RTOS. There might be application specific prerequisites you would want to do before entering standby which deviate from this specific implementation.

Parameters

retainCache	selects if VIMS cache shall be retained or not. false : VIMS cache is not retained true : VIMS cache is retained
vimsPdMode	selects the VIMS power domain mode. The parameter must be one of the following: VIMS_ON_CPU_ON_MODE VIMS_NO_PWR_UP_MODE
rechargeMode	specifies the requested recharge mode. The parameter must be one of the following: SYSCTRL_PREFERRED_RECHARGE_MODE : Preferred recharge mode specified by TI

Returns

None

{
    uint32_t modeVIMS;

    // In external regulator mode:
    // Set static recharge timing to approximately 500 milliseconds
    // Else:
    // Handle compensation for improving RCOSC_LF stability at low temperatures
    // as configured in CCFG
    SysCtrlSetRechargeBeforePowerDown(XOSC_IN_HIGH_POWER_MODE);

    // Freeze the IOs on the boundary between MCU and AON
    AONIOCFreezeEnable();

    // Ensure any possible outstanding AON writes complete before turning off the power domains
    SysCtrlAonSync();

    // Request power off of domains in the MCU voltage domain
    PRCMPowerDomainOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH | PRCM_DOMAIN_CPU);

    // Ensure that no clocks are forced on in any modes for Crypto, DMA and I2S
    HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) &= (~PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN & ~PRCM_SECDMACLKGR_DMA_AM_CLK_EN);
    HWREG(PRCM_BASE + PRCM_O_I2SCLKGR)    &= ~PRCM_I2SCLKGR_AM_CLK_EN;

    // Gate running deep sleep clocks for Crypto, DMA and I2S
    PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_CRYPTO);
    PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_UDMA);
    PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_I2S);

    // Load the new clock settings
    PRCMLoadSet();

    // Configure the VIMS power domain mode
    HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode;

    // Request uLDO during standby
    PRCMMcuUldoConfigure(1);

    // In external regulator mode:
    // - Setting the AON_PMCTL_O_RECHARGECFG register is already handled above.
    //   (in function SysCtrlSetRechargeBeforePowerDown() )
    // Else:
    // - Set the AON_PMCTL_O_RECHARGECFG register as described below.
    if ((HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & AON_PMCTL_PWRCTL_EXT_REG_MODE)==0)
    {
        // In internal regulator mode the recharge functionality is set up with
        // adaptive recharge mode and fixed parameter values
        if(rechargeMode == SYSCTRL_PREFERRED_RECHARGE_MODE)
        {
            // Enable the Recharge Comparator
            HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR;
        }
        else
        {
            // Set requested recharge mode
            HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = rechargeMode;
        }
    }

    // Ensure all writes have taken effect
    SysCtrlAonSync();

    // Ensure UDMA, Crypto and I2C clocks are turned off
    while (!PRCMLoadGet()) {;}

    // Ensure power domains have been turned off.
    // CPU power domain will power down when PRCMDeepSleep() executes.
    while (PRCMPowerDomainsAllOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_OFF) {;}

    // Turn off cache retention if requested
    if (retainCache == false) {

        // Get the current VIMS mode
        do {
            modeVIMS = VIMSModeGet(VIMS_BASE);
        } while (modeVIMS == VIMS_MODE_CHANGING);

        // If in a cache mode, turn VIMS off
        if (modeVIMS == VIMS_MODE_ENABLED) {
           VIMSModeSet(VIMS_BASE, VIMS_MODE_OFF);
        }

        // Disable retention of cache RAM
        PRCMCacheRetentionDisable();
    }

    // Invoke deep sleep to go to STANDBY
    PRCMDeepSleep();
}

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SysCtrlSystemReset()

static void SysCtrlSystemReset ( void  )

inlinestatic

Perform a full system reset.

Returns

The chip will reset and hence never return from this call.

{
   // Disable CPU interrupts
   CPUcpsid();
   // Write reset register
   HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN ) = 1;
   // Finally, wait until the above write propagates
   while ( 1 ) {
      // Do nothing, just wait for the reset (and never return from here)
   }
}

Here is the call graph for this function:

Macro Definition Documentation

CPU_DEEP_SLEEP

#define CPU_DEEP_SLEEP   0x00000002

CPU_RUN

#define CPU_RUN   0x00000000

CPU_SLEEP

#define CPU_SLEEP   0x00000001

RSTSRC_CLK_LOSS

#define RSTSRC_CLK_LOSS   (( AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))

RSTSRC_PIN_RESET

#define RSTSRC_PIN_RESET   (( AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))

RSTSRC_PWR_ON

#define RSTSRC_PWR_ON   (( AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))

RSTSRC_SYSRESET

#define RSTSRC_SYSRESET   (( AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))

RSTSRC_VDDR_LOSS

#define RSTSRC_VDDR_LOSS   (( AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))

RSTSRC_VDDS_LOSS

#define RSTSRC_VDDS_LOSS   (( AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))

RSTSRC_WAKEUP_FROM_SHUTDOWN

#define RSTSRC_WAKEUP_FROM_SHUTDOWN   ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 1 )

Referenced by SysCtrlResetSourceGet().

RSTSRC_WAKEUP_FROM_TCK_NOISE

#define RSTSRC_WAKEUP_FROM_TCK_NOISE   ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 2 )

Referenced by SysCtrlResetSourceGet().

RSTSRC_WARMRESET

#define RSTSRC_WARMRESET   (( AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))

SYSCTRL_PREFERRED_RECHARGE_MODE

#define SYSCTRL_PREFERRED_RECHARGE_MODE   0xFFFFFFFF

Referenced by SysCtrlStandby().

SYSCTRL_SYSBUS_OFF

#define SYSCTRL_SYSBUS_OFF   0x00000000

SYSCTRL_SYSBUS_ON

#define SYSCTRL_SYSBUS_ON   0x00000001

VIMS_NO_PWR_UP_MODE

#define VIMS_NO_PWR_UP_MODE   2

VIMS_ON_BUS_ON_MODE

#define VIMS_ON_BUS_ON_MODE   1

VIMS_ON_CPU_ON_MODE

#define VIMS_ON_CPU_ON_MODE   0

XOSC_IN_HIGH_POWER_MODE

#define XOSC_IN_HIGH_POWER_MODE   0

Referenced by SysCtrlStandby().

XOSC_IN_LOW_POWER_MODE

#define XOSC_IN_LOW_POWER_MODE   1