AUX_EVCTL

Instance: AUX_EVCTL
Component: AUX_EVCTL
Base address: 0x400C5000


AUX Event Controller (AUX_EVCTL) assembles events originating from:
- AUX submodules, including ADC and comparators.
- AUXIO.
- EVENT.
- AON_PMCTL.
- AON_RTC.
- AON_BATMON.

into two 64-bit event buses. One is synchronized to the AUX clock and one is left unsynchronized.

The subscribers to the synchronous event bus are AUX_TIMER01, AUX_SCE and AUX_EVCTL.
The subscribers to the asynchronous event bus are AUX_TIMER2, AUX_ANAIF, AUX_TDC and AUX_SYSIF.

AUX_EVCTL uses the synchronous event bus to generate events to AON_EVENT and EVENT, as well as to AUX_SCE. AUX_SCE can poll event status registers and combine certain instructions like WEV0, WEV1 with one or two configurable events. The latter saves power when execution must stall until a condition is met.

TOP:AUX_EVCTL Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

EVSTAT0

RO

32

0x0000 0000

0x0000 0000

0x400C 5000

EVSTAT1

RO

32

0x0000 0000

0x0000 0004

0x400C 5004

EVSTAT2

RO

32

0x0000 0000

0x0000 0008

0x400C 5008

EVSTAT3

RO

32

0x0000 0000

0x0000 000C

0x400C 500C

SCEWEVCFG0

RW

32

0x0000 0000

0x0000 0010

0x400C 5010

SCEWEVCFG1

RW

32

0x0000 0000

0x0000 0014

0x400C 5014

DMACTL

RW

32

0x0000 0000

0x0000 0018

0x400C 5018

SWEVSET

RW

32

0x0000 0000

0x0000 0020

0x400C 5020

EVTOAONFLAGS

RW

32

0x0000 0000

0x0000 0024

0x400C 5024

EVTOAONPOL

RW

32

0x0000 0000

0x0000 0028

0x400C 5028

EVTOAONFLAGSCLR

RW

32

0x0000 0000

0x0000 002C

0x400C 502C

EVTOMCUFLAGS

RW

32

0x0000 0000

0x0000 0030

0x400C 5030

EVTOMCUPOL

RW

32

0x0000 0000

0x0000 0034

0x400C 5034

EVTOMCUFLAGSCLR

RW

32

0x0000 0000

0x0000 0038

0x400C 5038

COMBEVTOMCUMASK

RW

32

0x0000 0000

0x0000 003C

0x400C 503C

EVOBSCFG

RW

32

0x0000 0000

0x0000 0040

0x400C 5040

PROGDLY

RW

32

0x0000 0000

0x0000 0044

0x400C 5044

MANUAL

RW

32

0x0000 0000

0x0000 0048

0x400C 5048

EVSTAT0L

RO

32

0x0000 0000

0x0000 004C

0x400C 504C

EVSTAT0H

RO

32

0x0000 0000

0x0000 0050

0x400C 5050

EVSTAT1L

RO

32

0x0000 0000

0x0000 0054

0x400C 5054

EVSTAT1H

RO

32

0x0000 0000

0x0000 0058

0x400C 5058

EVSTAT2L

RO

32

0x0000 0000

0x0000 005C

0x400C 505C

EVSTAT2H

RO

32

0x0000 0000

0x0000 0060

0x400C 5060

EVSTAT3L

RO

32

0x0000 0000

0x0000 0064

0x400C 5064

EVSTAT3H

RO

32

0x0000 0000

0x0000 0068

0x400C 5068

TOP:AUX_EVCTL Register Descriptions

TOP:AUX_EVCTL:EVSTAT0

Address Offset 0x0000 0000
Physical Address 0x400C 5000 Instance 0x400C 5000
Description Event Status 0

Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIO.
- EVOBSCFG.
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUXIO15 AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. RO 0
14 AUXIO14 AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. RO 0
13 AUXIO13 AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. RO 0
12 AUXIO12 AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. RO 0
11 AUXIO11 AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. RO 0
10 AUXIO10 AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. RO 0
9 AUXIO9 AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. RO 0
8 AUXIO8 AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. RO 0
7 AUXIO7 AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. RO 0
6 AUXIO6 AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. RO 0
5 AUXIO5 AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. RO 0
4 AUXIO4 AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. RO 0
3 AUXIO3 AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. RO 0
2 AUXIO2 AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. RO 0
1 AUXIO1 AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. RO 0
0 AUXIO0 AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. RO 0

TOP:AUX_EVCTL:EVSTAT1

Address Offset 0x0000 0004
Physical Address 0x400C 5004 Instance 0x400C 5004
Description Event Status 1

Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIO.
- EVOBSCFG.
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUXIO31 AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7. RO 0
14 AUXIO30 AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6. RO 0
13 AUXIO29 AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5. RO 0
12 AUXIO28 AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4. RO 0
11 AUXIO27 AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3. RO 0
10 AUXIO26 AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2. RO 0
9 AUXIO25 AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1. RO 0
8 AUXIO24 AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0. RO 0
7 AUXIO23 AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7. RO 0
6 AUXIO22 AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6. RO 0
5 AUXIO21 AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5. RO 0
4 AUXIO20 AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4. RO 0
3 AUXIO19 AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3. RO 0
2 AUXIO18 AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2. RO 0
1 AUXIO17 AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1. RO 0
0 AUXIO16 AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0. RO 0

TOP:AUX_EVCTL:EVSTAT2

Address Offset 0x0000 0008
Physical Address 0x400C 5008 Instance 0x400C 5008
Description Event Status 2

Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC.
- AUX_SYSIF.
- AUX_AIODIO.
- EVOBSCFG.
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUX_COMPB Comparator B output.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the synchronization rate for this event.		 RO 0
14 AUX_COMPA Comparator A output.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the synchronization rate for this event.		 RO 0
13 MCU_OBSMUX1 Observation input 1 from IOC.
This event is configured by IOC:OBSAUXOUTPUT.SEL1.		 RO 0
12 MCU_OBSMUX0 Observation input 0 from IOC.
This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by IOC:OBSAUXOUTPUT.SEL_MISC.		 RO 0
11 MCU_EV Event from EVENT configured by EVENT:AUXSEL0. RO 0
10 ACLK_REF TDC reference clock.
It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ.		 RO 0
9 VDDR_RECHARGE Event is high during VDDR recharge. RO 0
8 MCU_ACTIVE Event is high while system(MCU, AUX, or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state). Event is not high during VDDR recharge. RO 0
7 PWR_DWN Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO power supply). RO 0
6 SCLK_LF SCLK_LF clock RO 0
5 AON_BATMON_TEMP_UPD Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP. RO 0
4 AON_BATMON_BAT_UPD Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT. RO 0
3 AON_RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19.
AON_RTC:CTL.RTC_4KHZ_EN enables this event.		 RO 0
2 AON_RTC_CH2_DLY AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration. RO 0
1 AON_RTC_CH2 AON_RTC:EVFLAGS.CH2. RO 0
0 MANUAL_EV Programmable event. See MANUAL for description. RO 0

TOP:AUX_EVCTL:EVSTAT3

Address Offset 0x0000 000C
Physical Address 0x400C 500C Instance 0x400C 500C
Description Event Status 3

Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register.
- AUX_TIMER2.
- AUX_ANAIF.
- AUX_TDC .
- AUX_SYSIF.
- AUX_AIODIO.
- EVOBSCFG.
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUX_TIMER2_CLKSWITCH_RDY AUX_SYSIF:TIMER2CLKSWITCH.RDY RO 0
14 AUX_DAC_HOLD_ACTIVE AUX_ANAIF:DACSTAT.HOLD_ACTIVE RO 0
13 AUX_SMPH_AUTOTAKE_DONE See AUX_SMPH:AUTOTAKE.SMPH_ID for description. RO 0
12 AUX_ADC_FIFO_NOT_EMPTY AUX_ANAIF:ADCFIFOSTAT.EMPTY negated RO 0
11 AUX_ADC_FIFO_ALMOST_FULL AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL RO 0
10 AUX_ADC_IRQ The logical function for this event is configurable.

When DMACTL.EN = 1 :
Event = UDMA0 Channel 7 done event OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW

When DMACTL.EN = 0 :
Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW

Bit 7 in UDMA0:DONEMASK must be 0.		 RO 0
9 AUX_ADC_DONE AUX_ANAIF ADC conversion done event.
Event is synchronized at AUX bus rate.		 RO 0
8 AUX_ISRC_RESET_N AUX_ANAIF:ISRCCTL.RESET_N RO 0
7 AUX_TDC_DONE AUX_TDC:STAT.DONE RO 0
6 AUX_TIMER0_EV AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description. RO 0
5 AUX_TIMER1_EV AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description. RO 0
4 AUX_TIMER2_PULSE AUX_TIMER2 pulse event.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.		 RO 0
3 AUX_TIMER2_EV3 AUX_TIMER2 event output 3.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.		 RO 0
2 AUX_TIMER2_EV2 AUX_TIMER2 event output 2.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.		 RO 0
1 AUX_TIMER2_EV1 AUX_TIMER2 event output 1.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.		 RO 0
0 AUX_TIMER2_EV0 AUX_TIMER2 event output 0.
Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the synchronization rate for this event.		 RO 0

TOP:AUX_EVCTL:SCEWEVCFG0

Address Offset 0x0000 0010
Physical Address 0x400C 5010 Instance 0x400C 5010
Description Sensor Controller Engine Wait Event Configuration 0

Configuration of this register and SCEWEVCFG1 controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS. This bit can be used by AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions.

When COMB_EV_EN = 0:
AUX_SCE:WUSTAT.EV_SIGNALS (7) = EV0_SEL event

When COMB_EV_EN = 1:
AUX_SCE:WUSTAT.EV_SIGNALS (7) = ( EV0_SEL event ) OR ( SCEWEVCFG1.EV1_SEL event )

Bit fields SCEWEVCFG1.EV0_POL and SCEWEVCFG1.EV1_POL control the polarity of selected events.

Event combination is useful when there is a need to wait for a certain condition with timeout.
Type RW
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6 COMB_EV_EN Event combination control:

0: Disable event combination.
1: Enable event combination.		 RW 0
5:0 EV0_SEL Select the event source from the synchronous event bus to be used in event equation.
Value ENUM Name Description
0x0 AUXIO0 EVSTAT0.AUXIO0
0x1 AUXIO1 EVSTAT0.AUXIO1
0x2 AUXIO2 EVSTAT0.AUXIO2
0x3 AUXIO3 EVSTAT0.AUXIO3
0x4 AUXIO4 EVSTAT0.AUXIO4
0x5 AUXIO5 EVSTAT0.AUXIO5
0x6 AUXIO6 EVSTAT0.AUXIO6
0x7 AUXIO7 EVSTAT0.AUXIO7
0x8 AUXIO8 EVSTAT0.AUXIO8
0x9 AUXIO9 EVSTAT0.AUXIO9
0xA AUXIO10 EVSTAT0.AUXIO10
0xB AUXIO11 EVSTAT0.AUXIO11
0xC AUXIO12 EVSTAT0.AUXIO12
0xD AUXIO13 EVSTAT0.AUXIO13
0xE AUXIO14 EVSTAT0.AUXIO14
0xF AUXIO15 EVSTAT0.AUXIO15
0x10 AUXIO16 EVSTAT1.AUXIO16
0x11 AUXIO17 EVSTAT1.AUXIO17
0x12 AUXIO18 EVSTAT1.AUXIO18
0x13 AUXIO19 EVSTAT1.AUXIO19
0x14 AUXIO20 EVSTAT1.AUXIO20
0x15 AUXIO21 EVSTAT1.AUXIO21
0x16 AUXIO22 EVSTAT1.AUXIO22
0x17 AUXIO23 EVSTAT1.AUXIO23
0x18 AUXIO24 EVSTAT1.AUXIO24
0x19 AUXIO25 EVSTAT1.AUXIO25
0x1A AUXIO26 EVSTAT1.AUXIO26
0x1B AUXIO27 EVSTAT1.AUXIO27
0x1C AUXIO28 EVSTAT1.AUXIO28
0x1D AUXIO29 EVSTAT1.AUXIO29
0x1E AUXIO30 EVSTAT1.AUXIO30
0x1F AUXIO31 EVSTAT1.AUXIO31
0x20 AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY
0x21 AON_RTC_CH2 EVSTAT2.AON_RTC_CH2
0x22 AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY
0x23 AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ
0x24 AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD
0x25 AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD
0x26 SCLK_LF EVSTAT2.SCLK_LF
0x27 PWR_DWN EVSTAT2.PWR_DWN
0x28 MCU_ACTIVE EVSTAT2.MCU_ACTIVE
0x29 VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE
0x2A ACLK_REF EVSTAT2.ACLK_REF
0x2B MCU_EV EVSTAT2.MCU_EV
0x2C MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0
0x2D MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1
0x2E AUX_COMPA EVSTAT2.AUX_COMPA
0x2F AUX_COMPB EVSTAT2.AUX_COMPB
0x30 AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0
0x31 AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1
0x32 AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2
0x33 AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3
0x34 AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE
0x35 AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV
0x36 AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV
0x37 AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE
0x38 AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N
0x39 AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE
0x3A AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ
0x3B AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
0x3C AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
0x3D AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
0x3E AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE
0x3F AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
RW 0b00 0000

TOP:AUX_EVCTL:SCEWEVCFG1

Address Offset 0x0000 0014
Physical Address 0x400C 5014 Instance 0x400C 5014
Description Sensor Controller Engine Wait Event Configuration 1

See SCEWEVCFG0 for description.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 EV0_POL Polarity of SCEWEVCFG0.EV0_SEL event.

When SCEWEVCFG0.COMB_EV_EN is 0:

0: Non-inverted.
1: Non-inverted.

When SCEWEVCFG0.COMB_EV_EN is 1.

0: Non-inverted.
1: Inverted.		 RW 0
6 EV1_POL Polarity of EV1_SEL event.

When SCEWEVCFG0.COMB_EV_EN is 0:

0: Non-inverted.
1: Non-inverted.

When SCEWEVCFG0.COMB_EV_EN is 1.

0: Non-inverted.
1: Inverted.		 RW 0
5:0 EV1_SEL Select the event source from the synchronous event bus to be used in event equation.
Value ENUM Name Description
0x0 AUXIO0 EVSTAT0.AUXIO0
0x1 AUXIO1 EVSTAT0.AUXIO1
0x2 AUXIO2 EVSTAT0.AUXIO2
0x3 AUXIO3 EVSTAT0.AUXIO3
0x4 AUXIO4 EVSTAT0.AUXIO4
0x5 AUXIO5 EVSTAT0.AUXIO5
0x6 AUXIO6 EVSTAT0.AUXIO6
0x7 AUXIO7 EVSTAT0.AUXIO7
0x8 AUXIO8 EVSTAT0.AUXIO8
0x9 AUXIO9 EVSTAT0.AUXIO9
0xA AUXIO10 EVSTAT0.AUXIO10
0xB AUXIO11 EVSTAT0.AUXIO11
0xC AUXIO12 EVSTAT0.AUXIO12
0xD AUXIO13 EVSTAT0.AUXIO13
0xE AUXIO14 EVSTAT0.AUXIO14
0xF AUXIO15 EVSTAT0.AUXIO15
0x10 AUXIO16 EVSTAT1.AUXIO16
0x11 AUXIO17 EVSTAT1.AUXIO17
0x12 AUXIO18 EVSTAT1.AUXIO18
0x13 AUXIO19 EVSTAT1.AUXIO19
0x14 AUXIO20 EVSTAT1.AUXIO20
0x15 AUXIO21 EVSTAT1.AUXIO21
0x16 AUXIO22 EVSTAT1.AUXIO22
0x17 AUXIO23 EVSTAT1.AUXIO23
0x18 AUXIO24 EVSTAT1.AUXIO24
0x19 AUXIO25 EVSTAT1.AUXIO25
0x1A AUXIO26 EVSTAT1.AUXIO26
0x1B AUXIO27 EVSTAT1.AUXIO27
0x1C AUXIO28 EVSTAT1.AUXIO28
0x1D AUXIO29 EVSTAT1.AUXIO29
0x1E AUXIO30 EVSTAT1.AUXIO30
0x1F AUXIO31 EVSTAT1.AUXIO31
0x20 AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY
0x21 AON_RTC_CH2 EVSTAT2.AON_RTC_CH2
0x22 AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY
0x23 AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ
0x24 AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD
0x25 AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD
0x26 SCLK_LF EVSTAT2.SCLK_LF
0x27 PWR_DWN EVSTAT2.PWR_DWN
0x28 MCU_ACTIVE EVSTAT2.MCU_ACTIVE
0x29 VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE
0x2A ACLK_REF EVSTAT2.ACLK_REF
0x2B MCU_EV EVSTAT2.MCU_EV
0x2C MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0
0x2D MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1
0x2E AUX_COMPA EVSTAT2.AUX_COMPA
0x2F AUX_COMPB EVSTAT2.AUX_COMPB
0x30 AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0
0x31 AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1
0x32 AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2
0x33 AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3
0x34 AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE
0x35 AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV
0x36 AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV
0x37 AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE
0x38 AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N
0x39 AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE
0x3A AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ
0x3B AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
0x3C AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
0x3D AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
0x3E AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE
0x3F AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
RW 0b00 0000

TOP:AUX_EVCTL:DMACTL

Address Offset 0x0000 0018
Physical Address 0x400C 5018 Instance 0x400C 5018
Description Direct Memory Access Control
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 REQ_MODE UDMA0 Request mode
Value ENUM Name Description
0x0 BURST Burst requests are generated on UDMA0 channel 7 when the condition configured in SEL is met.
0x1 SINGLE Single requests are generated on UDMA0 channel 7 when the condition configured in SEL is met.
RW 0
1 EN uDMA ADC interface enable.

0: Disable UDMA0 interface to ADC.
1: Enable UDMA0 interface to ADC.		 RW 0
0 SEL Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data.
Value ENUM Name Description
0x0 AUX_ADC_FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there are samples in the ADC FIFO.
0x1 AUX_ADC_FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC FIFO is almost full (3/4 full).
RW 0

TOP:AUX_EVCTL:SWEVSET

Address Offset 0x0000 0020
Physical Address 0x400C 5020 Instance 0x400C 5020
Description Software Event Set

Set software event flags from AUX domain to AON and MCU domains. CPUs in MCU domain can read the event flags from EVTOAONFLAGS and clear them in EVTOAONFLAGSCLR.

Use of these event flags is software-defined.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 SWEV2 Software event flag 2.

0: No effect.
1: Set software event flag 2.		 WO 0
1 SWEV1 Software event flag 1.

0: No effect.
1: Set software event flag 1.		 WO 0
0 SWEV0 Software event flag 0.

0: No effect.
1: Set software event flag 0.		 WO 0

TOP:AUX_EVCTL:EVTOAONFLAGS

Address Offset 0x0000 0024
Physical Address 0x400C 5024 Instance 0x400C 5024
Description Events To AON Flags

This register contains a collection of event flags routed to AON_EVENT.

To clear an event flag, write to EVTOAONFLAGSCLR or write 0 to event flag in this register.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 AUX_TIMER1_EV This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV. RW 0
7 AUX_TIMER0_EV This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV. RW 0
6 AUX_TDC_DONE This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE. RW 0
5 AUX_ADC_DONE This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE. RW 0
4 AUX_COMPB This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB. RW 0
3 AUX_COMPA This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA. RW 0
2 SWEV2 This event flag is set when software writes a 1 to SWEVSET.SWEV2. RW 0
1 SWEV1 This event flag is set when software writes a 1 to SWEVSET.SWEV1. RW 0
0 SWEV0 This event flag is set when software writes a 1 to SWEVSET.SWEV0. RW 0

TOP:AUX_EVCTL:EVTOAONPOL

Address Offset 0x0000 0028
Physical Address 0x400C 5028 Instance 0x400C 5028
Description Events To AON Polarity

Event source polarity configuration for EVTOAONFLAGS.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 AUX_TIMER1_EV Select the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
7 AUX_TIMER0_EV Select the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
6 AUX_TDC_DONE Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
5 AUX_ADC_DONE Select the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
4 AUX_COMPB Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB.
Value ENUM Name Description
0x0 RISE Rising edge
0x1 FALL Falling edge
RW 0
3 AUX_COMPA Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA.
Value ENUM Name Description
0x0 RISE Rising edge
0x1 FALL Falling edge
RW 0
2:0 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000

TOP:AUX_EVCTL:EVTOAONFLAGSCLR

Address Offset 0x0000 002C
Physical Address 0x400C 502C Instance 0x400C 502C
Description Events To AON Clear

Clear event flags in EVTOAONFLAGS.

In order to clear a level sensitive event flag, the event must be deasserted.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 AUX_TIMER1_EV Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV.

Read value is 0.		 WO 0
7 AUX_TIMER0_EV Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV.

Read value is 0.		 WO 0
6 AUX_TDC_DONE Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE.

Read value is 0.		 WO 0
5 AUX_ADC_DONE Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE.

Read value is 0.		 WO 0
4 AUX_COMPB Write 1 to clear EVTOAONFLAGS.AUX_COMPB.

Read value is 0.		 WO 0
3 AUX_COMPA Write 1 to clear EVTOAONFLAGS.AUX_COMPA.

Read value is 0.		 WO 0
2 SWEV2 Write 1 to clear EVTOAONFLAGS.SWEV2.

Read value is 0.		 WO 0
1 SWEV1 Write 1 to clear EVTOAONFLAGS.SWEV1.

Read value is 0.		 WO 0
0 SWEV0 Write 1 to clear EVTOAONFLAGS.SWEV0.

Read value is 0.		 WO 0

TOP:AUX_EVCTL:EVTOMCUFLAGS

Address Offset 0x0000 0030
Physical Address 0x400C 5030 Instance 0x400C 5030
Description Events to MCU Flags

This register contains a collection of event flags routed to MCU domain.

To clear an event flag, write to EVTOMCUFLAGSCLR or write 0 to event flag in this register. Follow procedure described in AUX_SYSIF:WUCLR to clear AUX_WU_EV event flag.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUX_TIMER2_PULSE This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE occurs on EVSTAT3.AUX_TIMER2_PULSE. RW 0
14 AUX_TIMER2_EV3 This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 occurs on EVSTAT3.AUX_TIMER2_EV3. RW 0
13 AUX_TIMER2_EV2 This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 occurs on EVSTAT3.AUX_TIMER2_EV2. RW 0
12 AUX_TIMER2_EV1 This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 occurs on EVSTAT3.AUX_TIMER2_EV1. RW 0
11 AUX_TIMER2_EV0 This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 occurs on EVSTAT3.AUX_TIMER2_EV0. RW 0
10 AUX_ADC_IRQ This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ. RW 0
9 MCU_OBSMUX0 This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0. RW 0
8 AUX_ADC_FIFO_ALMOST_FULL This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL. RW 0
7 AUX_ADC_DONE This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE. RW 0
6 AUX_SMPH_AUTOTAKE_DONE This event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE. RW 0
5 AUX_TIMER1_EV This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV. RW 0
4 AUX_TIMER0_EV This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV. RW 0
3 AUX_TDC_DONE This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE. RW 0
2 AUX_COMPB This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB. RW 0
1 AUX_COMPA This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA. RW 0
0 AUX_WU_EV This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on reduction-OR of the AUX_SYSIF:WUFLAGS register. RW 0

TOP:AUX_EVCTL:EVTOMCUPOL

Address Offset 0x0000 0034
Physical Address 0x400C 5034 Instance 0x400C 5034
Description Event To MCU Polarity

Event source polarity configuration for EVTOMCUFLAGS.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUX_TIMER2_PULSE Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
14 AUX_TIMER2_EV3 Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
13 AUX_TIMER2_EV2 Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
12 AUX_TIMER2_EV1 Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
11 AUX_TIMER2_EV0 Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
10 AUX_ADC_IRQ Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
9 MCU_OBSMUX0 Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
8 AUX_ADC_FIFO_ALMOST_FULL Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
7 AUX_ADC_DONE Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
6 AUX_SMPH_AUTOTAKE_DONE Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
5 AUX_TIMER1_EV Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
4 AUX_TIMER0_EV Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
3 AUX_TDC_DONE Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
2 AUX_COMPB Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB.
Value ENUM Name Description
0x0 RISE Rising edge
0x1 FALL Falling edge
RW 0
1 AUX_COMPA Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA.
Value ENUM Name Description
0x0 RISE Rising edge
0x1 FALL Falling edge
RW 0
0 AUX_WU_EV Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0

TOP:AUX_EVCTL:EVTOMCUFLAGSCLR

Address Offset 0x0000 0038
Physical Address 0x400C 5038 Instance 0x400C 5038
Description Events To MCU Flags Clear

Clear event flags in EVTOMCUFLAGS.

In order to clear a level sensitive event flag, the event must be deasserted.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUX_TIMER2_PULSE Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE.

Read value is 0.		 WO 0
14 AUX_TIMER2_EV3 Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3.

Read value is 0.		 WO 0
13 AUX_TIMER2_EV2 Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2.

Read value is 0.		 WO 0
12 AUX_TIMER2_EV1 Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1.

Read value is 0.		 WO 0
11 AUX_TIMER2_EV0 Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0.

Read value is 0.		 WO 0
10 AUX_ADC_IRQ Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ.

Read value is 0.		 WO 0
9 MCU_OBSMUX0 Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0.

Read value is 0.		 WO 0
8 AUX_ADC_FIFO_ALMOST_FULL Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.

Read value is 0.		 WO 0
7 AUX_ADC_DONE Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE.

Read value is 0.		 WO 0
6 AUX_SMPH_AUTOTAKE_DONE Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.

Read value is 0.		 WO 0
5 AUX_TIMER1_EV Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV.

Read value is 0.		 WO 0
4 AUX_TIMER0_EV Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV.

Read value is 0.		 WO 0
3 AUX_TDC_DONE Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE.

Read value is 0.		 WO 0
2 AUX_COMPB Write 1 to clear EVTOMCUFLAGS.AUX_COMPB.

Read value is 0.		 WO 0
1 AUX_COMPA Write 1 to clear EVTOMCUFLAGS.AUX_COMPA.

Read value is 0.		 WO 0
0 AUX_WU_EV Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV.

Read value is 0.		 WO 0

TOP:AUX_EVCTL:COMBEVTOMCUMASK

Address Offset 0x0000 003C
Physical Address 0x400C 503C Instance 0x400C 503C
Description Combined Event To MCU Mask

Select event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU.

The AUX_COMB event is high as long as one or more of the included event flags are set.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUX_TIMER2_PULSE EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
14 AUX_TIMER2_EV3 EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
13 AUX_TIMER2_EV2 EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
12 AUX_TIMER2_EV1 EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
11 AUX_TIMER2_EV0 EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
10 AUX_ADC_IRQ EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
9 MCU_OBSMUX0 EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
8 AUX_ADC_FIFO_ALMOST_FULL EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
7 AUX_ADC_DONE EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
6 AUX_SMPH_AUTOTAKE_DONE EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
5 AUX_TIMER1_EV EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
4 AUX_TIMER0_EV EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
3 AUX_TDC_DONE EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
2 AUX_COMPB EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event.

0: Exclude
1: Include.		 RW 0
1 AUX_COMPA EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
0 AUX_WU_EV EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0

TOP:AUX_EVCTL:EVOBSCFG

Address Offset 0x0000 0040
Physical Address 0x400C 5040 Instance 0x400C 5040
Description Event Observation Configuration
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:0 EVOBS_SEL Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIO.
Value ENUM Name Description
0x0 AUXIO0 EVSTAT0.AUXIO0
0x1 AUXIO1 EVSTAT0.AUXIO1
0x2 AUXIO2 EVSTAT0.AUXIO2
0x3 AUXIO3 EVSTAT0.AUXIO3
0x4 AUXIO4 EVSTAT0.AUXIO4
0x5 AUXIO5 EVSTAT0.AUXIO5
0x6 AUXIO6 EVSTAT0.AUXIO6
0x7 AUXIO7 EVSTAT0.AUXIO7
0x8 AUXIO8 EVSTAT0.AUXIO8
0x9 AUXIO9 EVSTAT0.AUXIO9
0xA AUXIO10 EVSTAT0.AUXIO10
0xB AUXIO11 EVSTAT0.AUXIO11
0xC AUXIO12 EVSTAT0.AUXIO12
0xD AUXIO13 EVSTAT0.AUXIO13
0xE AUXIO14 EVSTAT0.AUXIO14
0xF AUXIO15 EVSTAT0.AUXIO15
0x10 AUXIO16 EVSTAT1.AUXIO16
0x11 AUXIO17 EVSTAT1.AUXIO17
0x12 AUXIO18 EVSTAT1.AUXIO18
0x13 AUXIO19 EVSTAT1.AUXIO19
0x14 AUXIO20 EVSTAT1.AUXIO20
0x15 AUXIO21 EVSTAT1.AUXIO21
0x16 AUXIO22 EVSTAT1.AUXIO22
0x17 AUXIO23 EVSTAT1.AUXIO23
0x18 AUXIO24 EVSTAT1.AUXIO24
0x19 AUXIO25 EVSTAT1.AUXIO25
0x1A AUXIO26 EVSTAT1.AUXIO26
0x1B AUXIO27 EVSTAT1.AUXIO27
0x1C AUXIO28 EVSTAT1.AUXIO28
0x1D AUXIO29 EVSTAT1.AUXIO29
0x1E AUXIO30 EVSTAT1.AUXIO30
0x1F AUXIO31 EVSTAT1.AUXIO31
0x20 MANUAL_EV EVSTAT2.MANUAL_EV
0x21 AON_RTC_CH2 EVSTAT2.AON_RTC_CH2
0x22 AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY
0x23 AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ
0x24 AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD
0x25 AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD
0x26 SCLK_LF EVSTAT2.SCLK_LF
0x27 PWR_DWN EVSTAT2.PWR_DWN
0x28 MCU_ACTIVE EVSTAT2.MCU_ACTIVE
0x29 VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE
0x2A ACLK_REF EVSTAT2.ACLK_REF
0x2B MCU_EV EVSTAT2.MCU_EV
0x2C MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0
0x2D MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1
0x2E AUX_COMPA EVSTAT2.AUX_COMPA
0x2F AUX_COMPB EVSTAT2.AUX_COMPB
0x30 AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0
0x31 AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1
0x32 AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2
0x33 AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3
0x34 AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE
0x35 AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV
0x36 AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV
0x37 AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE
0x38 AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N
0x39 AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE
0x3A AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ
0x3B AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
0x3C AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
0x3D AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
0x3E AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE
0x3F AUX_TIMER2_CLKSW_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
RW 0b00 0000

TOP:AUX_EVCTL:PROGDLY

Address Offset 0x0000 0044
Physical Address 0x400C 5044 Instance 0x400C 5044
Description Programmable Delay
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE VALUE decrements to 0 at a rate of 1 MHz.

The event AUX_PROG_DLY_IDLE is high when VALUE is 0, otherwise it is low.

Only use the programmable delay counter and the AUX_PROG_DLY_IDLE event when AUX_SYSIF:OPMODEACK.ACK equals A or LP.

Decrementation of VALUE halts when either is true:
- AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode.
- AUX_SYSIF:TIMERHALT.PROGDLY is set.		 RW 0x0000

TOP:AUX_EVCTL:MANUAL

Address Offset 0x0000 0048
Physical Address 0x400C 5048 Instance 0x400C 5048
Description Manual

Programmable event.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 EV This bit field sets the value of EVSTAT2.MANUAL_EV. RW 0

TOP:AUX_EVCTL:EVSTAT0L

Address Offset 0x0000 004C
Physical Address 0x400C 504C Instance 0x400C 504C
Description Event Status 0 Low
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ALIAS_EV Alias of EVSTAT0 event 7 down to 0. RO 0x00

TOP:AUX_EVCTL:EVSTAT0H

Address Offset 0x0000 0050
Physical Address 0x400C 5050 Instance 0x400C 5050
Description Event Status 0 High
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ALIAS_EV Alias of EVSTAT0 event 15 down to 8. RO 0x00

TOP:AUX_EVCTL:EVSTAT1L

Address Offset 0x0000 0054
Physical Address 0x400C 5054 Instance 0x400C 5054
Description Event Status 1 Low
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ALIAS_EV Alias of EVSTAT1 event 7 down to 0. RO 0x00

TOP:AUX_EVCTL:EVSTAT1H

Address Offset 0x0000 0058
Physical Address 0x400C 5058 Instance 0x400C 5058
Description Event Status 1 High
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ALIAS_EV Alias of EVSTAT1 event 15 down to 8. RO 0x00

TOP:AUX_EVCTL:EVSTAT2L

Address Offset 0x0000 005C
Physical Address 0x400C 505C Instance 0x400C 505C
Description Event Status 2 Low
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ALIAS_EV Alias of EVSTAT2 event 7 down to 0. RO 0x00

TOP:AUX_EVCTL:EVSTAT2H

Address Offset 0x0000 0060
Physical Address 0x400C 5060 Instance 0x400C 5060
Description Event Status 2 High
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ALIAS_EV Alias of EVSTAT2 event 15 down to 8. RO 0x00

TOP:AUX_EVCTL:EVSTAT3L

Address Offset 0x0000 0064
Physical Address 0x400C 5064 Instance 0x400C 5064
Description Event Status 3 Low
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ALIAS_EV Alias of EVSTAT3 event 7 down to 0. RO 0x00

TOP:AUX_EVCTL:EVSTAT3H

Address Offset 0x0000 0068
Physical Address 0x400C 5068 Instance 0x400C 5068
Description Event Status 3 High
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ALIAS_EV Alias of EVSTAT3 event 15 down to 8. RO 0x00


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