AUX_TIMER2

Instance: AUX_TIMER2
Component: AUX_TIMER2
Base address: 0x400C3000


AUX Timer2 (AUX_TIMER2) offers flexible:
- generation of waveforms and events.
- capture of signal period and duty cycle.
- generation of single clock pulse.

It consists of a:
- 16-bit counter.
- 4 capture compare channels.
- 4 event outputs, which are mapped to AUX event bus, see EVCTL.

Each channel subscribes to the asynchronous AUX event bus. They can control one or more event outputs in both capture and compare modes. AUX_SYSIF:TIMER2CLKCTL.SRC selects clock source for the timer.

TOP:AUX_TIMER2 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CTL

RW

32

0x0000 0000

0x0000 0000

0x400C 3000

TARGET

RW

32

0x0000 0000

0x0000 0004

0x400C 3004

SHDWTARGET

RW

32

0x0000 0000

0x0000 0008

0x400C 3008

CNTR

RO

32

0x0000 0000

0x0000 000C

0x400C 300C

PRECFG

RW

32

0x0000 0000

0x0000 0010

0x400C 3010

EVCTL

WO

32

0x0000 0000

0x0000 0014

0x400C 3014

PULSETRIG

RW

32

0x0000 0000

0x0000 0018

0x400C 3018

CH0EVCFG

RW

32

0x0000 0000

0x0000 0080

0x400C 3080

CH0CCFG

RW

32

0x0000 0000

0x0000 0084

0x400C 3084

CH0PCC

RW

32

0x0000 0000

0x0000 0088

0x400C 3088

CH0CC

RW

32

0x0000 0000

0x0000 008C

0x400C 308C

CH1EVCFG

RW

32

0x0000 0000

0x0000 0090

0x400C 3090

CH1CCFG

RW

32

0x0000 0000

0x0000 0094

0x400C 3094

CH1PCC

RW

32

0x0000 0000

0x0000 0098

0x400C 3098

CH1CC

RW

32

0x0000 0000

0x0000 009C

0x400C 309C

CH2EVCFG

RW

32

0x0000 0000

0x0000 00A0

0x400C 30A0

CH2CCFG

RW

32

0x0000 0000

0x0000 00A4

0x400C 30A4

CH2PCC

RW

32

0x0000 0000

0x0000 00A8

0x400C 30A8

CH2CC

RW

32

0x0000 0000

0x0000 00AC

0x400C 30AC

CH3EVCFG

RW

32

0x0000 0000

0x0000 00B0

0x400C 30B0

CH3CCFG

RW

32

0x0000 0000

0x0000 00B4

0x400C 30B4

CH3PCC

RW

32

0x0000 0000

0x0000 00B8

0x400C 30B8

CH3CC

RW

32

0x0000 0000

0x0000 00BC

0x400C 30BC

TOP:AUX_TIMER2 Register Descriptions

TOP:AUX_TIMER2:CTL

Address Offset 0x0000 0000
Physical Address 0x400C 3000 Instance 0x400C 3000
Description Timer Control
Type RW
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6 CH3_RESET Channel 3 reset.

0: No effect.
1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG.

Read returns 0.		 RW 0
5 CH2_RESET Channel 2 reset.

0: No effect.
1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG.

Read returns 0.		 RW 0
4 CH1_RESET Channel 1 reset.

0: No effect.
1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG.

Read returns 0.		 RW 0
3 CH0_RESET Channel 0 reset.

0: No effect.
1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG.

Read returns 0.		 RW 0
2 TARGET_EN Select counter target value.

You must select TARGET to use shadow target functionality.
Value ENUM Name Description
0x0 CNTR_MAX 65535
0x1 TARGET TARGET.VALUE
RW 0
1:0 MODE Timer mode control.

The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or UPDWN_PER.

When you write MODE all internally queued updates to CHnCC and TARGET clear.
Value ENUM Name Description
0x0 DIS Disable timer. Updates to counter, channels, and events stop.
0x1 UP_ONCE Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS.
0x2 UP_PER Count up periodically. The timer increments from 0 to target value, repeatedly.

Period = (target value + 1) * timer clock period
0x3 UPDWN_PER Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly.

Period = (target value * 2) * timer clock period
RW 0b00

TOP:AUX_TIMER2:TARGET

Address Offset 0x0000 0004
Physical Address 0x400C 3004 Instance 0x400C 3004
Description Target

User defined counter target.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE 16 bit user defined counter target value, which is used when selected by CTL.TARGET_EN. RW 0x0000

TOP:AUX_TIMER2:SHDWTARGET

Address Offset 0x0000 0008
Physical Address 0x400C 3008 Instance 0x400C 3008
Description Shadow Target
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Target value for next counter period.

The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy does not happen when you restart the timer.

This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM.		 RW 0x0000

TOP:AUX_TIMER2:CNTR

Address Offset 0x0000 000C
Physical Address 0x400C 300C Instance 0x400C 300C
Description Counter
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE 16 bit current counter value. RO 0x0000

TOP:AUX_TIMER2:PRECFG

Address Offset 0x0000 0010
Physical Address 0x400C 3010 Instance 0x400C 3010
Description Clock Prescaler Configuration
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 CLKDIV Clock division.

CLKDIV determines the timer clock frequency for counter, synchronization, and timer event updates. The timer clock frequency is the clock selected by AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the timer clock period.

0x00: Divide by 1.
0x01: Divide by 2.
...
0xFF: Divide by 256.		 RW 0x00

TOP:AUX_TIMER2:EVCTL

Address Offset 0x0000 0014
Physical Address 0x400C 3014 Instance 0x400C 3014
Description Event Control

Set and clear individual events manually. Manual update of an event takes priority over automatic channel updates to the same event. You cannot set and clear an event at the same time, such requests will be neglected.

An event can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an event at the same time.

The four events connect to the asynchronous AUX event bus:
- Event 0 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
- Event 1 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
- Event 2 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
- Event 3 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
Type WO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. WO 0x00 0000
7 EV3_SET Set event 3.

Write 1 to set event 3.		 WO 0
6 EV3_CLR Clear event 3.

Write 1 to clear event 3.		 WO 0
5 EV2_SET Set event 2.

Write 1 to set event 2.		 WO 0
4 EV2_CLR Clear event 2.

Write 1 to clear event 2.		 WO 0
3 EV1_SET Set event 1.

Write 1 to set event 1.		 WO 0
2 EV1_CLR Clear event 1.

Write 1 to clear event 1.		 WO 0
1 EV0_SET Set event 0.

Write 1 to set event 0.		 WO 0
0 EV0_CLR Clear event 0.

Write 1 to clear event 0.		 WO 0

TOP:AUX_TIMER2:PULSETRIG

Address Offset 0x0000 0018
Physical Address 0x400C 3018 Instance 0x400C 3018
Description Pulse Trigger
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 TRIG Pulse trigger.

Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC.		 WO 0

TOP:AUX_TIMER2:CH0EVCFG

Address Offset 0x0000 0080
Physical Address 0x400C 3080 Instance 0x400C 3080
Description Channel 0 Event Configuration

This register configures channel function and enables event outputs.

Each channel has an edge-detection circuit with memory. The circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode.

The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 EV3_GEN Event 3 enable.

0: Channel 0 does not control event 3.
1: Channel 0 controls event 3.

When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.		 RW 0
6 EV2_GEN Event 2 enable.

0: Channel 0 does not control event 2.
1: Channel 0 controls event 2.

When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.		 RW 0
5 EV1_GEN Event 1 enable.

0: Channel 0 does not control event 1.
1: Channel 0 controls event 1.

When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.		 RW 0
4 EV0_GEN Event 0 enable.

0: Channel 0 does not control event 0.
1: Channel 0 controls event 0.

When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.		 RW 0
3:0 CCACT Capture-Compare action.

Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events.
Value ENUM Name Description
0x0 DIS Disable channel.
0x1 SET_ON_CAPT_DIS Set on capture, and then disable channel.

Channel function sequence:
- Set enabled events on capture event and copy CNTR.VALUE to CH0CC.VALUE.
- Disable channel.

Primary use scenario is to select this function before you start the timer.
Follow these steps if you need to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no event enable.
- Configure CH0CCFG (optional).
- Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0x2 CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Clear enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH0CC.VALUE = CNTR.VALUE.
- Disable channel.

Enabled events are set when CH0CC.VALUE = 0 and CNTR.VALUE = 0.
0x3 SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Set enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH0CC.VALUE = CNTR.VALUE.
- Disable channel.

Enabled events are cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 0.
0x4 CLR_ON_CMP_DIS Clear on compare, and then disable channel.

Channel function sequence:
- Clear enabled events when CH0CC.VALUE = CNTR.VALUE.
- Disable channel.
0x5 SET_ON_CMP_DIS Set on compare, and then disable channel.

Channel function sequence:
- Set enabled events when CH0CC.VALUE = CNTR.VALUE.
- Disable channel.
0x6 TGL_ON_CMP_DIS Toggle on compare, and then disable channel.

Channel function sequence:
- Toggle enabled events when CH0CC.VALUE = CNTR.VALUE.
- Disable channel.
0x7 PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.

Channel function sequence:
- Pulse enabled events when CH0CC.VALUE = CNTR.VALUE.
- Disable channel.

The event is high for two timer clock periods.
0x8 PER_PULSE_WIDTH_MEAS Period and pulse width measurement.

Continuously capture period and pulse width of the signal selected by CH0CCFG.CAPT_SRC relative to the signal edge given by CH0CCFG.EDGE.

Set enabled events when CH0CC.VALUE contains signal period and CH0PCC.VALUE contains signal pulse width.

Notes:
- Make sure that you configure CH0CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when CH0CC.VALUE contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- If you want to observe a timeout event configure another channel to SET_ON_CAPT.

Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period.
- Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period.
0x9 SET_ON_CAPT Set on capture repeatedly.

Channel function sequence:
- Set enabled events on capture event and copy CNTR.VALUE to CH0CC.VALUE.

Primary use scenario is to select this function before you start the timer.
Follow these steps if you need to select this function while CTL.MODE is different from DIS:
- Select this function with no event enable.
- Configure CH0CCFG (optional).
- Wait for three timer clock periods as defined in PRECFG before you enable events.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0xA CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH0CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:

When CH0CC.VALUE <= TARGET.VALUE:
Duty cycle = 1 - ( CH0CC.VALUE / TARGET.VALUE ).

When CH0CC.VALUE > TARGET.VALUE:
Duty cycle = 0.

Enabled events are set when CH0CC.VALUE = 0 and CNTR.VALUE = 0.
0xB SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.

Channel function sequence:
- Set enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH0CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:

When CH0CC.VALUE <= TARGET.VALUE:
Duty cycle = CH0CC.VALUE / ( TARGET.VALUE + 1 ).

When CH0CC.VALUE > TARGET.VALUE:
Duty cycle = 1.

Enabled events are cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 0.
0xC CLR_ON_CMP Clear on compare repeatedly.

Channel function sequence:
- Clear enabled events when CH0CC.VALUE = CNTR.VALUE.
0xD SET_ON_CMP Set on compare repeatedly.

Channel function sequence:
- Set enabled events when CH0CC.VALUE = CNTR.VALUE.
0xE TGL_ON_CMP Toggle on compare repeatedly.

Channel function sequence:
- Toggle enabled events when CH0CC.VALUE = CNTR.VALUE.
0xF PULSE_ON_CMP Pulse on compare repeatedly.

Channel function sequence:
- Pulse enabled events when CH0CC.VALUE = CNTR.VALUE.

The event is high for two timer clock periods.
RW 0x0

TOP:AUX_TIMER2:CH0CCFG

Address Offset 0x0000 0084
Physical Address 0x400C 3084 Instance 0x400C 3084
Description Channel 0 Capture Configuration
Type RW
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6:1 CAPT_SRC Select capture signal source from the asynchronous AUX event bus.

The selected signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH0EVCFG
- this register is reconfigured while CTL.MODE is different from DIS.

You can avoid false capture events. When wanted channel function is:
- SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT.
- SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT.
- PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH0EVCFG.CCACT.

If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.
Value ENUM Name Description
0x0 AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
0x1 AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
0x2 AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
0x3 AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
0x4 AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
0x5 AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
0x6 AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
0x7 AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
0x8 AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
0x9 AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
0xA AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
0xB AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
0xC AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
0xD AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
0xE AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
0xF AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
0x10 AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
0x11 AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
0x12 AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
0x13 AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
0x14 AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
0x15 AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
0x16 AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
0x17 AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
0x18 AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
0x19 AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
0x1A AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
0x1B AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
0x1C AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
0x1D AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
0x1E AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
0x1F AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
0x20 MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
0x21 AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
0x22 AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
0x23 AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
0x24 AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
0x25 AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
0x26 SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
0x27 PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
0x28 MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
0x29 VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
0x2A ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
0x2B MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
0x2C MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
0x2D MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
0x2E AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
0x2F AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
0x30 AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
0x31 AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
0x32 AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
0x33 AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
0x35 AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
0x36 AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
0x37 AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
0x38 AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
0x39 AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
0x3A AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
0x3B AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
0x3C AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
0x3D AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
0x3F NO_EVENT No event.
RW 0b00 0000
0 EDGE Edge configuration.

Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH0EVCFG.CCACT.
Value ENUM Name Description
0x0 FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC.
0x1 RISING Capture CNTR.VALUE at rising edge of CAPT_SRC.
RW 0

TOP:AUX_TIMER2:CH0PCC

Address Offset 0x0000 0088
Physical Address 0x400C 3088 Instance 0x400C 3088
Description Channel 0 Pipeline Capture Compare
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Pipeline Capture Compare value.

16-bit user defined pipeline compare value or channel-updated capture value.

Compare mode:
An update of VALUE will be transferred to CH0CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH0CCFG.EDGE and CH0CCFG.CAPT_SRC.		 RW 0x0000

TOP:AUX_TIMER2:CH0CC

Address Offset 0x0000 008C
Physical Address 0x400C 308C Instance 0x400C 308C
Description Channel 0 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Capture Compare value.

16-bit user defined compare value or channel-updated capture value.

Compare mode:
VALUE is compared against CNTR.VALUE and an event is generated as specified by CH0EVCFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VALUE when a capture event occurs. CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture value.		 RW 0x0000

TOP:AUX_TIMER2:CH1EVCFG

Address Offset 0x0000 0090
Physical Address 0x400C 3090 Instance 0x400C 3090
Description Channel 1 Event Configuration

This register configures channel function and enables event outputs.

Each channel has an edge-detection circuit with memory. The circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode.

The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 EV3_GEN Event 3 enable.

0: Channel 1 does not control event 3.
1: Channel 1 controls event 3.

When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.		 RW 0
6 EV2_GEN Event 2 enable.

0: Channel 1 does not control event 2.
1: Channel 1 controls event 2.

When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.		 RW 0
5 EV1_GEN Event 1 enable.

0: Channel 1 does not control event 1.
1: Channel 1 controls event 1.

When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.		 RW 0
4 EV0_GEN Event 0 enable.

0: Channel 1 does not control event 0.
1: Channel 1 controls event 0.

When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.		 RW 0
3:0 CCACT Capture-Compare action.

Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events.
Value ENUM Name Description
0x0 DIS Disable channel.
0x1 SET_ON_CAPT_DIS Set on capture, and then disable channel.

Channel function sequence:
- Set enabled events on capture event and copy CNTR.VALUE to CH1CC.VALUE.
- Disable channel.

Primary use scenario is to select this function before you start the timer.
Follow these steps if you need to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no event enable.
- Configure CH1CCFG (optional).
- Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0x2 CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Clear enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH1CC.VALUE = CNTR.VALUE.
- Disable channel.

Enabled events are set when CH1CC.VALUE = 0 and CNTR.VALUE = 0.
0x3 SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Set enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH1CC.VALUE = CNTR.VALUE.
- Disable channel.

Enabled events are cleared when CH1CC.VALUE = 0 and CNTR.VALUE = 0.
0x4 CLR_ON_CMP_DIS Clear on compare, and then disable channel.

Channel function sequence:
- Clear enabled events when CH1CC.VALUE = CNTR.VALUE.
- Disable channel.
0x5 SET_ON_CMP_DIS Set on compare, and then disable channel.

Channel function sequence:
- Set enabled events when CH1CC.VALUE = CNTR.VALUE.
- Disable channel.
0x6 TGL_ON_CMP_DIS Toggle on compare, and then disable channel.

Channel function sequence:
- Toggle enabled events when CH1CC.VALUE = CNTR.VALUE.
- Disable channel.
0x7 PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.

Channel function sequence:
- Pulse enabled events when CH1CC.VALUE = CNTR.VALUE.
- Disable channel.

The event is high for two timer clock periods.
0x8 PER_PULSE_WIDTH_MEAS Period and pulse width measurement.

Continuously capture period and pulse width of the signal selected by CH1CCFG.CAPT_SRC relative to the signal edge given by CH1CCFG.EDGE.

Set enabled events when CH1CC.VALUE contains signal period and CH1PCC.VALUE contains signal pulse width.

Notes:
- Make sure that you configure CH1CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when CH1CC.VALUE contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- If you want to observe a timeout event configure another channel to SET_ON_CAPT.

Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period.
- Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period.
0x9 SET_ON_CAPT Set on capture repeatedly.

Channel function sequence:
- Set enabled events on capture event and copy CNTR.VALUE to CH1CC.VALUE.

Primary use scenario is to select this function before you start the timer.
Follow these steps if you need to select this function while CTL.MODE is different from DIS:
- Select this function with no event enable.
- Configure CH1CCFG (optional).
- Wait for three timer clock periods as defined in PRECFG before you enable events.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0xA CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH1CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:

When CH1CC.VALUE <= TARGET.VALUE:
Duty cycle = 1 - ( CH1CC.VALUE / TARGET.VALUE ).

When CH1CC.VALUE > TARGET.VALUE:
Duty cycle = 0.

Enabled events are set when CH1CC.VALUE = 0 and CNTR.VALUE = 0.
0xB SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.

Channel function sequence:
- Set enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH1CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:

When CH1CC.VALUE <= TARGET.VALUE:
Duty cycle = CH1CC.VALUE / ( TARGET.VALUE + 1 ).

When CH1CC.VALUE > TARGET.VALUE:
Duty cycle = 1.

Enabled events are cleared when CH1CC.VALUE = 0 and CNTR.VALUE = 0.
0xC CLR_ON_CMP Clear on compare repeatedly.

Channel function sequence:
- Clear enabled events when CH1CC.VALUE = CNTR.VALUE.
0xD SET_ON_CMP Set on compare repeatedly.

Channel function sequence:
- Set enabled events when CH1CC.VALUE = CNTR.VALUE.
0xE TGL_ON_CMP Toggle on compare repeatedly.

Channel function sequence:
- Toggle enabled events when CH1CC.VALUE = CNTR.VALUE.
0xF PULSE_ON_CMP Pulse on compare repeatedly.

Channel function sequence:
- Pulse enabled events when CH1CC.VALUE = CNTR.VALUE.

The event is high for two timer clock periods.
RW 0x0

TOP:AUX_TIMER2:CH1CCFG

Address Offset 0x0000 0094
Physical Address 0x400C 3094 Instance 0x400C 3094
Description Channel 1 Capture Configuration
Type RW
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6:1 CAPT_SRC Select capture signal source from the asynchronous AUX event bus.

The selected signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH1EVCFG
- this register is reconfigured while CTL.MODE is different from DIS.

You can avoid false capture events. When wanted channel function is:
- SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT.
- SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT.
- PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH1EVCFG.CCACT.

If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.
Value ENUM Name Description
0x0 AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
0x1 AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
0x2 AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
0x3 AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
0x4 AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
0x5 AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
0x6 AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
0x7 AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
0x8 AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
0x9 AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
0xA AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
0xB AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
0xC AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
0xD AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
0xE AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
0xF AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
0x10 AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
0x11 AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
0x12 AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
0x13 AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
0x14 AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
0x15 AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
0x16 AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
0x17 AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
0x18 AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
0x19 AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
0x1A AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
0x1B AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
0x1C AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
0x1D AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
0x1E AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
0x1F AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
0x20 MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
0x21 AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
0x22 AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
0x23 AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
0x24 AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
0x25 AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
0x26 SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
0x27 PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
0x28 MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
0x29 VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
0x2A ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
0x2B MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
0x2C MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
0x2D MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
0x2E AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
0x2F AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
0x30 AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
0x31 AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
0x32 AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
0x33 AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
0x35 AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
0x36 AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
0x37 AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
0x38 AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
0x39 AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
0x3A AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
0x3B AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
0x3C AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
0x3D AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
0x3F NO_EVENT No event.
RW 0b00 0000
0 EDGE Edge configuration.

Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH1EVCFG.CCACT.
Value ENUM Name Description
0x0 FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC.
0x1 RISING Capture CNTR.VALUE at rising edge of CAPT_SRC.
RW 0

TOP:AUX_TIMER2:CH1PCC

Address Offset 0x0000 0098
Physical Address 0x400C 3098 Instance 0x400C 3098
Description Channel 1 Pipeline Capture Compare
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Pipeline Capture Compare value.

16-bit user defined pipeline compare value or channel-updated capture value.

Compare mode:
An update of VALUE will be transferred to CH1CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH1CCFG.EDGE and CH1CCFG.CAPT_SRC.		 RW 0x0000

TOP:AUX_TIMER2:CH1CC

Address Offset 0x0000 009C
Physical Address 0x400C 309C Instance 0x400C 309C
Description Channel 1 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Capture Compare value.

16-bit user defined compare value or channel-updated capture value.

Compare mode:
VALUE is compared against CNTR.VALUE and an event is generated as specified by CH1EVCFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VALUE when a capture event occurs. CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture value.		 RW 0x0000

TOP:AUX_TIMER2:CH2EVCFG

Address Offset 0x0000 00A0
Physical Address 0x400C 30A0 Instance 0x400C 30A0
Description Channel 2 Event Configuration

This register configures channel function and enables event outputs.

Each channel has an edge-detection circuit with memory. The circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode.

The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 EV3_GEN Event 3 enable.

0: Channel 2 does not control event 3.
1: Channel 2 controls event 3.

When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.		 RW 0
6 EV2_GEN Event 2 enable.

0: Channel 2 does not control event 2.
1: Channel 2 controls event 2.

When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.		 RW 0
5 EV1_GEN Event 1 enable.

0: Channel 2 does not control event 1.
1: Channel 2 controls event 1.

When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.		 RW 0
4 EV0_GEN Event 0 enable.

0: Channel 2 does not control event 0.
1: Channel 2 controls event 0.

When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.		 RW 0
3:0 CCACT Capture-Compare action.

Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events.
Value ENUM Name Description
0x0 DIS Disable channel.
0x1 SET_ON_CAPT_DIS Set on capture, and then disable channel.

Channel function sequence:
- Set enabled events on capture event and copy CNTR.VALUE to CH2CC.VALUE.
- Disable channel.

Primary use scenario is to select this function before you start the timer.
Follow these steps if you need to select this function while CTL.MODE is different from DIS:
- Set to SET_ON_CAPT with no event enable.
- Configure CH2CCFG (optional).
- Wait for three timer clock periods as defined in PRECFG before you set to SET_ON_CAPT_DIS. Event enable is optional.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0x2 CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Clear enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH2CC.VALUE = CNTR.VALUE.
- Disable channel.

Enabled events are set when CH2CC.VALUE = 0 and CNTR.VALUE = 0.
0x3 SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Set enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH2CC.VALUE = CNTR.VALUE.
- Disable channel.

Enabled events are cleared when CH2CC.VALUE = 0 and CNTR.VALUE = 0.
0x4 CLR_ON_CMP_DIS Clear on compare, and then disable channel.

Channel function sequence:
- Clear enabled events when CH2CC.VALUE = CNTR.VALUE.
- Disable channel.
0x5 SET_ON_CMP_DIS Set on compare, and then disable channel.

Channel function sequence:
- Set enabled events when CH2CC.VALUE = CNTR.VALUE.
- Disable channel.
0x6 TGL_ON_CMP_DIS Toggle on compare, and then disable channel.

Channel function sequence:
- Toggle enabled events when CH2CC.VALUE = CNTR.VALUE.
- Disable channel.
0x7 PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.

Channel function sequence:
- Pulse enabled events when CH2CC.VALUE = CNTR.VALUE.
- Disable channel.

The event is high for two timer clock periods.
0x8 PER_PULSE_WIDTH_MEAS Period and pulse width measurement.

Continuously capture period and pulse width of the signal selected by CH2CCFG.CAPT_SRC relative to the signal edge given by CH2CCFG.EDGE.

Set enabled events when CH2CC.VALUE contains signal period and CH2PCC.VALUE contains signal pulse width.

Notes:
- Make sure that you configure CH2CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when CH2CC.VALUE contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- If you want to observe a timeout event configure another channel to SET_ON_CAPT.

Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period.
- Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period.
0x9 SET_ON_CAPT Set on capture repeatedly.

Channel function sequence:
- Set enabled events on capture event and copy CNTR.VALUE to CH2CC.VALUE.

Primary use scenario is to select this function before you start the timer.
Follow these steps if you need to select this function while CTL.MODE is different from DIS:
- Select this function with no event enable.
- Configure CH2CCFG (optional).
- Wait for three timer clock periods as defined in PRECFG before you enable events.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0xA CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH2CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:

When CH2CC.VALUE <= TARGET.VALUE:
Duty cycle = 1 - ( CH2CC.VALUE / TARGET.VALUE ).

When CH2CC.VALUE > TARGET.VALUE:
Duty cycle = 0.

Enabled events are set when CH2CC.VALUE = 0 and CNTR.VALUE = 0.
0xB SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.

Channel function sequence:
- Set enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH2CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:

When CH2CC.VALUE <= TARGET.VALUE:
Duty cycle = CH2CC.VALUE / ( TARGET.VALUE + 1 ).

When CH2CC.VALUE > TARGET.VALUE:
Duty cycle = 1.

Enabled events are cleared when CH2CC.VALUE = 0 and CNTR.VALUE = 0.
0xC CLR_ON_CMP Clear on compare repeatedly.

Channel function sequence:
- Clear enabled events when CH2CC.VALUE = CNTR.VALUE.
0xD SET_ON_CMP Set on compare repeatedly.

Channel function sequence:
- Set enabled events when CH2CC.VALUE = CNTR.VALUE.
0xE TGL_ON_CMP Toggle on compare repeatedly.

Channel function sequence:
- Toggle enabled events when CH2CC.VALUE = CNTR.VALUE.
0xF PULSE_ON_CMP Pulse on compare repeatedly.

Channel function sequence:
- Pulse enabled events when CH2CC.VALUE = CNTR.VALUE.

The event is high for two timer clock periods.
RW 0x0

TOP:AUX_TIMER2:CH2CCFG

Address Offset 0x0000 00A4
Physical Address 0x400C 30A4 Instance 0x400C 30A4
Description Channel 2 Capture Configuration
Type RW
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6:1 CAPT_SRC Select capture signal source from the asynchronous AUX event bus.

The selected signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH2EVCFG
- this register is reconfigured while CTL.MODE is different from DIS.

You can avoid false capture events. When wanted channel function is:
- SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT.
- SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT.
- PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH2EVCFG.CCACT.

If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.
Value ENUM Name Description
0x0 AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
0x1 AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
0x2 AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
0x3 AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
0x4 AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
0x5 AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
0x6 AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
0x7 AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
0x8 AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
0x9 AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
0xA AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
0xB AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
0xC AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
0xD AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
0xE AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
0xF AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
0x10 AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
0x11 AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
0x12 AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
0x13 AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
0x14 AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
0x15 AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
0x16 AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
0x17 AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
0x18 AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
0x19 AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
0x1A AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
0x1B AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
0x1C AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
0x1D AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
0x1E AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
0x1F AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
0x20 MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
0x21 AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
0x22 AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
0x23 AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
0x24 AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
0x25 AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
0x26 SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
0x27 PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
0x28 MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
0x29 VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
0x2A ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
0x2B MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
0x2C MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
0x2D MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
0x2E AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
0x2F AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
0x30 AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
0x31 AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
0x32 AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
0x33 AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
0x35 AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
0x36 AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
0x37 AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
0x38 AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
0x39 AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
0x3A AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
0x3B AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
0x3C AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
0x3D AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
0x3F NO_EVENT No event.
RW 0b00 0000
0 EDGE Edge configuration.

Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH2EVCFG.CCACT.
Value ENUM Name Description
0x0 FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC.
0x1 RISING Capture CNTR.VALUE at rising edge of CAPT_SRC.
RW 0

TOP:AUX_TIMER2:CH2PCC

Address Offset 0x0000 00A8
Physical Address 0x400C 30A8 Instance 0x400C 30A8
Description Channel 2 Pipeline Capture Compare
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Pipeline Capture Compare value.

16-bit user defined pipeline compare value or channel-updated capture value.

Compare mode:
An update of VALUE will be transferred to CH2CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH2CCFG.EDGE and CH2CCFG.CAPT_SRC.		 RW 0x0000

TOP:AUX_TIMER2:CH2CC

Address Offset 0x0000 00AC
Physical Address 0x400C 30AC Instance 0x400C 30AC
Description Channel 2 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Capture Compare value.

16-bit user defined compare value or channel-updated capture value.

Compare mode:
VALUE is compared against CNTR.VALUE and an event is generated as specified by CH2EVCFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VALUE when a capture event occurs. CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture value.		 RW 0x0000

TOP:AUX_TIMER2:CH3EVCFG

Address Offset 0x0000 00B0
Physical Address 0x400C 30B0 Instance 0x400C 30B0
Description Channel 3 Event Configuration

This register configures channel function and enables event outputs.

Each channel has an edge-detection circuit with memory. The circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode.

The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 EV3_GEN Event 3 enable.

0: Channel 3 does not control event 3.
1: Channel 3 controls event 3.

When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.		 RW 0
6 EV2_GEN Event 2 enable.

0: Channel 3 does not control event 2.
1: Channel 3 controls event 2.

When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.		 RW 0
5 EV1_GEN Event 1 enable.

0: Channel 3 does not control event 1.
1: Channel 3 controls event 1.

When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.		 RW 0
4 EV0_GEN Event 0 enable.

0: Channel 3 does not control event 0.
1: Channel 3 controls event 0.

When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.		 RW 0
3:0 CCACT Capture-Compare action.

Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events.
Value ENUM Name Description
0x0 DIS Disable channel.
0x1 SET_ON_CAPT_DIS Set on capture, and then disable channel.

Channel function sequence:
- Set enabled events on capture event and copy CNTR.VALUE to CH3CC.VALUE.
- Disable channel.

Primary use scenario is to select this function before you start the timer.
Follow these steps if you need to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no event enable.
- Configure CH3CCFG (optional).
- Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0x2 CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Clear enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.
- Disable channel.

Enabled events are set when CH3CC.VALUE = 0 and CNTR.VALUE = 0.
0x3 SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Set enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.
- Disable channel.

Enabled events are cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 0.
0x4 CLR_ON_CMP_DIS Clear on compare, and then disable channel.

Channel function sequence:
- Clear enabled events when CH3CC.VALUE = CNTR.VALUE.
- Disable channel.
0x5 SET_ON_CMP_DIS Set on compare, and then disable channel.

Channel function sequence:
- Set enabled events when CH3CC.VALUE = CNTR.VALUE.
- Disable channel.
0x6 TGL_ON_CMP_DIS Toggle on compare, and then disable channel.

Channel function sequence:
- Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.
- Disable channel.
0x7 PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.

Channel function sequence:
- Pulse enabled events when CH3CC.VALUE = CNTR.VALUE.
- Disable channel.

The event is high for two timer clock periods.
0x8 PER_PULSE_WIDTH_MEAS Period and pulse width measurement.

Continuously capture period and pulse width of the signal selected by CH3CCFG.CAPT_SRC relative to the signal edge given by CH3CCFG.EDGE.

Set enabled events when CH3CC.VALUE contains signal period and CH3PCC.VALUE contains signal pulse width.

Notes:
- Make sure that you configure CH3CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when CH3CC.VALUE contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- If you want to observe a timeout event configure another channel to SET_ON_CAPT.

Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period.
- Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period.
0x9 SET_ON_CAPT Set on capture repeatedly.

Channel function sequence:
- Set enabled events on capture event and copy CNTR.VALUE to CH3CC.VALUE.

Primary use scenario is to select this function before you start the timer.
Follow these steps if you need to select this function while CTL.MODE is different from DIS:
- Select this function with no event enable.
- Configure CH3CCFG (optional).
- Wait for three timer clock periods as defined in PRECFG before you enable events.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0xA CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:

When CH3CC.VALUE <= TARGET.VALUE:
Duty cycle = 1 - ( CH3CC.VALUE / TARGET.VALUE ).

When CH3CC.VALUE > TARGET.VALUE:
Duty cycle = 0.

Enabled events are set when CH3CC.VALUE = 0 and CNTR.VALUE = 0.
0xB SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.

Channel function sequence:
- Set enabled events when CNTR.VALUE = 0.
- Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:

When CH3CC.VALUE <= TARGET.VALUE:
Duty cycle = CH3CC.VALUE / ( TARGET.VALUE + 1 ).

When CH3CC.VALUE > TARGET.VALUE:
Duty cycle = 1.

Enabled events are cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 0.
0xC CLR_ON_CMP Clear on compare repeatedly.

Channel function sequence:
- Clear enabled events when CH3CC.VALUE = CNTR.VALUE.
0xD SET_ON_CMP Set on compare repeatedly.

Channel function sequence:
- Set enabled events when CH3CC.VALUE = CNTR.VALUE.
0xE TGL_ON_CMP Toggle on compare repeatedly.

Channel function sequence:
- Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.
0xF PULSE_ON_CMP Pulse on compare repeatedly.

Channel function sequence:
- Pulse enabled events when CH3CC.VALUE = CNTR.VALUE.

The event is high for two timer clock periods.
RW 0x0

TOP:AUX_TIMER2:CH3CCFG

Address Offset 0x0000 00B4
Physical Address 0x400C 30B4 Instance 0x400C 30B4
Description Channel 3 Capture Configuration
Type RW
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6:1 CAPT_SRC Select capture signal source from the asynchronous AUX event bus.

The selected signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH3EVCFG
- this register is reconfigured while CTL.MODE is different from DIS.

You can avoid false capture events. When wanted channel function:
- SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT.
- SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT.
- PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH3EVCFG.CCACT.

If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.
Value ENUM Name Description
0x0 AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
0x1 AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
0x2 AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
0x3 AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
0x4 AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
0x5 AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
0x6 AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
0x7 AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
0x8 AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
0x9 AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
0xA AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
0xB AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
0xC AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
0xD AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
0xE AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
0xF AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
0x10 AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
0x11 AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
0x12 AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
0x13 AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
0x14 AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
0x15 AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
0x16 AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
0x17 AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
0x18 AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
0x19 AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
0x1A AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
0x1B AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
0x1C AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
0x1D AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
0x1E AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
0x1F AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
0x20 MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
0x21 AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
0x22 AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
0x23 AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
0x24 AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
0x25 AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
0x26 SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
0x27 PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
0x28 MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
0x29 VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
0x2A ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
0x2B MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
0x2C MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
0x2D MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
0x2E AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
0x2F AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
0x30 AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
0x31 AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
0x32 AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
0x33 AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
0x35 AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
0x36 AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
0x37 AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
0x38 AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
0x39 AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
0x3A AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
0x3B AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
0x3C AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
0x3D AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
0x3F NO_EVENT No event.
RW 0b00 0000
0 EDGE Edge configuration.

Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH3EVCFG.CCACT.
Value ENUM Name Description
0x0 FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC.
0x1 RISING Capture CNTR.VALUE at rising edge of CAPT_SRC.
RW 0

TOP:AUX_TIMER2:CH3PCC

Address Offset 0x0000 00B8
Physical Address 0x400C 30B8 Instance 0x400C 30B8
Description Channel 3 Pipeline Capture Compare
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Pipeline Capture Compare value.

16-bit user defined pipeline compare value or channel-updated capture value.

Compare mode:
An update of VALUE will be transferred to CH3CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH3CCFG.EDGE and CH3CCFG.CAPT_SRC.		 RW 0x0000

TOP:AUX_TIMER2:CH3CC

Address Offset 0x0000 00BC
Physical Address 0x400C 30BC Instance 0x400C 30BC
Description Channel 3 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Capture Compare value.

16-bit user defined compare value or channel-updated capture value.

Compare mode:
VALUE is compared against CNTR.VALUE and an event is generated as specified by CH3EVCFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VALUE when a capture event occurs. CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture value.		 RW 0x0000


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