477 uint32_t ui32TrimValue;
482 if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
483 AON_PMCTL_PWRCTL_EXT_REG_MODE)
489 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
492 HWREG(FLASH_CFG_BASE +
FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
494 ui32Value = ((ui32TrimValue &
495 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
496 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
497 FLASH_CFG_STANDBY_MODE_SEL_S;
499 ui32Value |= ((ui32TrimValue &
500 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
501 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
502 FLASH_CFG_STANDBY_PW_SEL_S;
506 ui32Value |= ((ui32TrimValue &
507 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
508 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
509 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
510 FLASH_CFG_DIS_IDLE_S;
512 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
513 ~(FLASH_CFG_STANDBY_MODE_SEL_M |
514 FLASH_CFG_STANDBY_PW_SEL_M |
515 FLASH_CFG_DIS_STANDBY_M |
516 FLASH_CFG_DIS_IDLE_M)) | ui32Value;
519 if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
522 while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
528 ui32Value = ((ui32TrimValue &
529 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
530 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
531 FLASH_FSEQPMP_VIN_AT_X_S;
536 if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
537 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
539 ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
542 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
543 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
544 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
545 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
546 FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
547 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
555 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
558 HWREG(FLASH_CFG_BASE +
FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
560 ui32Value = ((ui32TrimValue &
561 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
562 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
563 FLASH_CFG_STANDBY_MODE_SEL_S;
565 ui32Value |= ((ui32TrimValue &
566 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
567 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
568 FLASH_CFG_STANDBY_PW_SEL_S;
572 ui32Value |= ((ui32TrimValue &
573 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
574 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
575 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
576 FLASH_CFG_DIS_IDLE_S;
578 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
579 ~(FLASH_CFG_STANDBY_MODE_SEL_M |
580 FLASH_CFG_STANDBY_PW_SEL_M |
581 FLASH_CFG_DIS_STANDBY_M |
582 FLASH_CFG_DIS_IDLE_M)) | ui32Value;
585 if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
588 while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
594 ui32Value = (((ui32TrimValue &
595 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
596 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
597 FLASH_FSEQPMP_VIN_AT_X_S);
602 if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
603 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
605 ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
608 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
609 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
610 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
611 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
612 FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
613 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
#define FCFG1_OFFSET
Definition: flash.h:149