CC23x0R5DriverLibrary
Data Structures | Macros
System Control Block (SCB)
Defines and Type Definitions

Type definitions for the System Control Block Registers. More...

Collaboration diagram for System Control Block (SCB):

Data Structures

struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 

Macros

#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 

Detailed Description

Type definitions for the System Control Block Registers.

Macro Definition Documentation

§ SCB_CPUID_IMPLEMENTER_Pos

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

§ SCB_CPUID_IMPLEMENTER_Msk

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

§ SCB_CPUID_VARIANT_Pos

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

§ SCB_CPUID_VARIANT_Msk

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

§ SCB_CPUID_ARCHITECTURE_Pos

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

§ SCB_CPUID_ARCHITECTURE_Msk

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

§ SCB_CPUID_PARTNO_Pos

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

§ SCB_CPUID_PARTNO_Msk

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

§ SCB_CPUID_REVISION_Pos

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

§ SCB_CPUID_REVISION_Msk

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

§ SCB_ICSR_NMIPENDSET_Pos

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

§ SCB_ICSR_NMIPENDSET_Msk

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Referenced by IntSetPend().

§ SCB_ICSR_PENDSVSET_Pos

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

§ SCB_ICSR_PENDSVSET_Msk

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Referenced by IntSetPend().

§ SCB_ICSR_PENDSVCLR_Pos

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

§ SCB_ICSR_PENDSVCLR_Msk

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Referenced by IntClearPend().

§ SCB_ICSR_PENDSTSET_Pos

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

§ SCB_ICSR_PENDSTSET_Msk

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Referenced by IntSetPend().

§ SCB_ICSR_PENDSTCLR_Pos

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

§ SCB_ICSR_PENDSTCLR_Msk

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Referenced by IntClearPend().

§ SCB_ICSR_ISRPREEMPT_Pos

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

§ SCB_ICSR_ISRPREEMPT_Msk

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

§ SCB_ICSR_ISRPENDING_Pos

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

§ SCB_ICSR_ISRPENDING_Msk

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

§ SCB_ICSR_VECTPENDING_Pos

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

§ SCB_ICSR_VECTPENDING_Msk

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

§ SCB_ICSR_VECTACTIVE_Pos

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

§ SCB_ICSR_VECTACTIVE_Msk

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

§ SCB_AIRCR_VECTKEY_Pos

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Referenced by __NVIC_SystemReset().

§ SCB_AIRCR_VECTKEY_Msk

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

§ SCB_AIRCR_VECTKEYSTAT_Pos

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

§ SCB_AIRCR_VECTKEYSTAT_Msk

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

§ SCB_AIRCR_ENDIANESS_Pos

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

§ SCB_AIRCR_ENDIANESS_Msk

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

§ SCB_AIRCR_SYSRESETREQ_Pos

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

§ SCB_AIRCR_SYSRESETREQ_Msk

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Referenced by __NVIC_SystemReset().

§ SCB_AIRCR_VECTCLRACTIVE_Pos

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

§ SCB_AIRCR_VECTCLRACTIVE_Msk

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

§ SCB_SCR_SEVONPEND_Pos

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

§ SCB_SCR_SEVONPEND_Msk

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

§ SCB_SCR_SLEEPDEEP_Pos

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

§ SCB_SCR_SLEEPDEEP_Msk

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

§ SCB_SCR_SLEEPONEXIT_Pos

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

§ SCB_SCR_SLEEPONEXIT_Msk

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

§ SCB_CCR_STKALIGN_Pos

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

§ SCB_CCR_STKALIGN_Msk

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

§ SCB_CCR_UNALIGN_TRP_Pos

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

§ SCB_CCR_UNALIGN_TRP_Msk

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

§ SCB_SHCSR_SVCALLPENDED_Pos

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

§ SCB_SHCSR_SVCALLPENDED_Msk

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask