dma.h
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32 #ifndef __DMA_H__
33 #define __DMA_H__
34 
35 //*****************************************************************************
36 //
39 //
40 //*****************************************************************************
41 
42 //*****************************************************************************
43 //
44 // If building with a C++ compiler, make all of the definitions in this header
45 // have a C binding.
46 //
47 //*****************************************************************************
48 #ifdef __cplusplus
49 extern "C"
50 {
51 #endif
52 
53 #include <stdbool.h>
54 #include <ti/devices/msp432p4xx/inc/msp.h>
55 #include <ti/devices/msp432p4xx/driverlib/interrupt.h>
56 
57 //*****************************************************************************
58 //
59 // A structure that defines an entry in the channel control table. These
60 // fields are used by the DMA controller and normally it is not necessary for
61 // software to directly read or write fields in the table.
62 //
63 //*****************************************************************************
64 typedef struct _DMA_ControlTable
65 {
66  //
67  // The ending source address of the data transfer.
68  //
69  volatile void *srcEndAddr;
70 
71  //
72  // The ending destination address of the data transfer.
73  //
74  volatile void *dstEndAddr;
75 
76  //
77  // The channel control mode.
78  //
79  volatile uint32_t control;
80 
81  //
82  // An unused location.
83  //
84  volatile uint32_t spare;
86 
87 //*****************************************************************************
88 //
154 //
155 //*****************************************************************************
156 #define DMA_TaskStructEntry(transferCount, \
157  itemSize, \
158  srcIncrement, \
159  srcAddr, \
160  dstIncrement, \
161  dstAddr, \
162  arbSize, \
163  mode) \
164  { \
165  (((srcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(srcAddr) : \
166  ((void *)(&((uint8_t *)(srcAddr))[((transferCount - 1) << \
167  ((srcIncrement) >> 26))]))), \
168  (((dstIncrement) == UDMA_DST_INC_NONE) ? (void *)(dstAddr) : \
169  ((void *)(&((uint8_t *)(dstAddr))[((transferCount - 1) << \
170  ((dstIncrement) >> 30))]))), \
171  (srcIncrement) | (dstIncrement) | (itemSize) | (arbSize) | \
172  (((transferCount) - 1) << 4) | \
173  ((((mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
174  ((mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
175  (mode) | UDMA_MODE_ALT_SELECT : (mode)), 0 \
176  }
177 
178 //*****************************************************************************
179 //
180 // Flags that can be passed to DMA_enableChannelAttribute(),
181 // DMA_disableChannelAttribute(), and returned from DMA_getChannelAttribute().
182 //
183 //*****************************************************************************
184 #define UDMA_ATTR_USEBURST 0x00000001
185 #define UDMA_ATTR_ALTSELECT 0x00000002
186 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004
187 #define UDMA_ATTR_REQMASK 0x00000008
188 #define UDMA_ATTR_ALL 0x0000000F
189 
190 //*****************************************************************************
191 //
192 // DMA control modes that can be passed to DMAModeSet() and returned
193 // DMAModeGet().
194 //
195 //*****************************************************************************
196 #define UDMA_MODE_STOP 0x00000000
197 #define UDMA_MODE_BASIC 0x00000001
198 #define UDMA_MODE_AUTO 0x00000002
199 #define UDMA_MODE_PINGPONG 0x00000003
200 #define UDMA_MODE_MEM_SCATTER_GATHER \
201  0x00000004
202 #define UDMA_MODE_PER_SCATTER_GATHER \
203  0x00000006
204 #define UDMA_MODE_ALT_SELECT 0x00000001
205 
206 //*****************************************************************************
207 //
208 // Channel configuration values that can be passed to DMAControlSet().
209 //
210 //*****************************************************************************
211 #define UDMA_DST_INC_8 0x00000000
212 #define UDMA_DST_INC_16 0x40000000
213 #define UDMA_DST_INC_32 0x80000000
214 #define UDMA_DST_INC_NONE 0xc0000000
215 #define UDMA_SRC_INC_8 0x00000000
216 #define UDMA_SRC_INC_16 0x04000000
217 #define UDMA_SRC_INC_32 0x08000000
218 #define UDMA_SRC_INC_NONE 0x0c000000
219 #define UDMA_SIZE_8 0x00000000
220 #define UDMA_SIZE_16 0x11000000
221 #define UDMA_SIZE_32 0x22000000
222 #define UDMA_DST_PROT_PRIV 0x00200000
223 #define UDMA_SRC_PROT_PRIV 0x00040000
224 #define UDMA_ARB_1 0x00000000
225 #define UDMA_ARB_2 0x00004000
226 #define UDMA_ARB_4 0x00008000
227 #define UDMA_ARB_8 0x0000c000
228 #define UDMA_ARB_16 0x00010000
229 #define UDMA_ARB_32 0x00014000
230 #define UDMA_ARB_64 0x00018000
231 #define UDMA_ARB_128 0x0001c000
232 #define UDMA_ARB_256 0x00020000
233 #define UDMA_ARB_512 0x00024000
234 #define UDMA_ARB_1024 0x00028000
235 #define UDMA_NEXT_USEBURST 0x00000008
236 
237 //*****************************************************************************
238 //
239 // Flags to be OR'd with the channel ID to indicate if the primary or alternate
240 // control structure should be used.
241 //
242 //*****************************************************************************
243 #define UDMA_PRI_SELECT 0x00000000
244 #define UDMA_ALT_SELECT 0x00000008
245 
246 //*****************************************************************************
247 //
248 // Values that can be passed to DMA_assignChannel() to select peripheral
249 // mapping for each channel. The channels named RESERVED may be assigned
250 // to a peripheral in future parts.
251 //
252 //*****************************************************************************
253 //
254 // Channel 0
255 //
256 #define DMA_CH0_RESERVED0 0x00000000
257 #define DMA_CH0_EUSCIA0TX 0x01000000
258 #define DMA_CH0_EUSCIB0TX0 0x02000000
259 #define DMA_CH0_EUSCIB3TX1 0x03000000
260 #define DMA_CH0_EUSCIB2TX2 0x04000000
261 #define DMA_CH0_EUSCIB1TX3 0x05000000
262 #define DMA_CH0_TIMERA0CCR0 0x06000000
263 #define DMA_CH0_AESTRIGGER0 0x07000000
264 
265 //
266 // Channel 1
267 //
268 #define DMA_CH1_RESERVED0 0x00000001
269 #define DMA_CH1_EUSCIA0RX 0x01000001
270 #define DMA_CH1_EUSCIB0RX0 0x02000001
271 #define DMA_CH1_EUSCIB3RX1 0x03000001
272 #define DMA_CH1_EUSCIB2RX2 0x04000001
273 #define DMA_CH1_EUSCIB1RX3 0x05000001
274 #define DMA_CH1_TIMERA0CCR2 0x06000001
275 #define DMA_CH1_AESTRIGGER1 0x07000001
276 
277 //
278 // Channel 2
279 //
280 #define DMA_CH2_RESERVED0 0x00000002
281 #define DMA_CH2_EUSCIA1TX 0x01000002
282 #define DMA_CH2_EUSCIB1TX0 0x02000002
283 #define DMA_CH2_EUSCIB0TX1 0x03000002
284 #define DMA_CH2_EUSCIB3TX2 0x04000002
285 #define DMA_CH2_EUSCIB2TX3 0x05000002
286 #define DMA_CH2_TIMERA1CCR0 0x06000002
287 #define DMA_CH2_AESTRIGGER2 0x07000002
288 
289 //
290 // Channel 3
291 //
292 #define DMA_CH3_RESERVED0 0x00000003
293 #define DMA_CH3_EUSCIA1RX 0x01000003
294 #define DMA_CH3_EUSCIB1RX0 0x02000003
295 #define DMA_CH3_EUSCIB0RX1 0x03000003
296 #define DMA_CH3_EUSCIB3RX2 0x04000003
297 #define DMA_CH3_EUSCIB2RX3 0x05000003
298 #define DMA_CH3_TIMERA1CCR2 0x06000003
299 #define DMA_CH3_RESERVED1 0x07000003
300 
301 //
302 // Channel 4
303 //
304 #define DMA_CH4_RESERVED0 0x00000004
305 #define DMA_CH4_EUSCIA2TX 0x01000004
306 #define DMA_CH4_EUSCIB2TX0 0x02000004
307 #define DMA_CH4_EUSCIB1TX1 0x03000004
308 #define DMA_CH4_EUSCIB0TX2 0x04000004
309 #define DMA_CH4_EUSCIB3TX3 0x05000004
310 #define DMA_CH4_TIMERA2CCR0 0x06000004
311 #define DMA_CH4_RESERVED1 0x07000004
312 
313 //
314 // Channel 5
315 //
316 #define DMA_CH5_RESERVED0 0x00000005
317 #define DMA_CH5_EUSCIA2RX 0x01000005
318 #define DMA_CH5_EUSCIB2RX0 0x02000005
319 #define DMA_CH5_EUSCIB1RX1 0x03000005
320 #define DMA_CH5_EUSCIB0RX2 0x04000005
321 #define DMA_CH5_EUSCIB3RX3 0x05000005
322 #define DMA_CH5_TIMERA2CCR2 0x06000005
323 #define DMA_CH5_RESERVED1 0x07000005
324 
325 //
326 // Channel 6
327 //
328 #define DMA_CH6_RESERVED0 0x00000006
329 #define DMA_CH6_EUSCIA3TX 0x01000006
330 #define DMA_CH6_EUSCIB3TX0 0x02000006
331 #define DMA_CH6_EUSCIB2TX1 0x03000006
332 #define DMA_CH6_EUSCIB1TX2 0x04000006
333 #define DMA_CH6_EUSCIB0TX3 0x05000006
334 #define DMA_CH6_TIMERA3CCR0 0x06000006
335 #define DMA_CH6_EXTERNALPIN 0x07000006
336 
337 //
338 // Channel 7
339 //
340 #define DMA_CH7_RESERVED0 0x00000007
341 #define DMA_CH7_EUSCIA3RX 0x01000007
342 #define DMA_CH7_EUSCIB3RX0 0x02000007
343 #define DMA_CH7_EUSCIB2RX1 0x03000007
344 #define DMA_CH7_EUSCIB1RX2 0x04000007
345 #define DMA_CH7_EUSCIB0RX3 0x05000007
346 #define DMA_CH7_TIMERA3CCR2 0x06000007
347 #define DMA_CH7_ADC14 0x07000007
348 
349 //
350 // Different interrupt handlers to pass into DMA_registerInterrupt and
351 // DMA_unregisterInterrupt and other Int functions
352 //
353 #define DMA_INT0 INT_DMA_INT0
354 #define DMA_INT1 INT_DMA_INT1
355 #define DMA_INT2 INT_DMA_INT2
356 #define DMA_INT3 INT_DMA_INT3
357 #define DMA_INTERR INT_DMA_ERR
358 
359 #define DMA_CHANNEL_0 0
360 #define DMA_CHANNEL_1 1
361 #define DMA_CHANNEL_2 2
362 #define DMA_CHANNEL_3 3
363 #define DMA_CHANNEL_4 4
364 #define DMA_CHANNEL_5 5
365 #define DMA_CHANNEL_6 6
366 #define DMA_CHANNEL_7 7
367 
368 //*****************************************************************************
369 //
370 // API Function prototypes
371 //
372 //*****************************************************************************
373 
374 //*****************************************************************************
375 //
382 //
383 //*****************************************************************************
384 extern void DMA_enableModule(void);
385 
386 //*****************************************************************************
387 //
394 //
395 //*****************************************************************************
396 extern void DMA_disableModule(void);
397 
398 //*****************************************************************************
399 //
407 //
408 //*****************************************************************************
409 extern uint32_t DMA_getErrorStatus(void);
410 
411 //*****************************************************************************
412 //
420 //
421 //*****************************************************************************
422 extern void DMA_clearErrorStatus(void);
423 
424 //*****************************************************************************
425 //
435 //
436 //*****************************************************************************
437 extern void DMA_enableChannel(uint32_t channelNum);
438 
439 //*****************************************************************************
440 //
450 //
451 //*****************************************************************************
452 extern void DMA_disableChannel(uint32_t channelNum);
453 
454 //*****************************************************************************
455 //
465 //
466 //*****************************************************************************
467 extern bool DMA_isChannelEnabled(uint32_t channelNum);
468 
469 //*****************************************************************************
470 //
487 //
488 //*****************************************************************************
489 extern void DMA_setControlBase(void *controlTable);
490 
491 //*****************************************************************************
492 //
500 //
501 //*****************************************************************************
502 extern void* DMA_getControlBase(void);
503 
504 //*****************************************************************************
505 //
513 //
514 //*****************************************************************************
515 extern void* DMA_getControlAlternateBase(void);
516 
517 //*****************************************************************************
518 //
530 //
531 //*****************************************************************************
532 extern void DMA_requestChannel(uint32_t channelNum);
533 
534 //*****************************************************************************
535 //
554 //
555 //*****************************************************************************
556 extern void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr);
557 
558 //*****************************************************************************
559 //
578 //
579 //*****************************************************************************
580 extern void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr);
581 
582 //*****************************************************************************
583 //
600 //
601 //*****************************************************************************
602 extern uint32_t DMA_getChannelAttribute(uint32_t channelNum);
603 
604 //*****************************************************************************
605 //
650 //
651 //*****************************************************************************
652 extern void DMA_setChannelControl(uint32_t channelStructIndex,
653  uint32_t control);
654 
655 //*****************************************************************************
656 //
722 //
723 //*****************************************************************************
724 extern void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
725  void *srcAddr, void *dstAddr, uint32_t transferSize);
726 
727 //*****************************************************************************
728 //
749 //
750 //*****************************************************************************
751 extern void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
752  void *taskList, uint32_t isPeriphSG);
753 
754 //*****************************************************************************
755 //
768 //
769 //*****************************************************************************
770 extern uint32_t DMA_getChannelSize(uint32_t channelStructIndex);
771 
772 //*****************************************************************************
773 //
787 //
788 //*****************************************************************************
789 extern uint32_t DMA_getChannelMode(uint32_t channelStructIndex);
790 
791 //*****************************************************************************
792 //
810 //
811 //*****************************************************************************
812 extern void DMA_assignChannel(uint32_t mapping);
813 
814 //*****************************************************************************
815 //
825 //
826 //*****************************************************************************
827 extern void DMA_requestSoftwareTransfer(uint32_t channel);
828 
829 //*****************************************************************************
830 //
850 //
851 //*****************************************************************************
852 extern void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel);
853 
854 //*****************************************************************************
855 //
869 //
870 //*****************************************************************************
871 extern void DMA_enableInterrupt(uint32_t interruptNumber);
872 
873 //*****************************************************************************
874 //
889 //
890 //*****************************************************************************
891 extern void DMA_disableInterrupt(uint32_t interruptNumber);
892 
893 //*****************************************************************************
894 //
911 //
912 //*****************************************************************************
913 extern uint32_t DMA_getInterruptStatus(void);
914 
915 //*****************************************************************************
916 //
928 //
929 //*****************************************************************************
930 extern void DMA_clearInterruptFlag(uint32_t channel);
931 
932 //*****************************************************************************
933 //
954 //
955 //*****************************************************************************
956 extern void DMA_registerInterrupt(uint32_t interruptNumber,
957  void (*intHandler)(void));
958 
959 //*****************************************************************************
960 //
978 //
979 //*****************************************************************************
980 extern void DMA_unregisterInterrupt(uint32_t interruptNumber);
981 
982 //*****************************************************************************
983 //
984 // Mark the end of the C bindings section for C++ compilers.
985 //
986 //*****************************************************************************
987 #ifdef __cplusplus
988 }
989 #endif
990 
991 //*****************************************************************************
992 //
993 // Close the Doxygen group.
995 //
996 //*****************************************************************************
997 
998 #endif // __UDMA_H__
uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
Definition: dma.c:548
struct _DMA_ControlTable DMA_ControlTable
Definition: dma.h:64
void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
Definition: dma.c:218
volatile uint32_t spare
Definition: dma.h:84
void DMA_registerInterrupt(uint32_t interruptNumber, void(*intHandler)(void))
Definition: dma.c:813
void DMA_enableModule(void)
Definition: dma.c:38
void DMA_clearInterruptFlag(uint32_t channel)
Definition: dma.c:769
void DMA_assignChannel(uint32_t mapping)
Definition: dma.c:645
uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
Definition: dma.c:600
void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
Definition: dma.c:325
void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
Definition: dma.c:735
void DMA_setControlBase(void *controlTable)
Definition: dma.c:120
uint32_t DMA_getInterruptStatus(void)
Definition: dma.c:764
volatile uint32_t control
Definition: dma.h:79
volatile void * dstEndAddr
Definition: dma.h:74
void DMA_requestChannel(uint32_t channelNum)
Definition: dma.c:152
volatile void * srcEndAddr
Definition: dma.h:69
uint32_t DMA_getChannelAttribute(uint32_t channelNum)
Definition: dma.c:271
void * DMA_getControlBase(void)
Definition: dma.c:134
void DMA_enableChannel(uint32_t channelNum)
Definition: dma.c:80
bool DMA_isChannelEnabled(uint32_t channelNum)
Definition: dma.c:106
void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount, void *taskList, uint32_t isPeriphSG)
Definition: dma.c:479
void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
Definition: dma.c:165
void DMA_disableChannel(uint32_t channelNum)
Definition: dma.c:93
void DMA_requestSoftwareTransfer(uint32_t channel)
Definition: dma.c:759
void DMA_disableInterrupt(uint32_t interruptNumber)
Definition: dma.c:794
void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode, void *srcAddr, void *dstAddr, uint32_t transferSize)
Definition: dma.c:357
uint32_t DMA_getErrorStatus(void)
Definition: dma.c:64
void DMA_unregisterInterrupt(uint32_t interruptNumber)
Definition: dma.c:837
void DMA_enableInterrupt(uint32_t interruptNumber)
Definition: dma.c:774
void * DMA_getControlAlternateBase(void)
Definition: dma.c:143
void DMA_clearErrorStatus(void)
Definition: dma.c:72
void DMA_disableModule(void)
Definition: dma.c:46

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