Configures and controls MSP432's DMA controller which is built around ARM's uDMA controller. More...

Data Structures
struct	_DMA_ControlTable

Macros
#define	DMA_TaskStructEntry(transferCount,itemSize,srcIncrement,srcAddr,dstIncrement,dstAddr,arbSize,mode)

#define	UDMA_ATTR_USEBURST 0x00000001

#define	UDMA_ATTR_ALTSELECT 0x00000002

#define	UDMA_ATTR_HIGH_PRIORITY 0x00000004

#define	UDMA_ATTR_REQMASK 0x00000008

#define	UDMA_ATTR_ALL 0x0000000F

#define	UDMA_MODE_STOP 0x00000000

#define	UDMA_MODE_BASIC 0x00000001

#define	UDMA_MODE_AUTO 0x00000002

#define	UDMA_MODE_PINGPONG 0x00000003

#define	UDMA_MODE_MEM_SCATTER_GATHER 0x00000004

#define	UDMA_MODE_PER_SCATTER_GATHER 0x00000006

#define	UDMA_MODE_ALT_SELECT 0x00000001

#define	UDMA_DST_INC_8 0x00000000

#define	UDMA_DST_INC_16 0x40000000

#define	UDMA_DST_INC_32 0x80000000

#define	UDMA_DST_INC_NONE 0xc0000000

#define	UDMA_SRC_INC_8 0x00000000

#define	UDMA_SRC_INC_16 0x04000000

#define	UDMA_SRC_INC_32 0x08000000

#define	UDMA_SRC_INC_NONE 0x0c000000

#define	UDMA_SIZE_8 0x00000000

#define	UDMA_SIZE_16 0x11000000

#define	UDMA_SIZE_32 0x22000000

#define	UDMA_DST_PROT_PRIV 0x00200000

#define	UDMA_SRC_PROT_PRIV 0x00040000

#define	UDMA_ARB_1 0x00000000

#define	UDMA_ARB_2 0x00004000

#define	UDMA_ARB_4 0x00008000

#define	UDMA_ARB_8 0x0000c000

#define	UDMA_ARB_16 0x00010000

#define	UDMA_ARB_32 0x00014000

#define	UDMA_ARB_64 0x00018000

#define	UDMA_ARB_128 0x0001c000

#define	UDMA_ARB_256 0x00020000

#define	UDMA_ARB_512 0x00024000

#define	UDMA_ARB_1024 0x00028000

#define	UDMA_NEXT_USEBURST 0x00000008

#define	UDMA_PRI_SELECT 0x00000000

#define	UDMA_ALT_SELECT 0x00000008

#define	DMA_CH0_RESERVED0 0x00000000

#define	DMA_CH0_EUSCIA0TX 0x01000000

#define	DMA_CH0_EUSCIB0TX0 0x02000000

#define	DMA_CH0_EUSCIB3TX1 0x03000000

#define	DMA_CH0_EUSCIB2TX2 0x04000000

#define	DMA_CH0_EUSCIB1TX3 0x05000000

#define	DMA_CH0_TIMERA0CCR0 0x06000000

#define	DMA_CH0_AESTRIGGER0 0x07000000

#define	DMA_CH1_RESERVED0 0x00000001

#define	DMA_CH1_EUSCIA0RX 0x01000001

#define	DMA_CH1_EUSCIB0RX0 0x02000001

#define	DMA_CH1_EUSCIB3RX1 0x03000001

#define	DMA_CH1_EUSCIB2RX2 0x04000001

#define	DMA_CH1_EUSCIB1RX3 0x05000001

#define	DMA_CH1_TIMERA0CCR2 0x06000001

#define	DMA_CH1_AESTRIGGER1 0x07000001

#define	DMA_CH2_RESERVED0 0x00000002

#define	DMA_CH2_EUSCIA1TX 0x01000002

#define	DMA_CH2_EUSCIB1TX0 0x02000002

#define	DMA_CH2_EUSCIB0TX1 0x03000002

#define	DMA_CH2_EUSCIB3TX2 0x04000002

#define	DMA_CH2_EUSCIB2TX3 0x05000002

#define	DMA_CH2_TIMERA1CCR0 0x06000002

#define	DMA_CH2_AESTRIGGER2 0x07000002

#define	DMA_CH3_RESERVED0 0x00000003

#define	DMA_CH3_EUSCIA1RX 0x01000003

#define	DMA_CH3_EUSCIB1RX0 0x02000003

#define	DMA_CH3_EUSCIB0RX1 0x03000003

#define	DMA_CH3_EUSCIB3RX2 0x04000003

#define	DMA_CH3_EUSCIB2RX3 0x05000003

#define	DMA_CH3_TIMERA1CCR2 0x06000003

#define	DMA_CH3_RESERVED1 0x07000003

#define	DMA_CH4_RESERVED0 0x00000004

#define	DMA_CH4_EUSCIA2TX 0x01000004

#define	DMA_CH4_EUSCIB2TX0 0x02000004

#define	DMA_CH4_EUSCIB1TX1 0x03000004

#define	DMA_CH4_EUSCIB0TX2 0x04000004

#define	DMA_CH4_EUSCIB3TX3 0x05000004

#define	DMA_CH4_TIMERA2CCR0 0x06000004

#define	DMA_CH4_RESERVED1 0x07000004

#define	DMA_CH5_RESERVED0 0x00000005

#define	DMA_CH5_EUSCIA2RX 0x01000005

#define	DMA_CH5_EUSCIB2RX0 0x02000005

#define	DMA_CH5_EUSCIB1RX1 0x03000005

#define	DMA_CH5_EUSCIB0RX2 0x04000005

#define	DMA_CH5_EUSCIB3RX3 0x05000005

#define	DMA_CH5_TIMERA2CCR2 0x06000005

#define	DMA_CH5_RESERVED1 0x07000005

#define	DMA_CH6_RESERVED0 0x00000006

#define	DMA_CH6_EUSCIA3TX 0x01000006

#define	DMA_CH6_EUSCIB3TX0 0x02000006

#define	DMA_CH6_EUSCIB2TX1 0x03000006

#define	DMA_CH6_EUSCIB1TX2 0x04000006

#define	DMA_CH6_EUSCIB0TX3 0x05000006

#define	DMA_CH6_TIMERA3CCR0 0x06000006

#define	DMA_CH6_EXTERNALPIN 0x07000006

#define	DMA_CH7_RESERVED0 0x00000007

#define	DMA_CH7_EUSCIA3RX 0x01000007

#define	DMA_CH7_EUSCIB3RX0 0x02000007

#define	DMA_CH7_EUSCIB2RX1 0x03000007

#define	DMA_CH7_EUSCIB1RX2 0x04000007

#define	DMA_CH7_EUSCIB0RX3 0x05000007

#define	DMA_CH7_TIMERA3CCR2 0x06000007

#define	DMA_CH7_ADC14 0x07000007

#define	DMA_INT0 INT_DMA_INT0

#define	DMA_INT1 INT_DMA_INT1

#define	DMA_INT2 INT_DMA_INT2

#define	DMA_INT3 INT_DMA_INT3

#define	DMA_INTERR INT_DMA_ERR

#define	DMA_CHANNEL_0 0

#define	DMA_CHANNEL_1 1

#define	DMA_CHANNEL_2 2

#define	DMA_CHANNEL_3 3

#define	DMA_CHANNEL_4 4

#define	DMA_CHANNEL_5 5

#define	DMA_CHANNEL_6 6

#define	DMA_CHANNEL_7 7

Typedefs
typedef struct _DMA_ControlTable	DMA_ControlTable

Functions
void	DMA_enableModule (void)

void	DMA_disableModule (void)

uint32_t	DMA_getErrorStatus (void)

void	DMA_clearErrorStatus (void)

void	DMA_enableChannel (uint32_t channelNum)

void	DMA_disableChannel (uint32_t channelNum)

bool	DMA_isChannelEnabled (uint32_t channelNum)

void	DMA_setControlBase (void *controlTable)

void *	DMA_getControlBase (void)

void *	DMA_getControlAlternateBase (void)

void	DMA_requestChannel (uint32_t channelNum)

void	DMA_enableChannelAttribute (uint32_t channelNum, uint32_t attr)

void	DMA_disableChannelAttribute (uint32_t channelNum, uint32_t attr)

uint32_t	DMA_getChannelAttribute (uint32_t channelNum)

void	DMA_setChannelControl (uint32_t channelStructIndex, uint32_t control)

void	DMA_setChannelTransfer (uint32_t channelStructIndex, uint32_t mode, void srcAddr, void dstAddr, uint32_t transferSize)

void	DMA_setChannelScatterGather (uint32_t channelNum, uint32_t taskCount, void *taskList, uint32_t isPeriphSG)

uint32_t	DMA_getChannelSize (uint32_t channelStructIndex)

uint32_t	DMA_getChannelMode (uint32_t channelStructIndex)

void	DMA_assignChannel (uint32_t mapping)

void	DMA_requestSoftwareTransfer (uint32_t channel)

void	DMA_assignInterrupt (uint32_t interruptNumber, uint32_t channel)

void	DMA_enableInterrupt (uint32_t interruptNumber)

void	DMA_disableInterrupt (uint32_t interruptNumber)

uint32_t	DMA_getInterruptStatus (void)

void	DMA_clearInterruptFlag (uint32_t channel)

void	DMA_registerInterrupt (uint32_t interruptNumber, void(*intHandler)(void))

void	DMA_unregisterInterrupt (uint32_t interruptNumber)

Detailed Description

Configures and controls MSP432's DMA controller which is built around ARM's uDMA controller.

Module Operation

The Micro Direct Memory Access (DMA) API provides functions to configure the MSP432 uDMA controller. The DMA controller is designed to work with the ARM Cortex-M processor and provides an efficient and low-overhead means of transferring blocks of data in the system.

The DMA controller has the following features:

dedicated channels for supported peripherals
one channel each for receive and transmit for devices with receive and transmit paths
dedicated channel for software initiated data transfers
channels can be independently configured and operated
an arbitration scheme that is configurable per channel
two levels of priority
subordinate to Cortex-M processor bus usage
data sizes of 8, 16, or 32 bits
address increment of byte, half-word, word, or none
maskable device requests
optional software initiated transfers on any channel
interrupt on transfer completion

The uDMA controller supports several different transfer modes, allowing for complex transfer schemes. The following transfer modes are provided:

Basic mode performs a simple transfer when a request is asserted by a device. This mode is appropriate to use with peripherals where the peripheral asserts the request signal whenever data should be transferred. The transfer pauses if the request is de-asserted, even if the transfer is not complete.
Auto-request mode performs a simple transfer that is started by a request, but always completes the entire transfer, even if the request is de-asserted. This mode is appropriate to use with software-initiated transfers.
Ping-Pong mode is used to transfer data to or from two buffers, switching from one buffer to the other as each buffer fills. This mode is appropriate to use with peripherals as a way to ensure a continuous flow of data to or from the peripheral. However, it is more complex to set up and requires code to manage the ping-pong buffers in the interrupt handler.
Memory scatter-gather mode is a complex mode that provides a way to set up a list of transfer ``tasks'' for the uDMA controller. Blocks of data can be transferred to and from arbitrary locations in memory.
Peripheral scatter-gather mode is similar to memory scatter-gather mode except that it is controlled by a peripheral request.

Detailed explanation of the various transfer modes is beyond the scope of this document. Please refer to the device data sheet for more information on the operation of the uDMA controller.

Programming Example

The DriverLib package contains a variety of different code examples that demonstrate the usage of the DMA module. These code examples are accessible under the examples/ folder of the SDK release as well as through TI Resource Explorer if using Code Composer Studio. These code examples provide a comprehensive list of use cases as well as practical applications involving each module.

Below is a very brief example of how to configure the DMA controller to transfer from a data array (data_array) to the EUSCI I2C module to be sent over the I2C line. This is useful in the sense that the EUSCI module does not constantly have to wake up the CPU in order to load the next byte into the buffer.

Macro Definition Documentation

#define DMA_TaskStructEntry	(	transferCount,
		itemSize,
		srcIncrement,
		srcAddr,
		dstIncrement,
		dstAddr,
		arbSize,
		mode
	)

Value:

{                                                                          \
        (((srcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(srcAddr) :           \
            ((void *)(&((uint8_t *)(srcAddr))[((transferCount - 1) <<          \
                                         ((srcIncrement) >> 26))]))),          \
            (((dstIncrement) == UDMA_DST_INC_NONE) ? (void *)(dstAddr) :       \
            ((void *)(&((uint8_t *)(dstAddr))[((transferCount - 1) <<          \
                                         ((dstIncrement) >> 30))]))),          \
        (srcIncrement) | (dstIncrement) | (itemSize) | (arbSize) |             \
        (((transferCount) - 1) << 4) |                                         \
        ((((mode) == UDMA_MODE_MEM_SCATTER_GATHER) ||                          \
          ((mode) == UDMA_MODE_PER_SCATTER_GATHER)) ?                          \
                (mode) | UDMA_MODE_ALT_SELECT : (mode)), 0                     \
    }

A helper macro for building scatter-gather task table entries.

This macro is intended to be used to help populate a table of DMA tasks for a scatter-gather transfer. This macro will calculate the values for the fields of a task structure entry based on the input parameters.

There are specific requirements for the values of each parameter. No checking is done so it is up to the caller to ensure that correct values are used for the parameters.

The transferCount parameter is the number of items that will be transferred by this task. It must be in the range 1-1024.

The itemSize parameter is the bit size of the transfer data. It must be one of UDMA_SIZE_8, UDMA_SIZE_16, or UDMA_SIZE_32.

The srcIncrement parameter is the increment size for the source data. It must be one of UDMA_SRC_INC_8, UDMA_SRC_INC_16, UDMA_SRC_INC_32, or UDMA_SRC_INC_NONE.

The srcAddr parameter is a void pointer to the beginning of the source data.

The dstIncrement parameter is the increment size for the destination data. It must be one of UDMA_DST_INC_8, UDMA_DST_INC_16, UDMA_DST_INC_32, or UDMA_DST_INC_NONE.

The dstAddr parameter is a void pointer to the beginning of the location where the data will be transferred.

The arbSize parameter is the arbitration size for the transfer, and must be one of UDMA_ARB_1, UDMA_ARB_2, UDMA_ARB_4, and so on up to UDMA_ARB_1024. This is used to select the arbitration size in powers of 2, from 1 to 1024.

The mode parameter is the mode to use for this transfer task. It must be one of UDMA_MODE_BASIC, UDMA_MODE_AUTO, UDMA_MODE_MEM_SCATTER_GATHER, or UDMA_MODE_PER_SCATTER_GATHER. Note that normally all tasks will be one of the scatter-gather modes while the last task is a task list will be AUTO or BASIC.

This macro is intended to be used to initialize individual entries of a structure of DMA_ControlTable type, like this:

DMA_ControlTable MyTaskList[] =
{
    DMA_TaskStructEntry(Task1Count, UDMA_SIZE_8,
                        UDMA_SRC_INC_8, MySourceBuf,
                        UDMA_DST_INC_8, MyDestBuf,
                        UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
    DMA_TaskStructEntry(Task2Count, ... ),
}

Parameters

transferCount	is the count of items to transfer for this task.
itemSize	is the bit size of the items to transfer for this task.
srcIncrement	is the bit size increment for source data.
srcAddr	is the starting address of the data to transfer.
dstIncrement	is the bit size increment for destination data.
dstAddr	is the starting address of the destination data.
arbSize	is the arbitration size to use for the transfer task.
mode	is the transfer mode for this task.

Returns: Nothing; this is not a function.

#define UDMA_ATTR_USEBURST 0x00000001

Referenced by DMA_disableChannelAttribute(), DMA_enableChannelAttribute(), and DMA_getChannelAttribute().

#define UDMA_ATTR_ALTSELECT 0x00000002

Referenced by DMA_disableChannelAttribute(), DMA_enableChannelAttribute(), and DMA_getChannelAttribute().

#define UDMA_ATTR_HIGH_PRIORITY 0x00000004

Referenced by DMA_disableChannelAttribute(), DMA_enableChannelAttribute(), and DMA_getChannelAttribute().

#define UDMA_ATTR_REQMASK 0x00000008

Referenced by DMA_disableChannelAttribute(), DMA_enableChannelAttribute(), and DMA_getChannelAttribute().

#define UDMA_ATTR_ALL 0x0000000F

#define UDMA_MODE_STOP 0x00000000

#define UDMA_MODE_BASIC 0x00000001

#define UDMA_MODE_AUTO 0x00000002

#define UDMA_MODE_PINGPONG 0x00000003

#define UDMA_MODE_MEM_SCATTER_GATHER 0x00000004

Referenced by DMA_getChannelMode(), and DMA_setChannelTransfer().

#define UDMA_MODE_PER_SCATTER_GATHER 0x00000006

Referenced by DMA_getChannelMode(), and DMA_setChannelTransfer().

#define UDMA_MODE_ALT_SELECT 0x00000001

Referenced by DMA_getChannelMode(), and DMA_setChannelTransfer().

#define UDMA_DST_INC_8 0x00000000

#define UDMA_DST_INC_16 0x40000000

#define UDMA_DST_INC_32 0x80000000

#define UDMA_DST_INC_NONE 0xc0000000

Referenced by DMA_setChannelTransfer().

#define UDMA_SRC_INC_8 0x00000000

#define UDMA_SRC_INC_16 0x04000000

#define UDMA_SRC_INC_32 0x08000000

#define UDMA_SRC_INC_NONE 0x0c000000

Referenced by DMA_setChannelTransfer().

#define UDMA_SIZE_8 0x00000000

#define UDMA_SIZE_16 0x11000000

#define UDMA_SIZE_32 0x22000000

#define UDMA_DST_PROT_PRIV 0x00200000

#define UDMA_SRC_PROT_PRIV 0x00040000

#define UDMA_ARB_1 0x00000000

#define UDMA_ARB_2 0x00004000

#define UDMA_ARB_4 0x00008000

#define UDMA_ARB_8 0x0000c000

#define UDMA_ARB_16 0x00010000

#define UDMA_ARB_32 0x00014000

#define UDMA_ARB_64 0x00018000

#define UDMA_ARB_128 0x0001c000

#define UDMA_ARB_256 0x00020000

#define UDMA_ARB_512 0x00024000

#define UDMA_ARB_1024 0x00028000

#define UDMA_NEXT_USEBURST 0x00000008

#define UDMA_PRI_SELECT 0x00000000

#define UDMA_ALT_SELECT 0x00000008

Referenced by DMA_setChannelScatterGather(), and DMA_setChannelTransfer().

#define DMA_CH0_RESERVED0 0x00000000

Referenced by DMA_assignChannel().

#define DMA_CH0_EUSCIA0TX 0x01000000

Referenced by DMA_assignChannel().

#define DMA_CH0_EUSCIB0TX0 0x02000000

Referenced by DMA_assignChannel().

#define DMA_CH0_EUSCIB3TX1 0x03000000

Referenced by DMA_assignChannel().

#define DMA_CH0_EUSCIB2TX2 0x04000000

Referenced by DMA_assignChannel().

#define DMA_CH0_EUSCIB1TX3 0x05000000

Referenced by DMA_assignChannel().

#define DMA_CH0_TIMERA0CCR0 0x06000000

Referenced by DMA_assignChannel().

#define DMA_CH0_AESTRIGGER0 0x07000000

Referenced by DMA_assignChannel().

#define DMA_CH1_RESERVED0 0x00000001

Referenced by DMA_assignChannel().

#define DMA_CH1_EUSCIA0RX 0x01000001

Referenced by DMA_assignChannel().

#define DMA_CH1_EUSCIB0RX0 0x02000001

Referenced by DMA_assignChannel().

#define DMA_CH1_EUSCIB3RX1 0x03000001

Referenced by DMA_assignChannel().

#define DMA_CH1_EUSCIB2RX2 0x04000001

Referenced by DMA_assignChannel().

#define DMA_CH1_EUSCIB1RX3 0x05000001

Referenced by DMA_assignChannel().

#define DMA_CH1_TIMERA0CCR2 0x06000001

Referenced by DMA_assignChannel().

#define DMA_CH1_AESTRIGGER1 0x07000001

Referenced by DMA_assignChannel().

#define DMA_CH2_RESERVED0 0x00000002

Referenced by DMA_assignChannel().

#define DMA_CH2_EUSCIA1TX 0x01000002

Referenced by DMA_assignChannel().

#define DMA_CH2_EUSCIB1TX0 0x02000002

Referenced by DMA_assignChannel().

#define DMA_CH2_EUSCIB0TX1 0x03000002

Referenced by DMA_assignChannel().

#define DMA_CH2_EUSCIB3TX2 0x04000002

Referenced by DMA_assignChannel().

#define DMA_CH2_EUSCIB2TX3 0x05000002

Referenced by DMA_assignChannel().

#define DMA_CH2_TIMERA1CCR0 0x06000002

Referenced by DMA_assignChannel().

#define DMA_CH2_AESTRIGGER2 0x07000002

Referenced by DMA_assignChannel().

#define DMA_CH3_RESERVED0 0x00000003

Referenced by DMA_assignChannel().

#define DMA_CH3_EUSCIA1RX 0x01000003

Referenced by DMA_assignChannel().

#define DMA_CH3_EUSCIB1RX0 0x02000003

Referenced by DMA_assignChannel().

#define DMA_CH3_EUSCIB0RX1 0x03000003

Referenced by DMA_assignChannel().

#define DMA_CH3_EUSCIB3RX2 0x04000003

Referenced by DMA_assignChannel().

#define DMA_CH3_EUSCIB2RX3 0x05000003

Referenced by DMA_assignChannel().

#define DMA_CH3_TIMERA1CCR2 0x06000003

Referenced by DMA_assignChannel().

#define DMA_CH3_RESERVED1 0x07000003

Referenced by DMA_assignChannel().

#define DMA_CH4_RESERVED0 0x00000004

Referenced by DMA_assignChannel().

#define DMA_CH4_EUSCIA2TX 0x01000004

Referenced by DMA_assignChannel().

#define DMA_CH4_EUSCIB2TX0 0x02000004

Referenced by DMA_assignChannel().

#define DMA_CH4_EUSCIB1TX1 0x03000004

Referenced by DMA_assignChannel().

#define DMA_CH4_EUSCIB0TX2 0x04000004

Referenced by DMA_assignChannel().

#define DMA_CH4_EUSCIB3TX3 0x05000004

Referenced by DMA_assignChannel().

#define DMA_CH4_TIMERA2CCR0 0x06000004

Referenced by DMA_assignChannel().

#define DMA_CH4_RESERVED1 0x07000004

Referenced by DMA_assignChannel().

#define DMA_CH5_RESERVED0 0x00000005

Referenced by DMA_assignChannel().

#define DMA_CH5_EUSCIA2RX 0x01000005

Referenced by DMA_assignChannel().

#define DMA_CH5_EUSCIB2RX0 0x02000005

Referenced by DMA_assignChannel().

#define DMA_CH5_EUSCIB1RX1 0x03000005

Referenced by DMA_assignChannel().

#define DMA_CH5_EUSCIB0RX2 0x04000005

Referenced by DMA_assignChannel().

#define DMA_CH5_EUSCIB3RX3 0x05000005

Referenced by DMA_assignChannel().

#define DMA_CH5_TIMERA2CCR2 0x06000005

Referenced by DMA_assignChannel().

#define DMA_CH5_RESERVED1 0x07000005

Referenced by DMA_assignChannel().

#define DMA_CH6_RESERVED0 0x00000006

Referenced by DMA_assignChannel().

#define DMA_CH6_EUSCIA3TX 0x01000006

Referenced by DMA_assignChannel().

#define DMA_CH6_EUSCIB3TX0 0x02000006

Referenced by DMA_assignChannel().

#define DMA_CH6_EUSCIB2TX1 0x03000006

Referenced by DMA_assignChannel().

#define DMA_CH6_EUSCIB1TX2 0x04000006

Referenced by DMA_assignChannel().

#define DMA_CH6_EUSCIB0TX3 0x05000006

Referenced by DMA_assignChannel().

#define DMA_CH6_TIMERA3CCR0 0x06000006

Referenced by DMA_assignChannel().

#define DMA_CH6_EXTERNALPIN 0x07000006

Referenced by DMA_assignChannel().

#define DMA_CH7_RESERVED0 0x00000007

Referenced by DMA_assignChannel().

#define DMA_CH7_EUSCIA3RX 0x01000007

Referenced by DMA_assignChannel().

#define DMA_CH7_EUSCIB3RX0 0x02000007

Referenced by DMA_assignChannel().

#define DMA_CH7_EUSCIB2RX1 0x03000007

Referenced by DMA_assignChannel().

#define DMA_CH7_EUSCIB1RX2 0x04000007

Referenced by DMA_assignChannel().

#define DMA_CH7_EUSCIB0RX3 0x05000007

Referenced by DMA_assignChannel().

#define DMA_CH7_TIMERA3CCR2 0x06000007

Referenced by DMA_assignChannel().

#define DMA_CH7_ADC14 0x07000007

Referenced by DMA_assignChannel().

#define DMA_INT0 INT_DMA_INT0

Referenced by DMA_registerInterrupt(), and DMA_unregisterInterrupt().

#define DMA_INT1 INT_DMA_INT1

Referenced by DMA_assignInterrupt(), DMA_disableInterrupt(), DMA_enableInterrupt(), DMA_registerInterrupt(), and DMA_unregisterInterrupt().

#define DMA_INT2 INT_DMA_INT2

Referenced by DMA_assignInterrupt(), DMA_disableInterrupt(), DMA_enableInterrupt(), DMA_registerInterrupt(), and DMA_unregisterInterrupt().

#define DMA_INT3 INT_DMA_INT3

Referenced by DMA_assignInterrupt(), DMA_disableInterrupt(), DMA_enableInterrupt(), DMA_registerInterrupt(), and DMA_unregisterInterrupt().

#define DMA_INTERR INT_DMA_ERR

Referenced by DMA_registerInterrupt(), and DMA_unregisterInterrupt().

#define DMA_CHANNEL_0 0

#define DMA_CHANNEL_1 1

#define DMA_CHANNEL_2 2

#define DMA_CHANNEL_3 3

#define DMA_CHANNEL_4 4

#define DMA_CHANNEL_5 5

#define DMA_CHANNEL_6 6

#define DMA_CHANNEL_7 7

Typedef Documentation

typedef struct _DMA_ControlTable DMA_ControlTable

Function Documentation

void DMA_enableModule ( void )

Enables the DMA controller for use.

This function enables the DMA controller. The DMA controller must be enabled before it can be configured and used.

Returns: None.

void DMA_disableModule ( void )

Disables the DMA controller for use.

This function disables the DMA controller. Once disabled, the DMA controller cannot operate until re-enabled with DMA_enableModule().

Returns: None.

uint32_t DMA_getErrorStatus ( void )

Gets the DMA error status.

This function returns the DMA error status. It should be called from within the DMA error interrupt handler to determine if a DMA error occurred.

Returns: Returns non-zero if a DMA error is pending.

void DMA_clearErrorStatus ( void )

Clears the DMA error interrupt.

This function clears a pending DMA error interrupt. This function should be called from within the DMA error interrupt handler to clear the interrupt.

Returns: None.

void DMA_enableChannel ( uint32_t channelNum )

Enables a DMA channel for operation.

Parameters

channelNum is the channel number to enable.

When a DMA transfer is completed, the channel is automatically disabled by the DMA controller. Therefore, this function should be called prior to starting up any new transfer.

Returns: None.

References ASSERT.

void DMA_disableChannel ( uint32_t channelNum )

Disables a DMA channel for operation.

Parameters

channelNum is the channel number to disable.

This function disables a specific DMA channel. Once disabled, a channel cannot respond to DMA transfer requests until re-enabled via DMA_enableChannel().

Returns: None.

References ASSERT.

bool DMA_isChannelEnabled ( uint32_t channelNum )

Checks if a DMA channel is enabled for operation.

Parameters

channelNum is the channel number to check.

This function checks to see if a specific DMA channel is enabled. This function can be used to check the status of a transfer, as the channel is automatically disabled at the end of a transfer.

Returns: Returns true if the channel is enabled, false if disabled.

References ASSERT.

void DMA_setControlBase ( void * controlTable )

Sets the base address for the channel control table.

Parameters

controlTable is a pointer to the 1024-byte-aligned base address of the DMA channel control table.

This function configures the base address of the channel control table. This table resides in system memory and holds control information for each DMA channel. The table must be aligned on a 1024-byte boundary. The base address must be configured before any of the channel functions can be used.

The size of the channel control table depends on the number of DMA channels and the transfer modes that are used. Refer to the introductory text and the microcontroller datasheet for more information about the channel control table.

Returns: None.

References ASSERT.

void* DMA_getControlBase ( void )

Gets the base address for the channel control table.

This function gets the base address of the channel control table. This table resides in system memory and holds control information for each DMA channel.

Returns: Returns a pointer to the base address of the channel control table.

void* DMA_getControlAlternateBase ( void )

Gets the base address for the channel control table alternate structures.

This function gets the base address of the second half of the channel control table that holds the alternate control structures for each channel.

Returns: Returns a pointer to the base address of the second half of the channel control table.

void DMA_requestChannel ( uint32_t channelNum )

Requests a DMA channel to start a transfer.

Parameters

channelNum is the channel number on which to request a DMA transfer.

This function allows software to request a DMA channel to begin a transfer. This function could be used for performing a memory-to-memory transfer, or if for some reason a transfer needs to be initiated by software instead of the peripheral associated with that channel.

Returns: None.

References ASSERT.

void DMA_enableChannelAttribute	(	uint32_t	channelNum,
		uint32_t	attr
	)

Enables attributes of a DMA channel.

Parameters

channelNum	is the channel to configure.
attr	is a combination of attributes for the channel.

This function is used to enable attributes of a DMA channel.

The attr parameter is the logical OR of any of the following:

UDMA_ATTR_USEBURST is used to restrict transfers to use only burst mode.
UDMA_ATTR_ALTSELECT is used to select the alternate control structure for this channel (it is very unlikely that this flag should be used).
UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
UDMA_ATTR_REQMASK is used to mask the hardware request signal from the peripheral for this channel.

Returns: None.

References ASSERT, UDMA_ATTR_ALTSELECT, UDMA_ATTR_HIGH_PRIORITY, UDMA_ATTR_REQMASK, and UDMA_ATTR_USEBURST.

void DMA_disableChannelAttribute	(	uint32_t	channelNum,
		uint32_t	attr
	)

Disables attributes of a DMA channel.

Parameters

channelNum	is the channel to configure.
attr	is a combination of attributes for the channel.

This function is used to disable attributes of a DMA channel.

The attr parameter is the logical OR of any of the following:

UDMA_ATTR_USEBURST is used to restrict transfers to use only burst mode.
UDMA_ATTR_ALTSELECT is used to select the alternate control structure for this channel.
UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
UDMA_ATTR_REQMASK is used to mask the hardware request signal from the peripheral for this channel.

Returns: None.

References ASSERT, UDMA_ATTR_ALTSELECT, UDMA_ATTR_HIGH_PRIORITY, UDMA_ATTR_REQMASK, and UDMA_ATTR_USEBURST.

uint32_t DMA_getChannelAttribute ( uint32_t channelNum )

Gets the enabled attributes of a DMA channel.

Parameters

channelNum is the channel to configure.

This function returns a combination of flags representing the attributes of the DMA channel.

Returns

Returns the logical OR of the attributes of the DMA channel, which can be any of the following:

UDMA_ATTR_USEBURST is used to restrict transfers to use only burst mode.
UDMA_ATTR_ALTSELECT is used to select the alternate control structure for this channel.
UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
UDMA_ATTR_REQMASK is used to mask the hardware request signal from the peripheral for this channel.

References ASSERT, UDMA_ATTR_ALTSELECT, UDMA_ATTR_HIGH_PRIORITY, UDMA_ATTR_REQMASK, and UDMA_ATTR_USEBURST.

void DMA_setChannelControl	(	uint32_t	channelStructIndex,
		uint32_t	control
	)

Sets the control parameters for a DMA channel control structure.

Parameters

channelStructIndex	is the logical OR of the DMA channel number with UDMA_PRI_SELECT or UDMA_ALT_SELECT.
control	is logical OR of several control values to set the control parameters for the channel.

This function is used to set control parameters for a DMA transfer. These parameters are typically not changed often.

The channelStructIndex parameter should be the logical OR of the channel number with one of UDMA_PRI_SELECT or UDMA_ALT_SELECT to choose whether the primary or alternate data structure is used.

The control parameter is the logical OR of five values: the data size, the source address increment, the destination address increment, the arbitration size, and the use burst flag. The choices available for each of these values is described below.

Choose the data size from one of UDMA_SIZE_8, UDMA_SIZE_16, or UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits.

Choose the source address increment from one of UDMA_SRC_INC_8, UDMA_SRC_INC_16, UDMA_SRC_INC_32, or UDMA_SRC_INC_NONE to select an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or to select non-incrementing.

Choose the destination address increment from one of UDMA_DST_INC_8, UDMA_DST_INC_16, UDMA_DST_INC_32, or UDMA_SRC_INC_8 to select an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or to select non-incrementing.

The arbitration size determines how many items are transferred before the DMA controller re-arbitrates for the bus. Choose the arbitration size from one of UDMA_ARB_1, UDMA_ARB_2, UDMA_ARB_4, UDMA_ARB_8, through UDMA_ARB_1024 to select the arbitration size from 1 to 1024 items, in powers of 2.

The value UDMA_NEXT_USEBURST is used to force the channel to only respond to burst requests at the tail end of a scatter-gather transfer.

Note: The address increment cannot be smaller than the data size.

Returns: None.

References ASSERT, and _DMA_ControlTable::control.

void DMA_setChannelTransfer	(	uint32_t	channelStructIndex,
		uint32_t	mode,
		void *	srcAddr,
		void *	dstAddr,
		uint32_t	transferSize
	)

Sets the transfer parameters for a DMA channel control structure.

Parameters

channelStructIndex	is the logical OR of the DMA channel number with either UDMA_PRI_SELECT or UDMA_ALT_SELECT.
mode	is the type of DMA transfer.
srcAddr	is the source address for the transfer.
dstAddr	is the destination address for the transfer.
transferSize	is the number of data items to transfer.

This function is used to configure the parameters for a DMA transfer. These parameters are typically changed often. The function DMA_setChannelControl() MUST be called at least once for this channel prior to calling this function.

The channelStructIndex parameter should be the logical OR of the channel number with one of UDMA_PRI_SELECT or UDMA_ALT_SELECT to choose whether the primary or alternate data structure is used.

The mode parameter should be one of the following values:

UDMA_MODE_STOP stops the DMA transfer. The controller sets the mode to this value at the end of a transfer.
UDMA_MODE_BASIC to perform a basic transfer based on request.
UDMA_MODE_AUTO to perform a transfer that always completes once started even if the request is removed.
UDMA_MODE_PINGPONG to set up a transfer that switches between the primary and alternate control structures for the channel. This mode allows use of ping-pong buffering for DMA transfers.
UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather transfer.
UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather transfer.

The srcAddr and dstAddr parameters are pointers to the first location of the data to be transferred. These addresses should be aligned according to the item size. The compiler takes care of this alignment if the pointers are pointing to storage of the appropriate data type.

The transferSize parameter is the number of data items, not the number of bytes.

The two scatter-gather modes, memory and peripheral, are actually different depending on whether the primary or alternate control structure is selected. This function looks for the UDMA_PRI_SELECT and UDMA_ALT_SELECT flag along with the channel number and sets the scatter-gather mode as appropriate for the primary or alternate control structure.

The channel must also be enabled using DMA_enableChannel() after calling this function. The transfer does not begin until the channel has been configured and enabled. Note that the channel is automatically disabled after the transfer is completed, meaning that DMA_enableChannel() must be called again after setting up the next transfer.

Note: Great care must be taken to not modify a channel control structure that is in use or else the results are unpredictable, including the possibility of undesired data transfers to or from memory or peripherals. For BASIC and AUTO modes, it is safe to make changes when the channel is disabled, or the DMA_getChannelMode() returns UDMA_MODE_STOP. For PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the primary or alternate control structure only when the other is being used. The DMA_getChannelMode() function returns UDMA_MODE_STOP when a channel control structure is inactive and safe to modify.

Returns: None.

References ASSERT, _DMA_ControlTable::control, _DMA_ControlTable::dstEndAddr, _DMA_ControlTable::srcEndAddr, UDMA_ALT_SELECT, UDMA_DST_INC_NONE, UDMA_MODE_ALT_SELECT, UDMA_MODE_MEM_SCATTER_GATHER, UDMA_MODE_PER_SCATTER_GATHER, and UDMA_SRC_INC_NONE.

void DMA_setChannelScatterGather	(	uint32_t	channelNum,
		uint32_t	taskCount,
		void *	taskList,
		uint32_t	isPeriphSG
	)

Configures a DMA channel for scatter-gather mode.

Parameters

channelNum	is the DMA channel number.
taskCount	is the number of scatter-gather tasks to execute.
taskList	is a pointer to the beginning of the scatter-gather task list.
isPeriphSG	is a flag to indicate it is a peripheral scatter-gather transfer (else it is memory scatter-gather transfer)

This function is used to configure a channel for scatter-gather mode. The caller must have already set up a task list and must pass a pointer to the start of the task list as the taskList parameter. The taskCount parameter is the count of tasks in the task list, not the size of the task list. The flag bIsPeriphSG should be used to indicate if scatter-gather should be configured for peripheral or memory operation.

See Also: DMA_TaskStructEntry

Returns: None.

References ASSERT, _DMA_ControlTable::control, _DMA_ControlTable::dstEndAddr, _DMA_ControlTable::spare, _DMA_ControlTable::srcEndAddr, and UDMA_ALT_SELECT.

uint32_t DMA_getChannelSize ( uint32_t channelStructIndex )

Gets the current transfer size for a DMA channel control structure.

Parameters

channelStructIndex is the logical OR of the DMA channel number with either UDMA_PRI_SELECT or UDMA_ALT_SELECT.

This function is used to get the DMA transfer size for a channel. The transfer size is the number of items to transfer, where the size of an item might be 8, 16, or 32 bits. If a partial transfer has already occurred, then the number of remaining items is returned. If the transfer is complete, then 0 is returned.

Returns: Returns the number of items remaining to transfer.

References ASSERT, and _DMA_ControlTable::control.

uint32_t DMA_getChannelMode ( uint32_t channelStructIndex )

Gets the transfer mode for a DMA channel control structure.

Parameters

channelStructIndex is the logical OR of the DMA channel number with either UDMA_PRI_SELECT or UDMA_ALT_SELECT.

This function is used to get the transfer mode for the DMA channel and to query the status of a transfer on a channel. When the transfer is complete the mode is UDMA_MODE_STOP.

Returns: Returns the transfer mode of the specified channel and control structure, which is one of the following values: UDMA_MODE_STOP, UDMA_MODE_BASIC, UDMA_MODE_AUTO, UDMA_MODE_PINGPONG, UDMA_MODE_MEM_SCATTER_GATHER, or UDMA_MODE_PER_SCATTER_GATHER.

References ASSERT, _DMA_ControlTable::control, UDMA_MODE_ALT_SELECT, UDMA_MODE_MEM_SCATTER_GATHER, and UDMA_MODE_PER_SCATTER_GATHER.

void DMA_assignChannel ( uint32_t mapping )

Assigns a peripheral mapping for a DMA channel.

Parameters

mapping is a macro specifying the peripheral assignment for a channel.

This function assigns a peripheral mapping to a DMA channel. It is used to select which peripheral is used for a DMA channel. The parameter mapping should be one of the macros named UDMA_CHn_tttt from the header file dma.h. For example, to assign DMA channel 0 to the eUSCI AO RX channel, the parameter should be the macro UDMA_CH1_EUSCIA0RX.

Please consult the data sheet for a table showing all the possible peripheral assignments for the DMA channels for a particular device.

Returns: None.

References ASSERT, DMA_CH0_AESTRIGGER0, DMA_CH0_EUSCIA0TX, DMA_CH0_EUSCIB0TX0, DMA_CH0_EUSCIB1TX3, DMA_CH0_EUSCIB2TX2, DMA_CH0_EUSCIB3TX1, DMA_CH0_RESERVED0, DMA_CH0_TIMERA0CCR0, DMA_CH1_AESTRIGGER1, DMA_CH1_EUSCIA0RX, DMA_CH1_EUSCIB0RX0, DMA_CH1_EUSCIB1RX3, DMA_CH1_EUSCIB2RX2, DMA_CH1_EUSCIB3RX1, DMA_CH1_RESERVED0, DMA_CH1_TIMERA0CCR2, DMA_CH2_AESTRIGGER2, DMA_CH2_EUSCIA1TX, DMA_CH2_EUSCIB0TX1, DMA_CH2_EUSCIB1TX0, DMA_CH2_EUSCIB2TX3, DMA_CH2_EUSCIB3TX2, DMA_CH2_RESERVED0, DMA_CH2_TIMERA1CCR0, DMA_CH3_EUSCIA1RX, DMA_CH3_EUSCIB0RX1, DMA_CH3_EUSCIB1RX0, DMA_CH3_EUSCIB2RX3, DMA_CH3_EUSCIB3RX2, DMA_CH3_RESERVED0, DMA_CH3_RESERVED1, DMA_CH3_TIMERA1CCR2, DMA_CH4_EUSCIA2TX, DMA_CH4_EUSCIB0TX2, DMA_CH4_EUSCIB1TX1, DMA_CH4_EUSCIB2TX0, DMA_CH4_EUSCIB3TX3, DMA_CH4_RESERVED0, DMA_CH4_RESERVED1, DMA_CH4_TIMERA2CCR0, DMA_CH5_EUSCIA2RX, DMA_CH5_EUSCIB0RX2, DMA_CH5_EUSCIB1RX1, DMA_CH5_EUSCIB2RX0, DMA_CH5_EUSCIB3RX3, DMA_CH5_RESERVED0, DMA_CH5_RESERVED1, DMA_CH5_TIMERA2CCR2, DMA_CH6_EUSCIA3TX, DMA_CH6_EUSCIB0TX3, DMA_CH6_EUSCIB1TX2, DMA_CH6_EUSCIB2TX1, DMA_CH6_EUSCIB3TX0, DMA_CH6_EXTERNALPIN, DMA_CH6_RESERVED0, DMA_CH6_TIMERA3CCR0, DMA_CH7_ADC14, DMA_CH7_EUSCIA3RX, DMA_CH7_EUSCIB0RX3, DMA_CH7_EUSCIB1RX2, DMA_CH7_EUSCIB2RX1, DMA_CH7_EUSCIB3RX0, DMA_CH7_RESERVED0, and DMA_CH7_TIMERA3CCR2.

void DMA_requestSoftwareTransfer ( uint32_t channel )

Initializes a software transfer of the corresponding DMA channel. This is done if the user wants to force a DMA on the specified channel without the hardware precondition. Specific channels can be configured using the DMA_assignChannel function.

Parameters

channel is the channel to trigger the interrupt

Returns: None

void DMA_assignInterrupt	(	uint32_t	interruptNumber,
		uint32_t	channel
	)

Assigns a specific DMA channel to the corresponding interrupt handler. For MSP432 devices, there are three configurable interrupts, and one master interrupt. This function will assign a specific DMA channel to the provided configurable DMA interrupt.

Note that once a channel is assigned to a configurable interrupt, it will be masked in hardware from the master DMA interrupt (interruptNumber zero). This function can also be used in conjunction with the DMAIntTrigger function to provide the feature to software trigger specific channel interrupts.

Parameters

interruptNumber	is the configurable interrupt to assign the given channel. Valid values are: DMA_INT1 the first configurable DMA interrupt handler DMA_INT2 the second configurable DMA interrupt handler DMA_INT3 the third configurable DMA interrupt handler
channel	is the channel to assign the interrupt

Returns: None.

References ASSERT, DMA_enableInterrupt(), DMA_INT1, DMA_INT2, and DMA_INT3.

void DMA_enableInterrupt ( uint32_t interruptNumber )

Enables the specified interrupt for the DMA controller. Note for interrupts one through three, specific channels have to be mapped to the interrupt using the DMA_assignInterrupt function.

Parameters

interruptNumber identifies which DMA interrupt is to be enabled. This interrupt should be one of the following:

DMA_INT1 the first configurable DMA interrupt handler
DMA_INT2 the second configurable DMA interrupt handler
DMA_INT3 the third configurable DMA interrupt handler

Returns: None.

References ASSERT, DMA_INT1, DMA_INT2, and DMA_INT3.

Referenced by DMA_assignInterrupt().

void DMA_disableInterrupt ( uint32_t interruptNumber )

Disables the specified interrupt for the DMA controller.

Parameters

interruptNumber identifies which DMA interrupt is to be disabled. This interrupt should be one of the following:

DMA_INT1 the first configurable DMA interrupt handler
DMA_INT2 the second configurable DMA interrupt handler
DMA_INT3 the third configurable DMA interrupt handler

Note for interrupts that are associated with a specific DMA channel (DMA_INT1 - DMA_INT3), this function will also enable that specific channel for interrupts.

Returns: None.

References ASSERT, DMA_INT1, DMA_INT2, and DMA_INT3.

uint32_t DMA_getInterruptStatus ( void )

Gets the DMA controller channel interrupt status for interrupt zero.

This function is used to get the interrupt status of the DMA controller. The returned value is a 32-bit bit mask that indicates which channels are requesting an interrupt. This function can be used from within an interrupt handler to determine or confirm which DMA channel has requested an interrupt.

Note that this will only apply to interrupt zero for the DMA controller as only one interrupt can be associated with interrupts one through three. If an interrupt is assigned to an interrupt other than interrupt zero, it will be masked by this function.

Returns: Returns a 32-bit mask which indicates requesting DMA channels. There is a bit for each channel and a 1 indicates that the channel is requesting an interrupt. Multiple bits can be set.

void DMA_clearInterruptFlag ( uint32_t channel )

Clears the DMA controller channel interrupt mask for interrupt zero.

Parameters

channel is the channel interrupt to clear.

This function is used to clear the interrupt status of the DMA controller. Note that only interrupts that weren't assigned to DMA interrupts one through three using the DMA_assignInterrupt function will be affected by this function. For other DMA interrupts, only one channel can be associated and therefore clearing is unnecessary.

Returns: None

void DMA_registerInterrupt	(	uint32_t	interruptNumber,
		void(*)(void)	intHandler
	)

Registers an interrupt handler for the DMA controller.

Parameters

interruptNumber	identifies which DMA interrupt is to be registered.
intHandler	is a pointer to the function to be called when the interrupt is called.

This function registers and enables the handler to be called when the DMA controller generates an interrupt. The interrupt parameter should be one of the following:

DMA_INT0 the master DMA interrupt handler
DMA_INT1 the first configurable DMA interrupt handler
DMA_INT2 the second configurable DMA interrupt handler
DMA_INT3 the third configurable DMA interrupt handler
DMA_INTERR the DMA error interrupt handler

See Also: Interrupt_registerInterrupt() for important information about registering interrupt handlers.

Returns: None.

References ASSERT, DMA_INT0, DMA_INT1, DMA_INT2, DMA_INT3, DMA_INTERR, Interrupt_enableInterrupt(), and Interrupt_registerInterrupt().

void DMA_unregisterInterrupt ( uint32_t interruptNumber )

Unregisters an interrupt handler for the DMA controller.

Parameters

interruptNumber identifies which DMA interrupt to unregister.

This function disables and unregisters the handler to be called for the specified DMA interrupt. The interrupt parameter should be one of the parameters as documented for the function DMA_registerInterrupt().

Note for interrupts that are associated with a specific DMA channel (DMA_INT1 - DMA_INT3), this function will also disable that specific channel for interrupts.

See Also: Interrupt_registerInterrupt() for important information about registering interrupt handlers.

Returns: None.

References ASSERT, DMA_INT0, DMA_INT1, DMA_INT2, DMA_INT3, DMA_INTERR, Interrupt_disableInterrupt(), and Interrupt_unregisterInterrupt().

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