Instance: AUX_AIODIO1
Component: AUX_AIODIO
Base address: 0x400C2000
AUX Analog/Digital Input Output Controller
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 2000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C 2004 |
|
RO |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C 2008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x400C 200C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 2010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 2014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 2018 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x400C 2000 | Instance | 0x400C 2000 |
Description | General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1 |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. |
RW | 0x00 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x400C 2004 | Instance | 0x400C 2004 |
Description | Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1 |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||||||||
15:14 | IO7 | Select mode for AUXIO[8i+7].
|
RW | 0b00 | |||||||||||||||||
13:12 | IO6 | Select mode for AUXIO[8i+6].
|
RW | 0b00 | |||||||||||||||||
11:10 | IO5 | Select mode for AUXIO[8i+5].
|
RW | 0b00 | |||||||||||||||||
9:8 | IO4 | Select mode for AUXIO[8i+4].
|
RW | 0b00 | |||||||||||||||||
7:6 | IO3 | Select mode for AUXIO[8i+3].
|
RW | 0b00 | |||||||||||||||||
5:4 | IO2 | Select mode for AUXIO[8i+2].
|
RW | 0b00 | |||||||||||||||||
3:2 | IO1 | Select mode for AUXIO[8i+1].
|
RW | 0b00 | |||||||||||||||||
1:0 | IO0 | Select mode for AUXIO[8i+0].
|
RW | 0b00 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x400C 2008 | Instance | 0x400C 2008 |
Description | General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and I = 1 for AUX_AIODIO1. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n value is old. | RO | 0x00 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x400C 200C | Instance | 0x400C 200C |
Description | General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0. |
RW | 0x00 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x400C 2010 | Instance | 0x400C 2010 |
Description | General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0. |
RW | 0x00 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x400C 2014 | Instance | 0x400C 2014 |
Description | General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0. |
RW | 0x00 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C 2018 | Instance | 0x400C 2018 |
Description | General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and I = 1 for AUX_AIODIO1. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage. |
RW | 0x00 |
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