Instance: AUX_TDC
Component: AUX_TDC
Base address: 0x400C4000
AUX Time To Digital Converter
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 4000 |
|
RO |
32 |
0x0000 0006 |
0x0000 0004 |
0x400C 4004 |
|
RO |
32 |
0x0000 0002 |
0x0000 0008 |
0x400C 4008 |
|
RW |
32 |
0x0000 000F |
0x0000 000C |
0x400C 400C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 4010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 4014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 4018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x400C 401C |
|
RW |
32 |
0x0000 001F |
0x0000 0020 |
0x400C 4020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x400C 4024 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x400C 4000 | Instance | 0x400C 4000 |
Description | Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
1:0 | CMD | TDC commands.
|
WO | 0b00 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x400C 4004 | Instance | 0x400C 4004 |
Description | Status | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||||||||||||||||||||||||||||||||||||||
7 | SAT | TDC measurement saturation flag. 0: Conversion has not saturated. 1: Conversion stopped due to saturation. This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD. |
RO | 0 | ||||||||||||||||||||||||||||||||||||||
6 | DONE | TDC measurement complete flag. 0: TDC measurement has not yet completed. 1: TDC measurement has completed. This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD. |
RO | 0 | ||||||||||||||||||||||||||||||||||||||
5:0 | STATE | TDC state machine status.
|
RO | 0b00 0110 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x400C 4008 | Instance | 0x400C 4008 |
Description | Result Result of last TDC conversion |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
24:0 | VALUE | TDC conversion result. The result of the TDC conversion is given in number of clock edges of the clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and falling edges are counted. If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it takes a non-zero time to stop the measurement. Hence, the maximum value of this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT to R24. |
RO | 0b0 0000 0000 0000 0000 0000 0010 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x400C 400C | Instance | 0x400C 400C |
Description | Saturation Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||||||||||||||||||||||||||||||||||||||||||||
3:0 | LIMIT | Saturation limit. The flag STAT.SAT is set when the TDC counter saturates. Values not enumerated are not supported
|
RW | 0xF |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x400C 4010 | Instance | 0x400C 4010 |
Description | Trigger Source Select source and polarity for TDC start and stop events. See the Technical Reference Manual for event timing requirements. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | |||||||||||
13 | STOP_POL | Polarity of stop source. Change only while STAT.STATE is IDLE.
|
RW | 0 | |||||||||||
12:8 | STOP_SRC | Select stop source from the asynchronous AUX event bus. Change only while STAT.STATE is IDLE. |
RW | 0b0 0000 | |||||||||||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
5 | START_POL | Polarity of start source. Change only while STAT.STATE is IDLE.
|
RW | 0 | |||||||||||
4:0 | START_SRC | Select start source from the asynchronous AUX event bus. Change only while STAT.STATE is IDLE. |
RW | 0b0 0000 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x400C 4014 | Instance | 0x400C 4014 |
Description | Trigger Counter Stop-counter control and status. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | CNT | Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. Read CNT to get the remaining number of stop events to ignore during a TDC measurement. Write CNT to update the remaining number of stop events to ignore during a TDC measurement. The TDC measurement ignores updates of CNT if there are no more stop events left to ignore. When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the start of the measurement. |
RW | 0x0000 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C 4018 | Instance | 0x400C 4018 |
Description | Trigger Counter Load Stop-counter load. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | CNT | Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. To measure frequency of an event source: - Set start event equal to stop event. - Set CNT to number of periods to measure. Both 0 and 1 values measures a single event source period. To measure pulse width of an event source: - Set start event source equal to stop event source. - Select different polarity for start and stop event. - Set CNT to 0. To measure time from the start event to the Nth stop event when N > 1: - Select different start and stop event source. - Set CNT to (N-1). See the Technical Reference Manual for event timing requirements. When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start of the measurement. |
RW | 0x0000 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x400C 401C | Instance | 0x400C 401C |
Description | Trigger Counter Configuration Stop-counter configuration. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | Enable stop-counter. 0: Disable stop-counter. 1: Enable stop-counter. Change only while STAT.STATE is IDLE. |
RW | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x400C 4020 | Instance | 0x400C 4020 |
Description | Prescaler Control The prescaler can be used to count events that are faster than the AUX clock frequency. It can be used to: - count pulses on a specified event from the asynchronous event bus. - prescale a specified event from the asynchronous event bus. To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to AUX_TDC_PRE. It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the AUX clock frequency. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
7 | RESET_N | Prescaler reset. 0: Reset prescaler. 1: Release reset of prescaler. AUX_TDC_PRE event becomes 0 when you reset the prescaler. |
RW | 0 | |||||||||||
6 | RATIO | Prescaler ratio. This controls how often the AUX_TDC_PRE event is generated by the prescaler.
|
RW | 0 | |||||||||||
5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
4:0 | SRC | Prescaler event source. Select an event from the asynchronous AUX event bus to connect to the prescaler input. Configure only while RESET_N is 0. |
RW | 0b1 1111 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x400C 4024 | Instance | 0x400C 4024 |
Description | Prescaler Counter | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | CNT | Prescaler counter value. Write a value to CNT to capture the value of the 16-bit prescaler counter into CNT. Read CNT to get the captured value. The read value gets 1 LSB uncertainty if the event source level rises when you release the reset. You must capture the prescaler counter value when the event source level is stable, either high or low: - Disable AUX I/O input buffer to clamp AUXIO event low. - Disable COMPA to clamp AUX_COMPA event low. The read value can in general get 1 LSB uncertainty when you gate the event source asynchronously. Please note the following: - The prescaler counter is reset to 2 by PRECTL.RESET_N. - The captured value is 2 when the number of rising edges on prescaler input is less than 3. Otherwise, captured value equals number of event pulses - 1. |
RW | 0x0000 |
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