CC26xx Driver Library
Functions
[i2c.h] Inter-Integrated Circuit
Peripherals

Functions

void I2CMasterInitExpClk (uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)
 Initializes the I2C Master block. More...
 
static void I2CMasterControl (uint32_t ui32Base, uint32_t ui32Cmd)
 Controls the state of the I2C Master module. More...
 
static void I2CMasterSlaveAddrSet (uint32_t ui32Base, uint8_t ui8SlaveAddr, bool bReceive)
 Sets the address that the I2C Master will place on the bus. More...
 
static void I2CMasterEnable (uint32_t ui32Base)
 Enables the I2C Master block. More...
 
static void I2CMasterDisable (uint32_t ui32Base)
 Disables the I2C master block. More...
 
static bool I2CMasterBusy (uint32_t ui32Base)
 Indicates whether or not the I2C Master is busy. More...
 
static bool I2CMasterBusBusy (uint32_t ui32Base)
 Indicates whether or not the I2C bus is busy. More...
 
static uint32_t I2CMasterDataGet (uint32_t ui32Base)
 Receives a byte that has been sent to the I2C Master. More...
 
static void I2CMasterDataPut (uint32_t ui32Base, uint8_t ui8Data)
 Transmits a byte from the I2C Master. More...
 
uint32_t I2CMasterErr (uint32_t ui32Base)
 Gets the error status of the I2C Master module. More...
 
static void I2CMasterIntEnable (uint32_t ui32Base)
 Enables the I2C Master interrupt. More...
 
static void I2CMasterIntDisable (uint32_t ui32Base)
 Disables the I2C Master interrupt. More...
 
static void I2CMasterIntClear (uint32_t ui32Base)
 Clears I2C Master interrupt sources. More...
 
static bool I2CMasterIntStatus (uint32_t ui32Base, bool bMasked)
 Gets the current I2C Master interrupt status. More...
 
static void I2CSlaveEnable (uint32_t ui32Base)
 Enables the I2C Slave block. More...
 
static void I2CSlaveInit (uint32_t ui32Base, uint8_t ui8SlaveAddr)
 Initializes the I2C Slave block. More...
 
static void I2CSlaveAddressSet (uint32_t ui32Base, uint8_t ui8SlaveAddr)
 Sets the I2C slave address. More...
 
static void I2CSlaveDisable (uint32_t ui32Base)
 Disables the I2C slave block. More...
 
static uint32_t I2CSlaveStatus (uint32_t ui32Base)
 Gets the I2C Slave module status. More...
 
static uint32_t I2CSlaveDataGet (uint32_t ui32Base)
 Receives a byte that has been sent to the I2C Slave. More...
 
static void I2CSlaveDataPut (uint32_t ui32Base, uint8_t ui8Data)
 Transmits a byte from the I2C Slave. More...
 
static void I2CSlaveIntEnable (uint32_t ui32Base, uint32_t ui32IntFlags)
 Enables individual I2C Slave interrupt sources. More...
 
static void I2CSlaveIntDisable (uint32_t ui32Base, uint32_t ui32IntFlags)
 Disables individual I2C Slave interrupt sources. More...
 
static void I2CSlaveIntClear (uint32_t ui32Base, uint32_t ui32IntFlags)
 Clears I2C Slave interrupt sources. More...
 
static uint32_t I2CSlaveIntStatus (uint32_t ui32Base, bool bMasked)
 Gets the current I2C Slave interrupt status. More...
 
void I2CIntRegister (uint32_t ui32Base, void(*pfnHandler)(void))
 Registers an interrupt handler for the I2C module in the dynamic interrupt table. More...
 
void I2CIntUnregister (uint32_t ui32Base)
 Unregisters an interrupt handler for the I2C module in the dynamic interrupt table. More...
 

Detailed Description

Introduction

The Inter-Integrated Circuit (I2C) API provides a set of functions for using the CC26xx I2C master and slave module. Functions are provided to perform the following actions:

The I2C master and slave module provide the ability to communicate to other IC devices over an I2C bus. The I2C bus is specified to support devices that can both transmit and receive (write and read) data. Also, devices on the I2C bus can be designated as either a master or a slave. The CC26xx I2C module supports both sending and receiving data as either a master or a slave, and also support the simultaneous operation as both a master and a slave. Finally, the CC26xx I2C module can operate at two speeds: standard (100 kb/s) and fast (400 kb/s).

The master and slave I2C module can generate interrupts. The I2C master module generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave module can generate interrupts when data is sent or requested by a master and when a START or STOP condition is present.

Master Operations

When using this API to drive the I2C master module, the user must first initialize the I2C master module with a call to I2CMasterInitExpClk(). This function sets the bus speed and enables the master module.

The user may transmit or receive data after the successful initialization of the I2C master module. Data is transferred by first setting the slave address using I2CMasterSlaveAddrSet(). This function is also used to define whether the transfer is a send (a write to the slave from the master) or a receive (a read from the slave by the master). Then, if connected to an I2C bus that has multiple masters, the CC26xx I2C master must first call I2CMasterBusBusy() before trying to initiate the desired transaction. After determining that the bus is not busy, if trying to send data, the user must call the I2CMasterDataPut() function. The transaction can then be initiated on the bus by calling the I2CMasterControl() function with any of the following commands:

Any of these commands result in the master arbitrating for the bus, driving the start sequence onto the bus, and sending the slave address and direction bit across the bus. The remainder of the transaction can then be driven using either a polling or interrupt-driven method.

For the single send and receive cases, the polling method involves looping on the return from I2CMasterBusy(). Once the function indicates that the I2C master is no longer busy, the bus transaction is complete and can be checked for errors using I2CMasterErr(). If there are no errors, then the data has been sent or is ready to be read using I2CMasterDataGet(). For the burst send and receive cases, the polling method also involves calling the I2CMasterControl() function for each byte transmitted or received (using either the I2C_MASTER_CMD_BURST_SEND_CONT or I2C_MASTER_CMD_BURST_RECEIVE_CONT commands), and for the last byte sent or received (using either the I2C_MASTER_CMD_BURST_SEND_FINISH or I2C_MASTER_CMD_BURST_RECEIVE_FINISH commands).

If any error is detected during the burst transfer, the appropriate stop command (I2C_MASTER_CMD_BURST_SEND_ERROR_STOP or I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) should be used to call the I2CMasterControl() function.

For the interrupt-driven transaction, the user must register an interrupt handler for the I2C devices and enable the I2C master interrupt; the interrupt occurs when the master is no longer busy.

Slave Operations

When using this API to drive the I2C slave module, the user must first initialize the I2C slave module with a call to I2CSlaveInit(). This function enables the I2C slave module and initializes the address of the slave. After the initialization completes, the user may poll the slave status using I2CSlaveStatus() to determine if a master requested a send or receive operation. Depending on the type of operation requested, the user can call I2CSlaveDataPut() or I2CSlaveDataGet() to complete the transaction. Alternatively, the I2C slave can handle transactions using an interrupt handler registered with I2CIntRegister(), and by enabling the I2C slave interrupt.

API

The I2C API is broken into three groups of functions: those that handle status and initialization, those that deal with sending and receiving data, and those that deal with interrupts.

Status and initialization functions for the I2C module are:

Sending and receiving data from the I2C module is handled by the following functions:

The I2C master and slave interrupts are handled by the following functions:

Function Documentation

§ I2CIntRegister()

void I2CIntRegister ( uint32_t  ui32Base,
void(*)(void)  pfnHandler 
)

Registers an interrupt handler for the I2C module in the dynamic interrupt table.

Note
Only use this function if you want to use the dynamic vector table (in SRAM)!

This function registers a function as the interrupt handler for a specific interrupt and enables the corresponding interrupt in the interrupt controller.

Specific I2C interrupts must be enabled via I2CMasterIntEnable() and I2CSlaveIntEnable(). If necessary, it is the interrupt handler's responsibility to clear the interrupt source via I2CMasterIntClear() and I2CSlaveIntClear().

Parameters
ui32Baseis the base address of the I2C Master module.
pfnHandleris a pointer to the function to be called when the I2C interrupt occurs.
Returns
None
See also
IntRegister() for important information about registering interrupt handlers.

Referenced by I2CSlaveIntStatus().

133 {
134  uint32_t ui32Int;
135 
136  // Check the arguments.
137  ASSERT(I2CBaseValid(ui32Base));
138 
139  // Get the interrupt number.
140  ui32Int = INT_I2C_IRQ;
141 
142  // Register the interrupt handler.
143  IntRegister(ui32Int, pfnHandler);
144 
145  // Enable the I2C interrupt.
146  IntEnable(ui32Int);
147 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71
IntRegister
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Registers a function as an interrupt handler in the dynamic vector table.
Definition: interrupt.c:151
IntEnable
void IntEnable(uint32_t ui32Interrupt)
Enables an interrupt or system exception.
Definition: interrupt.c:281
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§ I2CIntUnregister()

void I2CIntUnregister ( uint32_t  ui32Base)

Unregisters an interrupt handler for the I2C module in the dynamic interrupt table.

This function will clear the handler to be called when an I2C interrupt occurs. This will also mask off the interrupt in the interrupt controller so that the interrupt handler no longer is called.

Parameters
ui32Baseis the base address of the I2C Master module.
Returns
None
See also
IntRegister() for important information about registering interrupt handlers.

Referenced by I2CSlaveIntStatus().

156 {
157  uint32_t ui32Int;
158 
159  // Check the arguments.
160  ASSERT(I2CBaseValid(ui32Base));
161 
162  // Get the interrupt number.
163  ui32Int = INT_I2C_IRQ;
164 
165  // Disable the interrupt.
166  IntDisable(ui32Int);
167 
168  // Unregister the interrupt handler.
169  IntUnregister(ui32Int);
170 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71
IntUnregister
void IntUnregister(uint32_t ui32Interrupt)
Unregisters an interrupt handler in the dynamic vector table.
Definition: interrupt.c:187
IntDisable
void IntDisable(uint32_t ui32Interrupt)
Disables an interrupt or system exception.
Definition: interrupt.c:325
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§ I2CMasterBusBusy()

static bool I2CMasterBusBusy ( uint32_t  ui32Base)
inlinestatic

Indicates whether or not the I2C bus is busy.

This function returns an indication of whether or not the I2C bus is busy. This function can be used in a multi-master environment to determine if another master is currently using the bus.

Parameters
ui32Baseis the base address of the I2C module.
Returns
Returns status of the I2C bus:
  • true : I2C bus is busy.
  • false : I2C bus is not busy.
372 {
373  // Check the arguments.
374  ASSERT(I2CBaseValid(ui32Base));
375 
376  // Return the bus busy status.
377  if(HWREG(ui32Base + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY)
378  {
379  return(true);
380  }
381  else
382  {
383  return(false);
384  }
385 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterBusy()

static bool I2CMasterBusy ( uint32_t  ui32Base)
inlinestatic

Indicates whether or not the I2C Master is busy.

This function returns an indication of whether or not the I2C Master is busy transmitting or receiving data.

Parameters
ui32Baseis the base address of the I2C module.
Returns
Returns status of I2C Master:
  • true : I2C Master is busy.
  • false : I2C Master is not busy.
340 {
341  // Check the arguments.
342  ASSERT(I2CBaseValid(ui32Base));
343 
344  // Return the busy status.
345  if(HWREG(ui32Base + I2C_O_MSTAT) & I2C_MSTAT_BUSY)
346  {
347  return(true);
348  }
349  else
350  {
351  return(false);
352  }
353 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterControl()

static void I2CMasterControl ( uint32_t  ui32Base,
uint32_t  ui32Cmd 
)
inlinestatic

Controls the state of the I2C Master module.

This function is used to control the state of the Master module send and receive operations.

Parameters
ui32Baseis the base address of the I2C module.
ui32Cmdis the command to be issued by the I2C Master module The parameter can be one of the following values:
Returns
None
223 {
224  // Check the arguments.
225  ASSERT(I2CBaseValid(ui32Base));
226  ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||
227  // (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND
228  (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) ||
229  (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
230  (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
231  (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
232  (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
233  (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
234  (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
235  (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
236 
237  // Send the command.
238  HWREG(ui32Base + I2C_O_MCTRL) = ui32Cmd;
239 
240  // Delay minimum four cycles in order to ensure that the I2C_O_MSTAT
241  // register has been correctly updated before function exit
242  CPUdelay(2);
243 }
I2C_MASTER_CMD_BURST_SEND_START
#define I2C_MASTER_CMD_BURST_SEND_START
Definition: i2c.h:100
I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
Definition: i2c.h:106
I2C_MASTER_CMD_SINGLE_SEND
#define I2C_MASTER_CMD_SINGLE_SEND
Definition: i2c.h:96
I2C_MASTER_CMD_BURST_RECEIVE_CONT
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT
Definition: i2c.h:110
ASSERT
#define ASSERT(expr)
Definition: debug.h:71
I2C_MASTER_CMD_BURST_SEND_FINISH
#define I2C_MASTER_CMD_BURST_SEND_FINISH
Definition: i2c.h:104
I2C_MASTER_CMD_BURST_SEND_CONT
#define I2C_MASTER_CMD_BURST_SEND_CONT
Definition: i2c.h:102
I2C_MASTER_CMD_BURST_RECEIVE_FINISH
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH
Definition: i2c.h:112
I2C_MASTER_CMD_BURST_RECEIVE_START
#define I2C_MASTER_CMD_BURST_RECEIVE_START
Definition: i2c.h:108
I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
Definition: i2c.h:114
CPUdelay
void CPUdelay(uint32_t ui32Count)
Provide a small non-zero delay using a simple loop counter.
Definition: cpu.c:342
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§ I2CMasterDataGet()

static uint32_t I2CMasterDataGet ( uint32_t  ui32Base)
inlinestatic

Receives a byte that has been sent to the I2C Master.

This function reads a byte of data from the I2C Master Data Register.

Parameters
ui32Baseis the base address of the I2C module.
Returns
Returns the byte received from by the I2C Master, cast as an uint32_t.
401 {
402  // Check the arguments.
403  ASSERT(I2CBaseValid(ui32Base));
404 
405  // Read a byte.
406  return(HWREG(ui32Base + I2C_O_MDR));
407 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterDataPut()

static void I2CMasterDataPut ( uint32_t  ui32Base,
uint8_t  ui8Data 
)
inlinestatic

Transmits a byte from the I2C Master.

This function will place the supplied data into I2C Master Data Register.

Parameters
ui32Baseis the base address of the I2C module.
ui8Datais the data to be transmitted by the I2C Master
Returns
None
423 {
424  // Check the arguments.
425  ASSERT(I2CBaseValid(ui32Base));
426 
427  // Write the byte.
428  HWREG(ui32Base + I2C_O_MDR) = ui8Data;
429 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71
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§ I2CMasterDisable()

static void I2CMasterDisable ( uint32_t  ui32Base)
inlinestatic

Disables the I2C master block.

This will disable operation of the I2C master block.

Parameters
ui32Baseis the base address of the I2C module.
Returns
None
313 {
314  // Check the arguments.
315  ASSERT(I2CBaseValid(ui32Base));
316 
317  // Disable the master block.
318  HWREG(ui32Base + I2C_O_MCTRL) = 0;
319 
320  // Disable the clock for the master.
321  HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0;
322 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterEnable()

static void I2CMasterEnable ( uint32_t  ui32Base)
inlinestatic

Enables the I2C Master block.

This will enable operation of the I2C Master block.

Parameters
ui32Baseis the base address of the I2C module.
Returns
None

Referenced by I2CMasterInitExpClk().

289 {
290  // Check the arguments.
291  ASSERT(I2CBaseValid(ui32Base));
292 
293  // Enable the clock for the master.
294  HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1;
295 
296  // Enable the master block.
297  HWREG(ui32Base + I2C_O_MCTRL) = I2C_MCTRL_RUN;
298 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterErr()

uint32_t I2CMasterErr ( uint32_t  ui32Base)

Gets the error status of the I2C Master module.

This function is used to obtain the error status of the Master module send and receive operations.

Parameters
ui32Baseis the base address of the I2C module.
Returns
Returns the error status of the Master module:

Referenced by I2CMasterDataPut().

99 {
100  uint32_t ui32Err;
101 
102  // Check the arguments.
103  ASSERT(I2CBaseValid(ui32Base));
104 
105  // Get the raw error state.
106  ui32Err = HWREG(ui32Base + I2C_O_MSTAT);
107 
108  // If the I2C master is busy, then all the other status bits are invalid,
109  // and there is no error to report.
110  if(ui32Err & I2C_MSTAT_BUSY)
111  {
112  return(I2C_MASTER_ERR_NONE);
113  }
114 
115  // Check for errors.
116  if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST))
117  {
118  return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N));
119  }
120  else
121  {
122  return(I2C_MASTER_ERR_NONE);
123  }
124 }
I2C_MASTER_ERR_NONE
#define I2C_MASTER_ERR_NONE
Definition: i2c.h:122
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterInitExpClk()

void I2CMasterInitExpClk ( uint32_t  ui32Base,
uint32_t  ui32I2CClk,
bool  bFast 
)

Initializes the I2C Master block.

This function initializes operation of the I2C Master block. Upon successful initialization of the I2C block, this function will have set the bus speed for the master, and will have enabled the I2C Master block.

If the parameter bFast is true, then the master block will be set up to transfer data at 400 kbps; otherwise, it will be set up to transfer data at 100 kbps.

Parameters
ui32Baseis the base address of the I2C module.
ui32I2CClkis the rate of the clock supplied to the I2C module.
bFastset up for fast data transfers.
Returns
None
64 {
65  uint32_t ui32SCLFreq;
66  uint32_t ui32TPR;
67 
68  // Check the arguments.
69  ASSERT(I2CBaseValid(ui32Base));
70 
71  // Must enable the device before doing anything else.
72  I2CMasterEnable(ui32Base);
73 
74  // Get the desired SCL speed.
75  if(bFast == true)
76  {
77  ui32SCLFreq = 400000;
78  }
79  else
80  {
81  ui32SCLFreq = 100000;
82  }
83 
84  // Compute the clock divider that achieves the fastest speed less than or
85  // equal to the desired speed. The numerator is biased to favor a larger
86  // clock divider so that the resulting clock is always less than or equal
87  // to the desired clock, never greater.
88  ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1;
89  HWREG(ui32Base + I2C_O_MTPR) = ui32TPR;
90 }
I2CMasterEnable
static void I2CMasterEnable(uint32_t ui32Base)
Enables the I2C Master block.
Definition: i2c.h:288
ASSERT
#define ASSERT(expr)
Definition: debug.h:71
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§ I2CMasterIntClear()

static void I2CMasterIntClear ( uint32_t  ui32Base)
inlinestatic

Clears I2C Master interrupt sources.

The I2C Master interrupt source is cleared, so that it no longer asserts. This must be done in the interrupt handler to keep it from being called again immediately upon exit.

Note
Due to write buffers and synchronizers in the system it may take several clock cycles from a register write clearing an event in a module and until the event is actually cleared in the NVIC of the system CPU. It is recommended to clear the event source early in the interrupt service routine (ISR) to allow the event clear to propagate to the NVIC before returning from the ISR. At the same time, an early event clear allows new events of the same type to be pended instead of ignored if the event is cleared later in the ISR. It is the responsibility of the programmer to make sure that enough time has passed before returning from the ISR to avoid false re-triggering of the cleared event. A simple, although not necessarily optimal, way of clearing an event before returning from the ISR is:
  1. Write to clear event (interrupt source). (buffered write)
  2. Dummy read from the event source module. (making sure the write has propagated)
  3. Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
Parameters
ui32Baseis the base address of the I2C module.
Returns
None
521 {
522  // Check the arguments.
523  ASSERT(I2CBaseValid(ui32Base));
524 
525  // Clear the I2C master interrupt source.
526  HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC;
527 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterIntDisable()

static void I2CMasterIntDisable ( uint32_t  ui32Base)
inlinestatic

Disables the I2C Master interrupt.

Disables the I2C Master interrupt source.

Parameters
ui32Baseis the base address of the I2C module.
Returns
None
483 {
484  // Check the arguments.
485  ASSERT(I2CBaseValid(ui32Base));
486 
487  // Disable the master interrupt.
488  HWREG(ui32Base + I2C_O_MIMR) = 0;
489 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterIntEnable()

static void I2CMasterIntEnable ( uint32_t  ui32Base)
inlinestatic

Enables the I2C Master interrupt.

Enables the I2C Master interrupt source.

Parameters
ui32Baseis the base address of the I2C module.
Returns
None
462 {
463  // Check the arguments.
464  ASSERT(I2CBaseValid(ui32Base));
465 
466  // Enable the master interrupt.
467  HWREG(ui32Base + I2C_O_MIMR) = I2C_MIMR_IM;
468 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterIntStatus()

static bool I2CMasterIntStatus ( uint32_t  ui32Base,
bool  bMasked 
)
inlinestatic

Gets the current I2C Master interrupt status.

This returns the interrupt status for the I2C Master module. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Parameters
ui32Baseis the base address of the I2C Master module.
bMaskedselects either raw or masked interrupt status.
  • false : Raw interrupt status is requested.
  • true : Masked interrupt status is requested.
Returns
Returns the current interrupt status.
  • true : Active.
  • false : Not active.
549 {
550  // Check the arguments.
551  ASSERT(I2CBaseValid(ui32Base));
552 
553  // Return either the interrupt status or the raw interrupt status as
554  // requested.
555  if(bMasked)
556  {
557  return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false);
558  }
559  else
560  {
561  return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false);
562  }
563 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CMasterSlaveAddrSet()

static void I2CMasterSlaveAddrSet ( uint32_t  ui32Base,
uint8_t  ui8SlaveAddr,
bool  bReceive 
)
inlinestatic

Sets the address that the I2C Master will place on the bus.

This function will set the address that the I2C Master will place on the bus when initiating a transaction. When the bReceive parameter is set to true, the address will indicate that the I2C Master is initiating a read from the slave; otherwise the address will indicate that the I2C Master is initiating a write to the slave.

Parameters
ui32Baseis the base address of the I2C module.
ui8SlaveAddris a 7-bit slave address
bReceiveflag indicates the type of communication with the slave.
  • true : I2C Master is initiating a read from the slave.
  • false : I2C Master is initiating a write to the slave.
Returns
None
267 {
268  // Check the arguments.
269  ASSERT(I2CBaseValid(ui32Base));
270  ASSERT(!(ui8SlaveAddr & 0x80));
271 
272  // Set the address of the slave with which the master will communicate.
273  HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;
274 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveAddressSet()

static void I2CSlaveAddressSet ( uint32_t  ui32Base,
uint8_t  ui8SlaveAddr 
)
inlinestatic

Sets the I2C slave address.

This function writes the specified slave address.

Parameters
ui32Baseis the base address of the I2C Slave module.
ui8SlaveAddris the 7-bit slave address
Returns
None.
634 {
635  // Check the arguments.
636  ASSERT(I2CBaseValid(ui32Base));
637  ASSERT(!(ui8SlaveAddr & 0x80));
638 
639  // Set up the primary slave address.
640  HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
641 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveDataGet()

static uint32_t I2CSlaveDataGet ( uint32_t  ui32Base)
inlinestatic

Receives a byte that has been sent to the I2C Slave.

This function reads a byte of data from the I2C Slave Data Register.

Parameters
ui32Baseis the base address of the I2C Slave module.
Returns
Returns the byte received from by the I2C Slave, cast as an uint32_t.
707 {
708  // Check the arguments.
709  ASSERT(I2CBaseValid(ui32Base));
710 
711  // Read a byte.
712  return(HWREG(ui32Base + I2C_O_SDR));
713 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveDataPut()

static void I2CSlaveDataPut ( uint32_t  ui32Base,
uint8_t  ui8Data 
)
inlinestatic

Transmits a byte from the I2C Slave.

This function will place the supplied data into I2C Slave Data Register.

Parameters
ui32Baseis the base address of the I2C Slave module.
ui8Datadata to be transmitted from the I2C Slave.
Returns
None
729 {
730  // Check the arguments.
731  ASSERT(I2CBaseValid(ui32Base));
732 
733  // Write the byte.
734  HWREG(ui32Base + I2C_O_SDR) = ui8Data;
735 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveDisable()

static void I2CSlaveDisable ( uint32_t  ui32Base)
inlinestatic

Disables the I2C slave block.

This will disable operation of the I2C slave block.

Parameters
ui32Baseis the base address of the I2C Slave module.
Returns
None
656 {
657  // Check the arguments.
658  ASSERT(I2CBaseValid(ui32Base));
659 
660  // Disable the slave.
661  HWREG(ui32Base + I2C_O_SCTL) = 0x0;
662 
663  // Disable the clock to the slave block.
664  HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0;
665 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveEnable()

static void I2CSlaveEnable ( uint32_t  ui32Base)
inlinestatic

Enables the I2C Slave block.

This will enable operation of the I2C Slave block.

Parameters
ui32Baseis the base address of the I2C Slave module.
Returns
None

Referenced by I2CSlaveInit().

578 {
579  // Check the arguments.
580  ASSERT(I2CBaseValid(ui32Base));
581 
582  // Enable the clock to the slave block.
583  HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1;
584 
585  // Enable the slave.
586  HWREG(ui32Base + I2C_O_SCTL) = I2C_SCTL_DA;
587 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveInit()

static void I2CSlaveInit ( uint32_t  ui32Base,
uint8_t  ui8SlaveAddr 
)
inlinestatic

Initializes the I2C Slave block.

This function initializes operation of the I2C Slave block. Upon successful initialization of the I2C blocks, this function will have set the slave address and have enabled the I2C Slave block.

The parameter ui8SlaveAddr is the value that will be compared against the slave address sent by an I2C master.

Parameters
ui32Baseis the base address of the I2C Slave module.
ui8SlaveAddris the 7-bit slave address.
Returns
None
608 {
609  // Check the arguments.
610  ASSERT(I2CBaseValid(ui32Base));
611  ASSERT(!(ui8SlaveAddr & 0x80));
612 
613  // Must enable the device before doing anything else.
614  I2CSlaveEnable(ui32Base);
615 
616  // Set up the slave address.
617  HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
618 }
I2CSlaveEnable
static void I2CSlaveEnable(uint32_t ui32Base)
Enables the I2C Slave block.
Definition: i2c.h:577
ASSERT
#define ASSERT(expr)
Definition: debug.h:71
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§ I2CSlaveIntClear()

static void I2CSlaveIntClear ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)
inlinestatic

Clears I2C Slave interrupt sources.

The specified I2C Slave interrupt sources are cleared, so that they no longer assert. This must be done in the interrupt handler to keep it from being called again immediately upon exit.

Note
Due to write buffers and synchronizers in the system it may take several clock cycles from a register write clearing an event in a module and until the event is actually cleared in the NVIC of the system CPU. It is recommended to clear the event source early in the interrupt service routine (ISR) to allow the event clear to propagate to the NVIC before returning from the ISR. At the same time, an early event clear allows new events of the same type to be pended instead of ignored if the event is cleared later in the ISR. It is the responsibility of the programmer to make sure that enough time has passed before returning from the ISR to avoid false re-triggering of the cleared event. A simple, although not necessarily optimal, way of clearing an event before returning from the ISR is:
  1. Write to clear event (interrupt source). (buffered write)
  2. Dummy read from the event source module. (making sure the write has propagated)
  3. Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
Parameters
ui32Baseis the base address of the I2C module.
ui32IntFlagsis a bit mask of the interrupt sources to be cleared. The parameter is the bitwise OR of any of the following:
Returns
None
840 {
841  // Check the arguments.
842  ASSERT(I2CBaseValid(ui32Base));
843 
844  // Clear the I2C slave interrupt source.
845  HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags;
846 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveIntDisable()

static void I2CSlaveIntDisable ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)
inlinestatic

Disables individual I2C Slave interrupt sources.

Disables the indicated I2C Slave interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

Parameters
ui32Baseis the base address of the I2C Slave module.
ui32IntFlagsis the bit mask of the interrupt sources to be disabled. The parameter is the bitwise OR of any of the following:
Returns
None
791 {
792  uint32_t ui32Val;
793 
794  // Check the arguments.
795  ASSERT(I2CBaseValid(ui32Base));
796  ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START |
797  I2C_SLAVE_INT_DATA));
798 
799  // Disable the slave interrupt.
800  ui32Val = HWREG(ui32Base + I2C_O_SIMR);
801  ui32Val &= ~ui32IntFlags;
802  HWREG(ui32Base + I2C_O_SIMR) = ui32Val;
803 }
I2C_SLAVE_INT_STOP
#define I2C_SLAVE_INT_STOP
Definition: i2c.h:142
I2C_SLAVE_INT_START
#define I2C_SLAVE_INT_START
Definition: i2c.h:143
I2C_SLAVE_INT_DATA
#define I2C_SLAVE_INT_DATA
Definition: i2c.h:144
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveIntEnable()

static void I2CSlaveIntEnable ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)
inlinestatic

Enables individual I2C Slave interrupt sources.

Enables the indicated I2C Slave interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

Parameters
ui32Baseis the base address of the I2C module.
ui32IntFlagsis the bit mask of the slave interrupt sources to be enabled. The parameter is the bitwise OR of any of the following:
Returns
None
757 {
758  uint32_t ui32Val;
759 
760  // Check the arguments.
761  ASSERT(I2CBaseValid(ui32Base));
762  ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START |
763  I2C_SLAVE_INT_DATA));
764 
765  // Enable the slave interrupt.
766  ui32Val = HWREG(ui32Base + I2C_O_SIMR);
767  ui32Val |= ui32IntFlags;
768  HWREG(ui32Base + I2C_O_SIMR) = ui32Val;
769 }
I2C_SLAVE_INT_STOP
#define I2C_SLAVE_INT_STOP
Definition: i2c.h:142
I2C_SLAVE_INT_START
#define I2C_SLAVE_INT_START
Definition: i2c.h:143
I2C_SLAVE_INT_DATA
#define I2C_SLAVE_INT_DATA
Definition: i2c.h:144
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

§ I2CSlaveIntStatus()

static uint32_t I2CSlaveIntStatus ( uint32_t  ui32Base,
bool  bMasked 
)
inlinestatic

Gets the current I2C Slave interrupt status.

This returns the interrupt status for the I2C Slave module. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Parameters
ui32Baseis the base address of the I2C Slave module.
bMaskedselects either raw or masked interrupt status.
  • false : Raw interrupt status is requested.
  • true : Masked interrupt status is requested.
Returns
Returns the current interrupt status as an OR'ed combination of:
869 {
870  // Check the arguments.
871  ASSERT(I2CBaseValid(ui32Base));
872 
873  // Return either the interrupt status or the raw interrupt status as
874  // requested.
875  if(bMasked)
876  {
877  return(HWREG(ui32Base + I2C_O_SMIS));
878  }
879  else
880  {
881  return(HWREG(ui32Base + I2C_O_SRIS));
882  }
883 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71
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§ I2CSlaveStatus()

static uint32_t I2CSlaveStatus ( uint32_t  ui32Base)
inlinestatic

Gets the I2C Slave module status.

This function will return the action requested from a master, if any.

Parameters
ui32Baseis the base address of the I2C Slave module.
Returns
Returns the status of the I2C Slave module:
685 {
686  // Check the arguments.
687  ASSERT(I2CBaseValid(ui32Base));
688 
689  // Return the slave status.
690  return(HWREG(ui32Base + I2C_O_SSTAT));
691 }
ASSERT
#define ASSERT(expr)
Definition: debug.h:71

Macro Definition Documentation

§ I2C_MASTER_CMD_BURST_RECEIVE_CONT

#define I2C_MASTER_CMD_BURST_RECEIVE_CONT   0x00000009

Referenced by I2CMasterControl().

§ I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP

#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP   0x00000004

Referenced by I2CMasterControl().

§ I2C_MASTER_CMD_BURST_RECEIVE_FINISH

#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH   0x00000005

Referenced by I2CMasterControl().

§ I2C_MASTER_CMD_BURST_RECEIVE_START

#define I2C_MASTER_CMD_BURST_RECEIVE_START   0x0000000b

Referenced by I2CMasterControl().

§ I2C_MASTER_CMD_BURST_SEND_CONT

#define I2C_MASTER_CMD_BURST_SEND_CONT   0x00000001

Referenced by I2CMasterControl().

§ I2C_MASTER_CMD_BURST_SEND_ERROR_STOP

#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP   0x00000004

Referenced by I2CMasterControl().

§ I2C_MASTER_CMD_BURST_SEND_FINISH

#define I2C_MASTER_CMD_BURST_SEND_FINISH   0x00000005

Referenced by I2CMasterControl().

§ I2C_MASTER_CMD_BURST_SEND_START

#define I2C_MASTER_CMD_BURST_SEND_START   0x00000003

Referenced by I2CMasterControl().

§ I2C_MASTER_CMD_SINGLE_RECEIVE

#define I2C_MASTER_CMD_SINGLE_RECEIVE   0x00000007

§ I2C_MASTER_CMD_SINGLE_SEND

#define I2C_MASTER_CMD_SINGLE_SEND   0x00000007

Referenced by I2CMasterControl().

§ I2C_MASTER_ERR_ADDR_ACK

#define I2C_MASTER_ERR_ADDR_ACK   0x00000004

§ I2C_MASTER_ERR_ARB_LOST

#define I2C_MASTER_ERR_ARB_LOST   0x00000010

§ I2C_MASTER_ERR_DATA_ACK

#define I2C_MASTER_ERR_DATA_ACK   0x00000008

§ I2C_MASTER_ERR_NONE

#define I2C_MASTER_ERR_NONE   0

Referenced by I2CMasterErr().

§ I2C_SLAVE_ACT_NONE

#define I2C_SLAVE_ACT_NONE   0

§ I2C_SLAVE_ACT_RREQ

#define I2C_SLAVE_ACT_RREQ   0x00000001

§ I2C_SLAVE_ACT_RREQ_FBR

#define I2C_SLAVE_ACT_RREQ_FBR   0x00000005

§ I2C_SLAVE_ACT_TREQ

#define I2C_SLAVE_ACT_TREQ   0x00000002

§ I2C_SLAVE_INT_DATA

#define I2C_SLAVE_INT_DATA   0x00000001

Referenced by I2CSlaveIntDisable(), and I2CSlaveIntEnable().

§ I2C_SLAVE_INT_START

#define I2C_SLAVE_INT_START   0x00000002

Referenced by I2CSlaveIntDisable(), and I2CSlaveIntEnable().

§ I2C_SLAVE_INT_STOP

#define I2C_SLAVE_INT_STOP   0x00000004

Referenced by I2CSlaveIntDisable(), and I2CSlaveIntEnable().