[interrupt.h] Interrupt

Functions
void	IntRegister (uint32_t ui32Interrupt, void(*pfnHandler)(void))
	Registers a function as an interrupt handler in the dynamic vector table. More...
void	IntUnregister (uint32_t ui32Interrupt)
	Unregisters an interrupt handler in the dynamic vector table. More...
void	IntPriorityGroupingSet (uint32_t ui32Bits)
	Sets the priority grouping of the interrupt controller. More...
uint32_t	IntPriorityGroupingGet (void)
	Gets the priority grouping of the interrupt controller. More...
void	IntPrioritySet (uint32_t ui32Interrupt, uint8_t ui8Priority)
	Sets the priority of an interrupt. More...
int32_t	IntPriorityGet (uint32_t ui32Interrupt)
	Gets the priority of an interrupt. More...
void	IntEnable (uint32_t ui32Interrupt)
	Enables an interrupt or system exception. More...
void	IntDisable (uint32_t ui32Interrupt)
	Disables an interrupt or system exception. More...
void	IntPendSet (uint32_t ui32Interrupt)
	Pends an interrupt. More...
bool	IntPendGet (uint32_t ui32Interrupt)
	Checks if an interrupt is pending. More...
void	IntPendClear (uint32_t ui32Interrupt)
	Unpends an interrupt. More...
static bool	IntMasterEnable (void)
	Enables the CPU interrupt. More...
static bool	IntMasterDisable (void)
	Disables the CPU interrupts with configurable priority. More...
static void	IntPriorityMaskSet (uint32_t ui32PriorityMask)
	Sets the priority masking level. More...
static uint32_t	IntPriorityMaskGet (void)
	Gets the priority masking level. More...

Detailed Description

Introduction

The interrupt controller API provides a set of functions for dealing with the Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable and disable interrupts, register interrupt handlers, and set the priority of interrupts.

The event sources that trigger the interrupt lines in the NVIC are controlled by the MCU event fabric. All event sources are statically connected to the NVIC interrupt lines except one which is programmable. For more information about the MCU event fabric, see the MCU event fabric API.

API

Interrupts and system exceptions must be individually enabled and disabled through:

• IntEnable()
• IntDisable()

The global CPU interrupt can be enabled and disabled with the following functions:

• IntMasterEnable()
• IntMasterDisable()

This does not affect the individual interrupt enable states. Masking of the CPU interrupt can be used as a simple critical section (only an NMI can interrupt the CPU while the CPU interrupt is disabled), although masking the CPU interrupt can increase the interrupt response time.

It is possible to access the NVIC to see if any interrupts are pending and manually clear pending interrupts which have not yet been serviced or set a specific interrupt as pending to be handled based on its priority. Pending interrupts are cleared automatically when the interrupt is accepted and executed. However, the event source which caused the interrupt might need to be cleared manually to avoid re-triggering the corresponding interrupt. The functions to read, clear, and set pending interrupts are:

• IntPendGet()
• IntPendClear()
• IntPendSet()

The interrupt prioritization in the NVIC allows handling of higher priority interrupts before lower priority interrupts, as well as allowing preemption of lower priority interrupt handlers by higher priority interrupts. The device supports eight priority levels from 0 to 7 with 0 being the highest priority. The priority of each interrupt source can be set and examined using:

• IntPrioritySet()
• IntPriorityGet()

Interrupts can be masked based on their priority such that interrupts with the same or lower priority than the mask are effectively disabled. This can be configured with:

• IntPriorityMaskSet()
• IntPriorityMaskGet()

Subprioritization is also possible. Instead of having three bits of preemptable prioritization (eight levels), the NVIC can be configured for 3 - M bits of preemptable prioritization and M bits of subpriority. In this scheme, two interrupts with the same preemptable prioritization but different subpriorities do not cause a preemption. Instead, tail chaining is used to process the two interrupts back-to-back. If two interrupts with the same priority (and subpriority if so configured) are asserted at the same time, the one with the lower interrupt number is processed first. Subprioritization is handled by:

• IntPriorityGroupingSet()
• IntPriorityGroupingGet()

Interrupt Vector Table

The interrupt vector table can be configured in one of two ways:

• Statically (at compile time): Vector table is placed in Flash and each entry has a fixed pointer to an interrupt handler (ISR).
• Dynamically (at runtime): Vector table is placed in SRAM and each entry can be changed (registered or unregistered) at runtime. This allows a single interrupt to trigger different interrupt handlers (ISRs) depending on which interrupt handler is registered at the time the System CPU responds to the interrupt.

When configured, the interrupts must be explicitly enabled in the NVIC through IntEnable() before the CPU can respond to the interrupt (in addition to any interrupt enabling required within the peripheral).

Static Vector Table

Static registration of interrupt handlers is accomplished by editing the interrupt handler table in the startup code of the application. Texas Instruments provides startup files for each supported compiler ( startup_<compiler>.c ) and these startup files include a default static interrupt vector table. All entries, except ResetISR, are declared as extern with weak assignment to a default interrupt handler. This allows the user to declare and define a function (in the user's code) with the same name as an entry in the vector table. At compile time, the linker then replaces the pointer to the default interrupt handler in the vector table with the pointer to the interrupt handler defined by the user.

Statically configuring the interrupt table provides the fastest interrupt response time because the stacking operation (a write to SRAM on the data bus) is performed in parallel with the interrupt handler table fetch (a read from Flash on the instruction bus), as well as the prefetch of the interrupt handler (assuming it is also in Flash).

Dynamic Vector Table

Alternatively, interrupts can be registered in the vector table at runtime, thus dynamically. The dynamic vector table is placed in SRAM and the code can then modify the pointers to interrupt handlers throughout the application.

DriverLib uses these two functions to modify the dynamic vector table:

• IntRegister() : Write a pointer to an interrupt handler into the vector table.
• IntUnregister() : Write pointer to default interrupt handler into the vector table.

Note

First call to IntRegister() initializes the vector table in SRAM by copying the static vector table from Flash and forcing the NVIC to use the dynamic vector table from this point forward. If using the dynamic vector table it is highly recommended to initialize it during the setup phase of the application. The NVIC uses the static vector table in Flash until the application initializes the dynamic vector table in SRAM.

Runtime configuration of interrupts adds a small latency to the interrupt response time because the stacking operation (a write to SRAM on the data bus) and the interrupt handler fetch from the vector table (a read from SRAM on the instruction bus) must be performed sequentially.

The dynamic vector table, g_pfnRAMVectors, is placed in SRAM in the section called vtable_ram which is a section defined in the linker file. By default the linker file places this section at the start of the SRAM but this is configurable by the user.

Warning

Runtime configuration of interrupt handlers requires that the interrupt handler table is placed on a 256-byte boundary in SRAM (typically, this is at the beginning of SRAM). Failure to do so results in an incorrect vector address being fetched in response to an interrupt.

Function Documentation

IntDisable()

void IntDisable

(

uint32_t

ui32Interrupt

)

Disables an interrupt or system exception.

This function disables the specified interrupt in the interrupt controller.

Parameters

ui32Interrupt

specifies the index in the vector table to disable. See IntEnable() for list of valid arguments.

Returns

None

See also

IntEnable()

Referenced by AESIntUnregister(), AESWriteToKeyStore(), FlashIntUnregister(), I2CIntUnregister(), I2SIntUnregister(), IOCIntUnregister(), SHA2IntUnregister(), SSIIntUnregister(), TimerIntUnregister(), TRNGIntUnregister(), UARTIntUnregister(), uDMAIntUnregister(), and WatchdogIntUnregister().

{
    // Check the arguments.
    ASSERT(ui32Interrupt < NUM_INTERRUPTS);

    // Determine the interrupt to disable.
    if(ui32Interrupt == INT_MEMMANAGE_FAULT)
    {
        // Disable the MemManage interrupt.
        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
    }
    else if(ui32Interrupt == INT_BUS_FAULT)
    {
        // Disable the bus fault interrupt.
        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
    }
    else if(ui32Interrupt == INT_USAGE_FAULT)
    {
        // Disable the usage fault interrupt.
        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
    }
    else if(ui32Interrupt == INT_SYSTICK)
    {
        // Disable the System Tick interrupt.
        HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
    }
    else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
    {
        // Disable the general interrupt.
        HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16);
    }
    else if(ui32Interrupt >= 48)
    {
        // Disable the general interrupt.
        HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48);
    }
}

IntEnable()

void IntEnable

(

uint32_t

ui32Interrupt

)

Enables an interrupt or system exception.

This function enables the specified interrupt in the interrupt controller.

Note

If a fault condition occurs while the corresponding system exception is disabled, the fault is treated as a Hard Fault.

Parameters

ui32Interrupt

specifies the index in the vector table to enable. System exceptions: INT_MEMMANAGE_FAULT INT_BUS_FAULT INT_USAGE_FAULT INT_SYSTICK Interrupts: INT_AON_GPIO_EDGE INT_I2C_IRQ INT_RFC_CPE_1 INT_AON_RTC_COMB INT_UART0_COMB INT_AUX_SWEV0 INT_SSI0_COMB INT_RFC_CPE_0 INT_RFC_HW_COMB INT_RFC_CMD_ACK INT_I2S_IRQ INT_AUX_SWEV1 INT_WDT_IRQ INT_GPT0A INT_GPT0B INT_GPT1A INT_GPT1B INT_GPT2A INT_GPT2B INT_GPT3A INT_GPT3B INT_CRYPTO_RESULT_AVAIL_IRQ INT_DMA_DONE_COMB INT_DMA_ERR INT_FLASH INT_SWEV0 INT_AUX_COMB INT_AON_PROG0 INT_PROG0 (Programmable interrupt, see EventRegister()) INT_AUX_COMPA INT_AUX_ADC_IRQ INT_TRNG_IRQ INT_OSC_COMB INT_BATMON_COMB INT_PKA_IRQ INT_SSI1_COMB INT_UART1_COMB INT_AUX_TIMER2_EV0

Returns

None

See also

IntDisable()

Referenced by AESIntRegister(), AESWriteToKeyStore(), FlashIntRegister(), I2CIntRegister(), I2SIntRegister(), IOCIntRegister(), SHA2IntRegister(), SSIIntRegister(), TimerIntRegister(), TRNGIntRegister(), UARTIntRegister(), uDMAIntRegister(), and WatchdogIntRegister().

{
    // Check the arguments.
    ASSERT(ui32Interrupt < NUM_INTERRUPTS);

    // Determine the interrupt to enable.
    if(ui32Interrupt == INT_MEMMANAGE_FAULT)
    {
        // Enable the MemManage interrupt.
        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
    }
    else if(ui32Interrupt == INT_BUS_FAULT)
    {
        // Enable the bus fault interrupt.
        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
    }
    else if(ui32Interrupt == INT_USAGE_FAULT)
    {
        // Enable the usage fault interrupt.
        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
    }
    else if(ui32Interrupt == INT_SYSTICK)
    {
        // Enable the System Tick interrupt.
        HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
    }
    else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
    {
        // Enable the general interrupt.
        HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16);
    }
    else if(ui32Interrupt >= 48)
    {
        // Enable the general interrupt.
        HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48);
    }
}

IntMasterDisable()

static bool IntMasterDisable ( void  )

inlinestatic

Disables the CPU interrupts with configurable priority.

Prevents the CPU from receiving interrupts except NMI and hard fault. This does not affect the set of interrupts enabled in the interrupt controller; it just gates the interrupt from the interrupt controller to the CPU.

Returns

Returns:

• true : Interrupts were already disabled when the function was called.
• false : Interrupts were enabled and are now disabled.

{
    // Disable CPU interrupts.
    return(CPUcpsid());
}

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IntMasterEnable()

static bool IntMasterEnable ( void  )

inlinestatic

Enables the CPU interrupt.

Allows the CPU to respond to interrupts.

Returns

Returns:

• true : Interrupts were disabled and are now enabled.
• false : Interrupts were already enabled when the function was called.

{
    // Enable CPU interrupts.
    return(CPUcpsie());
}

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IntPendClear()

void IntPendClear

(

uint32_t

ui32Interrupt

)

Unpends an interrupt.

This function unpends the specified interrupt in the interrupt controller. This causes any previously generated interrupts that have not been handled yet (due to higher priority interrupts or the interrupt no having been enabled yet) to be discarded.

Note

It is not possible to unpend the NMI because it takes effect immediately when being pended.

Parameters

ui32Interrupt

specifies the index in the vector table to unpend. See IntPendSet() for list of valid arguments (except NMI).

Returns

None

Referenced by AESWriteToKeyStore(), and SetupTrimDevice().

{
    // Check the arguments.
    ASSERT(ui32Interrupt < NUM_INTERRUPTS);

    // Determine the interrupt to unpend.
    if(ui32Interrupt == INT_PENDSV)
    {
        // Unpend the PendSV interrupt.
        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
    }
    else if(ui32Interrupt == INT_SYSTICK)
    {
        // Unpend the SysTick interrupt.
        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
    }
    else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
    {
        // Unpend the general interrupt.
        HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16);
    }
    else if(ui32Interrupt >= 48)
    {
        // Unpend the general interrupt.
        HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48);
    }
}

IntPendGet()

bool IntPendGet

(

uint32_t

ui32Interrupt

)

Checks if an interrupt is pending.

This function checks the interrupt controller to see if an interrupt is pending.

The interrupt must be enabled in order for the corresponding interrupt handler to be executed, so an interrupt can be pending waiting to be enabled or waiting for an interrupt of higher priority to be done executing.

Note

This function does not support reading pending status for system exceptions (vector table indexes <16).

Parameters

ui32Interrupt

specifies the index in the vector table to check pending status for. See IntPendSet() for list of valid arguments (except system exceptions).

Returns

Returns:

• true : Specified interrupt is pending.
• false : Specified interrupt is not pending.

{
    uint32_t ui32IntPending;

    // Check the arguments.
    ASSERT(ui32Interrupt < NUM_INTERRUPTS);

    // Assume no interrupts are pending.
    ui32IntPending = 0;

    // The lower 16 IRQ vectors are unsupported by this function
    if (ui32Interrupt < 16)
    {

       return 0;
    }

    // Subtract lower 16 irq vectors
    ui32Interrupt -= 16;

    // Check if the interrupt is pending
    ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32));
    ui32IntPending &= (1 << (ui32Interrupt & 31));

    return ui32IntPending ? true : false;
}

IntPendSet()

void IntPendSet

(

uint32_t

ui32Interrupt

)

Pends an interrupt.

This function pends the specified interrupt in the interrupt controller. This causes the interrupt controller to execute the corresponding interrupt handler at the next available time, based on the current interrupt state priorities.

This interrupt controller automatically clears the pending interrupt once the interrupt handler is executed.

Parameters

ui32Interrupt

specifies the index in the vector table to pend. System exceptions: INT_NMI_FAULT INT_PENDSV INT_SYSTICK Interrupts: INT_AON_GPIO_EDGE INT_I2C_IRQ INT_RFC_CPE_1 INT_AON_RTC_COMB INT_UART0_COMB INT_AUX_SWEV0 INT_SSI0_COMB INT_RFC_CPE_0 INT_RFC_HW_COMB INT_RFC_CMD_ACK INT_I2S_IRQ INT_AUX_SWEV1 INT_WDT_IRQ INT_GPT0A INT_GPT0B INT_GPT1A INT_GPT1B INT_GPT2A INT_GPT2B INT_GPT3A INT_GPT3B INT_CRYPTO_RESULT_AVAIL_IRQ INT_DMA_DONE_COMB INT_DMA_ERR INT_FLASH INT_SWEV0 INT_AUX_COMB INT_AON_PROG0 INT_PROG0 (Programmable interrupt, see EventRegister()) INT_AUX_COMPA INT_AUX_ADC_IRQ INT_TRNG_IRQ INT_OSC_COMB INT_BATMON_COMB INT_PKA_IRQ INT_SSI1_COMB INT_UART1_COMB INT_AUX_TIMER2_EV0

Returns

None

See also

IntEnable()

{
    // Check the arguments.
    ASSERT(ui32Interrupt < NUM_INTERRUPTS);

    // Determine the interrupt to pend.
    if(ui32Interrupt == INT_NMI_FAULT)
    {
        // Pend the NMI interrupt.
        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
    }
    else if(ui32Interrupt == INT_PENDSV)
    {
        // Pend the PendSV interrupt.
        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
    }
    else if(ui32Interrupt == INT_SYSTICK)
    {
        // Pend the SysTick interrupt.
        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
    }
    else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
    {
        // Pend the general interrupt.
        HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16);
    }
    else if(ui32Interrupt >= 48)
    {
        // Pend the general interrupt.
        HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48);
    }
}

IntPriorityGet()

int32_t IntPriorityGet

(

uint32_t

ui32Interrupt

)

Gets the priority of an interrupt.

This function gets the priority of an interrupt.

Warning

This function does not support getting priority of interrupt vectors one through three which are:

• 1: Reset handler
• 2: NMI handler
• 3: Hard fault handler

Parameters

ui32Interrupt

specifies the index in the vector table to read priority of. See IntPrioritySet() for list of valid arguments.

Returns

Returns the interrupt priority:

• INT_PRI_LEVEL0 : Highest priority.
• INT_PRI_LEVEL1
• INT_PRI_LEVEL2
• INT_PRI_LEVEL3
• INT_PRI_LEVEL4
• INT_PRI_LEVEL5
• INT_PRI_LEVEL6
• INT_PRI_LEVEL7 : Lowest priority.

{
    // Check the arguments.
    ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));

    // Return the interrupt priority.
    return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) &
           0xFF);
}

IntPriorityGroupingGet()

uint32_t IntPriorityGroupingGet

(

void

)

Gets the priority grouping of the interrupt controller.

This function returns the split between preemptable priority levels and subpriority levels in the interrupt priority specification.

Returns

Returns the number of bits of preemptable priority.

• 0 : No pre-emption priority, eight bits of subpriority.
• 1 : One bit of pre-emption priority, seven bits of subpriority
• 2 : Two bits of pre-emption priority, six bits of subpriority
• 3-7 : Three bits of pre-emption priority, five bits of subpriority

{
    uint32_t ui32Loop, ui32Value;

    // Read the priority grouping.
    ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;

    // Loop through the priority grouping values.
    for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++)
    {
        // Stop looping if this value matches.
        if(ui32Value == g_pui32Priority[ui32Loop])
        {
            break;
        }
    }

    // Return the number of priority bits.
    return(ui32Loop);
}

IntPriorityGroupingSet()

void IntPriorityGroupingSet

(

uint32_t

ui32Bits

)

Sets the priority grouping of the interrupt controller.

This function specifies the split between preemptable priority levels and subpriority levels in the interrupt priority specification.

Three bits are available for hardware interrupt prioritization thus priority grouping values of three through seven have the same effect.

Parameters

ui32Bits

specifies the number of bits of preemptable priority. 0 : No pre-emption priority, eight bits of subpriority. 1 : One bit of pre-emption priority, seven bits of subpriority 2 : Two bits of pre-emption priority, six bits of subpriority 3-7 : Three bits of pre-emption priority, five bits of subpriority

Returns

None

See also

IntPrioritySet()

{
    // Check the arguments.
    ASSERT(ui32Bits < NUM_PRIORITY);

    // Set the priority grouping.
    HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits];
}

IntPriorityMaskGet()

static uint32_t IntPriorityMaskGet ( void  )

inlinestatic

Gets the priority masking level.

This function gets the current setting of the interrupt priority masking level. The value returned is the priority level such that all interrupts of that and lesser priority are masked. A value of 0 means that priority masking is disabled.

Smaller numbers correspond to higher interrupt priorities. So for example a priority level mask of 4 will allow interrupts of priority level 0-3, and interrupts with a numerical priority of 4 and greater will be blocked.

Returns

Returns the value of the interrupt priority level mask.

{
    return(CPUbasepriGet());
}

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IntPriorityMaskSet()

static void IntPriorityMaskSet ( uint32_t  ui32PriorityMask )

inlinestatic

Sets the priority masking level.

This function sets the interrupt priority masking level so that all interrupts at the specified or lesser priority level are masked. This can be used to globally disable a set of interrupts with priority below a predetermined threshold. A value of 0 disables priority masking.

Smaller numbers correspond to higher interrupt priorities. So for example a priority level mask of 4 will allow interrupts of priority level 0-3, and interrupts with a numerical priority of 4 and greater will be blocked. The device supports priority levels 0 through 7.

Parameters

ui32PriorityMask

is the priority level that will be masked. 0 : Disable priority masking. 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7. 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7. 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7. 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7. 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7. 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7. 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7.

Returns

None.

{
    CPUbasepriSet(ui32PriorityMask);
}

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IntPrioritySet()

void IntPrioritySet	(	uint32_t	ui32Interrupt,
		uint8_t	ui8Priority
	)

Sets the priority of an interrupt.

This function sets the priority of an interrupt, including system exceptions. When multiple interrupts are asserted simultaneously, the ones with the highest priority are processed before the lower priority interrupts. Smaller numbers correspond to higher interrupt priorities thus priority 0 is the highest interrupt priority.

Warning

This function does not support setting priority of interrupt vectors one through three which are:

• 1: Reset handler
• 2: NMI handler
• 3: Hard fault handler

Parameters

ui32Interrupt

specifies the index in the vector table to change priority for. System exceptions: INT_MEMMANAGE_FAULT INT_BUS_FAULT INT_USAGE_FAULT INT_SVCALL INT_DEBUG INT_PENDSV INT_SYSTICK Interrupts: INT_AON_GPIO_EDGE INT_I2C_IRQ INT_RFC_CPE_1 INT_AON_RTC_COMB INT_UART0_COMB INT_AUX_SWEV0 INT_SSI0_COMB INT_RFC_CPE_0 INT_RFC_HW_COMB INT_RFC_CMD_ACK INT_I2S_IRQ INT_AUX_SWEV1 INT_WDT_IRQ INT_GPT0A INT_GPT0B INT_GPT1A INT_GPT1B INT_GPT2A INT_GPT2B INT_GPT3A INT_GPT3B INT_CRYPTO_RESULT_AVAIL_IRQ INT_DMA_DONE_COMB INT_DMA_ERR INT_FLASH INT_SWEV0 INT_AUX_COMB INT_AON_PROG0 INT_PROG0 (Programmable interrupt, see EventRegister()) INT_AUX_COMPA INT_AUX_ADC_IRQ INT_TRNG_IRQ INT_OSC_COMB INT_BATMON_COMB INT_PKA_IRQ INT_SSI1_COMB INT_UART1_COMB INT_AUX_TIMER2_EV0

ui8Priority

specifies the priority of the interrupt. INT_PRI_LEVEL0 : Highest priority. INT_PRI_LEVEL1 INT_PRI_LEVEL2 INT_PRI_LEVEL3 INT_PRI_LEVEL4 INT_PRI_LEVEL5 INT_PRI_LEVEL6 INT_PRI_LEVEL7 : Lowest priority.

Returns

None

See also

IntPriorityGroupingSet()

{
    uint32_t ui32Temp;

    // Check the arguments.
    ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
    ASSERT(ui8Priority <= INT_PRI_LEVEL7);

    // Set the interrupt priority.
    ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]);
    ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3)));
    ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3));
    HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp;
}

IntRegister()

void IntRegister	(	uint32_t	ui32Interrupt,
		void(*)(void)	pfnHandler
	)

Registers a function as an interrupt handler in the dynamic vector table.

Note

Only use this function if you want to use the dynamic vector table (in SRAM)!

This function writes a function pointer to the dynamic interrupt vector table in SRAM to register the function as an interrupt handler (ISR). When the corresponding interrupt occurs, and it has been enabled (see IntEnable()), the function pointer is fetched from the dynamic vector table, and the System CPU will execute the interrupt handler.

Note

The first call to this function (directly or indirectly via a peripheral driver interrupt register function) copies the interrupt vector table from Flash to SRAM. NVIC uses the static vector table (in Flash) until this function is called.

Parameters

ui32Interrupt

specifies the index in the vector table to modify. System exceptions (vectors 0 to 15): INT_NMI_FAULT INT_HARD_FAULT INT_MEMMANAGE_FAULT INT_BUS_FAULT INT_USAGE_FAULT INT_SVCALL INT_DEBUG INT_PENDSV INT_SYSTICK Interrupts (vectors >15): INT_AON_GPIO_EDGE INT_I2C_IRQ INT_RFC_CPE_1 INT_AON_RTC_COMB INT_UART0_COMB INT_AUX_SWEV0 INT_SSI0_COMB INT_RFC_CPE_0 INT_RFC_HW_COMB INT_RFC_CMD_ACK INT_I2S_IRQ INT_AUX_SWEV1 INT_WDT_IRQ INT_GPT0A INT_GPT0B INT_GPT1A INT_GPT1B INT_GPT2A INT_GPT2B INT_GPT3A INT_GPT3B INT_CRYPTO_RESULT_AVAIL_IRQ INT_DMA_DONE_COMB INT_DMA_ERR INT_FLASH INT_SWEV0 INT_AUX_COMB INT_AON_PROG0 INT_PROG0 (Programmable interrupt, see EventRegister()) INT_AUX_COMPA INT_AUX_ADC_IRQ INT_TRNG_IRQ INT_OSC_COMB INT_BATMON_COMB INT_PKA_IRQ INT_SSI1_COMB INT_UART1_COMB INT_AUX_TIMER2_EV0

pfnHandler

is a pointer to the function to register as interrupt handler.

Returns

None.

See also

IntUnregister(), IntEnable()

Referenced by AESIntRegister(), FlashIntRegister(), I2CIntRegister(), I2SIntRegister(), IOCIntRegister(), SHA2IntRegister(), SSIIntRegister(), SysTickIntRegister(), TimerIntRegister(), TRNGIntRegister(), UARTIntRegister(), uDMAIntRegister(), and WatchdogIntRegister().

{
    uint32_t ui32Idx, ui32Value;

    // Check the arguments.
    ASSERT(ui32Interrupt < NUM_INTERRUPTS);

    // Make sure that the RAM vector table is correctly aligned.
    ASSERT(((uint32_t)g_pfnRAMVectors & 0x000000ff) == 0);

    // See if the RAM vector table has been initialized.
    if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors)
    {
        // Copy the vector table from the beginning of FLASH to the RAM vector
        // table.
        ui32Value = HWREG(NVIC_VTABLE);
        for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++)
        {
            g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) +
                                       ui32Value);
        }

        // Point NVIC at the RAM vector table.
        HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors;
    }

    // Save the interrupt handler.
    g_pfnRAMVectors[ui32Interrupt] = pfnHandler;
}

IntUnregister()

void IntUnregister

(

uint32_t

ui32Interrupt

)

Unregisters an interrupt handler in the dynamic vector table.

This function removes an interrupt handler from the dynamic vector table and replaces it with the default interrupt handler IntDefaultHandler().

Note

Remember to disable the interrupt before removing its interrupt handler from the vector table.

Parameters

ui32Interrupt

specifies the index in the vector table to modify. See IntRegister() for list of valid arguments.

Returns

None.

See also

IntRegister(), IntDisable()

Referenced by AESIntUnregister(), FlashIntUnregister(), I2CIntUnregister(), I2SIntUnregister(), IOCIntUnregister(), SHA2IntUnregister(), SSIIntUnregister(), SysTickIntUnregister(), TimerIntUnregister(), TRNGIntUnregister(), UARTIntUnregister(), uDMAIntUnregister(), and WatchdogIntUnregister().

{
    // Check the arguments.
    ASSERT(ui32Interrupt < NUM_INTERRUPTS);

    // Reset the interrupt handler.
    g_pfnRAMVectors[ui32Interrupt] = IntDefaultHandler;
}

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Macro Definition Documentation

INT_PRI_LEVEL0

#define INT_PRI_LEVEL0   0x00000000

INT_PRI_LEVEL1

#define INT_PRI_LEVEL1   0x00000020

INT_PRI_LEVEL2

#define INT_PRI_LEVEL2   0x00000040

INT_PRI_LEVEL3

#define INT_PRI_LEVEL3   0x00000060

INT_PRI_LEVEL4

#define INT_PRI_LEVEL4   0x00000080

INT_PRI_LEVEL5

#define INT_PRI_LEVEL5   0x000000A0

INT_PRI_LEVEL6

#define INT_PRI_LEVEL6   0x000000C0

INT_PRI_LEVEL7

#define INT_PRI_LEVEL7   0x000000E0

Referenced by IntPrioritySet().

INT_PRIORITY_MASK

#define INT_PRIORITY_MASK   0x000000E0