UART2CC32XX_HWAttrs Struct Reference

UART2CC32XX Hardware attributes. More...

#include <UART2CC32XX.h>

Data Fields
UART2_BASE_HWATTRS UART2CC32XX_FifoThreshold	txIntFifoThr
UART2CC32XX_FifoThreshold	rxIntFifoThr
uint32_t	rxDmaChannel
uint32_t	txDmaChannel

Detailed Description

UART2CC32XX Hardware attributes.

The fields, baseAddr and intNum are used by driverlib APIs and therefore must be populated by driverlib macro definitions. These definitions are found under the device family in:

• inc/hw_memmap.h
• inc/hw_ints.h
• driverlib/uart.h

intPriority is the UART peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). The CC32XX uses three of the priority bits, meaning ~0 has the same effect as (7 << 5).

  (7 << 5) will apply the lowest priority.
  (1 << 5) will apply the highest priority.

Setting the priority to 0 is not supported by this driver. HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

A sample structure is shown below:

const UART2CC32XX_HWAttrs UART2CC32XXHWAttrs[] = {
    {
        .baseAddr     = UARTA0_BASE,
        .intNum       = INT_UARTA0,
        .intPriority  = (~0),
        .flowControl  = UART2_FLOWCTRL_NONE,
        .rxPin        = UART2CC32XX_PIN_57_UART0_RX,
        .txPin        = UART2CC32XX_PIN_55_UART0_TX,
        .ctsPin       = UART2CC32XX_PIN_UNASSIGNED,
        .rtsPin       = UART2CC32XX_PIN_UNASSIGNED,
        .txIntFifoThr = UART2CC32XX_FIFO_THRESHOLD_1_8,
        .rxIntFifoThr = UART2CC32XX_FIFO_THRESHOLD_4_8,
        .rxDmaChannel = UDMA_CH8_UARTA0_RX,
        .txDmaChannel = UDMA_CH9_UARTA0_TX,
    },
    {
        .baseAddr     = UARTA1_BASE,
        .intNum       = INT_UARTA1,
        .intPriority  = (~0),
        .flowControl  = UART2_FLOWCTRL_NONE,
        .rxPin        = UART2CC32XX_PIN_08_UART1_RX,
        .txPin        = UART2CC32XX_PIN_07_UART1_TX,
        .ctsPin       = UART2CC32XX_PIN_UNASSIGNED,
        .rtsPin       = UART2CC32XX_PIN_UNASSIGNED,
        .txIntFifoThr = UART2CC32XX_FIFO_THRESHOLD_1_8,
        .rxIntFifoThr = UART2CC32XX_FIFO_THRESHOLD_4_8,
        .rxDmaChannel = UDMA_CH10_UARTA1_RX,
        .txDmaChannel = UDMA_CH11_UARTA1_TX,
    },
};

To enable flow control, the .ctsPin and/or .rtsPin must be assigned. In addition, .flowControl must be set to UART2_FLOWCTRL_HARDWARE.

Field Documentation

txIntFifoThr

UART2_BASE_HWATTRS UART2CC32XX_FifoThreshold UART2CC32XX_HWAttrs::txIntFifoThr

UART TX interrupt FIFO threshold select

rxIntFifoThr

UART2CC32XX_FifoThreshold UART2CC32XX_HWAttrs::rxIntFifoThr

UART RX interrupt FIFO threshold select

rxDmaChannel

uint32_t UART2CC32XX_HWAttrs::rxDmaChannel

uDMA channel for RX data

txDmaChannel

uint32_t UART2CC32XX_HWAttrs::txDmaChannel

uDMA channel for TX data

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The documentation for this struct was generated from the following file:

• UART2CC32XX.h