Hardware Architecture¶
The CC23xx¶
Arm Cortex-M0+ (Device Core)¶
The device core (CM0+) is designed to run the wireless protocol stack from the radio layer up to the user application. By only using one core for the solution, the CC23xx family is optimized for both cost and power.
Flash, RAM, and Peripherals¶
Depending on the model, devices in the CC23xx family contain between 256 kB-512 kB of in-system programmable flash memory and 28 kB-36 kB of SRAM. See the table below for a breakdown each device. The CC23xx also hosts a full range of peripherals including UART, I2C, I2S, AES, RNG, temperature and battery monitors, timers, and 1 SSI.
CC2340R2 |
CC2340R5 |
CC2340R5-Q1 |
|
|---|---|---|---|
Flash |
256 kB |
512 kB |
512 kB |
SRAM |
28 kB |
36 kB |
36 kB |
Programming Internal Flash With the ROM Bootloader¶
The CC23xx internal flash memory can be programmed using the bootloader located in device ROM. Both UART and SPI protocols are supported. See the CC23xx SimpleLink Wireless MCU Technical Reference Manual for more details on the programming protocol and requirements.
Note
Because the ROM bootloader uses predefined DIO pins for internal flash programming, allocate these pins in the board layout. The CC23xx SimpleLink Wireless MCU Technical Reference Manual has more details on the pins allocated to the bootloader based on the chip package type.
Startup Sequence¶
For a complete description of the CC23xx reset sequence, see the CC23xx SimpleLink Wireless MCU Technical Reference Manual.
